DIP

IP Verification

DIP

nLint - Rule Checker

DIP 3

Course Objects

Rule DefinitionnLint Utilizing

DIP 4

Rule Definition

Rule GroupCoding styleLanguage ConstructDesign styleDFTSimulationSynthesisHDL translationNaming Convention

DIP 5

Rule 21023

unconventional vector range definitionRange declaration uses descending bit order and zero bound on LSB

module initval;reg clock, reset;wire [1:8] count; //warning on "count[1:8]",

//"count[7:0]" is recommendedendmodule

DIP 6

Rule 21043

(verilog) more than one module in file(vhdl) more than one primary unit in file

See if each source file contains only one module or one primary unit

// File: test.vmodule test(); //file test.v contains only one module

//and the module name should be same//with file name

...endmodule

DIP 7

Rule 22003

bit width mismatch in assignmentSee if there is any width mismatch in assignment statements

wire [3:0] a;wire [2:0] b;assign a = b; //warning on "a" and "b

DIP 8

Rule 22004

bit width mismatch in bitwise operationAny width mismatch in bitwise operation.

module test(result, a, b, c, d);output [1:0] result;input [2:0] a, b; //a, b is 3 bit widthinput [3:0] c, d; //c, d is 4 bit widthreg [1:0] result;always @(a or b or c or d)if ((a+b) > (c+d)) //warning on "a"(3) and "c"(4)elseif ((a+b) == (c+d))result = 'b1;elseresult = 'b11;endmodule

DIP 9

Rule 22008

(verilog) expression connected to port instanceAny expression directly connected to a port of instance

module andtest;wire a,b1,b2;wire c;and and1(c, a, b1+b2);//warning on b1+b2 as port instance;endmodule

DIP 10

Rule 22011

combinational loop22011 will control the behavior of 22013

module andtest( b, c );input b;output c;wire a, b, c;....assign a = c;and and1(c, a, b); //warning on "c->a->c"endmodule

DIP 11

Rule 22013

asynchronous loop

Signal oscillate out of the clock control in asynchronous loop

module counter(count, clk );parameter number = 10;output [3:0] count;input clk;reg [3:0] count;reg i_rst;always @(posedge clk or posedge i_rst) //warning on "count->i_rst->count"if ( i_rst )count < = 0;elsecount < = count + 1;always @( count )if ( count == number )i_rst = 1;elsei_rst = 0;endmodule

DIP 12

Rule 22023

more than one statement per lineIf there are multiple statements on a line

always @(a or inc_dec)begin: COMBINATIONAL_PROCif ( inc_dec == 0)sum = a + 1;elsesum = a - 1;end //good coding style using separate line for each HDL

//statement

DIP 13

Rule 22043

(verilog) implicit port connection(vhdl) implicit port association

Name association used on the port instance list

module testini;...test u_test_0(sel, a, b, c, y); //warning hereendmodulemodule test(sel, a, b, c, y);...endmodule

DIP 14

Rule 22053

gated clockGated clock in the designmodule test ( q, clk, en, reset, d );output q;input clk, en, reset, d;reg q;wire clk, en, reset, d;wire clk_en;and U_and_1(clk_en, clk, en); //warning on "clk_en", is gatedalways @( posedge clk_en or negedge reset )if ( ~reset )q

DIP 15

Rule 22054

Invertor clockInvertor clock in the design

module test ( q, clk, reset, d );output q;input clk, reset, d;reg q;wire clk, reset, d;wire clk_i;inv U_buf_1(clk_i, clk);//warning on "clk_i", clk_i is drived//by a bufferalways @( posedge clk_i or negedge reset )if ( ~reset )q

DIP 16

Rule 22055

buffered clockExplicit buffered clock in the design

module test ( q, clk, reset, d );output q;input clk, reset, d;reg q;wire clk, reset, d;wire clk_i;buf U_buf_1(clk_i, clk);//warning on "clk_i", clk_i is drived//by a bufferalways @( posedge clk_i or negedge reset )if ( ~reset )q

DIP 17

Rule 22089

(verilog) single-bit logical operation on vectors

Single-bit logic operator (&&, ||) taking vectors as operands

module test(.pc(c), .pa(a), .pb(b));input [2:0] a, b;output [2:0] c;reg [2:0] c;always @(a or b)beginif (a && b)//warning on "a" and "b", both of them are //vector; this expression is equal to //"(|a) && (|b)"c = 1;if (!(a || b))//warning on "a" and "b", both of them are//vector; it is equal to "(|a) || (|b)"c = 0;endendmodule

DIP 18

Rule 22161

(verilog) wire not explicitly declaredAll wires are declared explicitly

module test(a, b, c, d, f);input a, b, c, d;output f;//wire f1, f2;assign d = f;and and1(f1, a, b); //warning on "f1", implicit wireor or1(f2, c, d); //warning on "f2", implicit wireor or2(f, f1, f2);endmodule

DIP 19

Rule 22181multiple clock signals

More than one clock signal in a module or an architecture

module block1(clock1,clock2,clock3,reset,count,data,data1,y,y1);input clock1, clock2, clock3, reset, data, data1;always @(posedge clock1 or negedge reset)//clock signal "clock1"beginendalways @(posedge clock2)//warning on "clock2", another clock signalbeginendalways @(posedge clock3)//warning on "clock3", another clock signalbeginendendmodule

DIP 20

Rule 22225clock signal active on both edges

Clock signal that is on both the rising and falling active edge

module block1(clock, reset, count, data, y);input clock, reset, data;output [8:0] count;reg [8:0] count;output y;reg y;initialcount

DIP 21

Rule 22247(verilog) delay in non-blocking assignment

Any delay used in a non-blocking assignment

module test(q, clock, reset, d);output q;input clock, reset, d;reg q;wire clock, reset, d;parameter D_RQ = 1, D_CQ = 2;always @(posedge clock or negedge reset)if (~reset)#D_RQ q

DIP 22

Rule 23002

(verilog) inferred storage not in library(vhdl) inferred storage

Check and report all inferred storages that are not in library

module test(c, a, b);input [1:0] a, b;output [1:0] c;reg [1:0] c;always @(a or b)if (a)c = b; //a latch "c" inferredendmodule

DIP 23

Rule 23007(verilog) case statement not fully-specified(vhdl) case/select statement not fully-specified

Case (select) statement that does not cover all cases and has nodefault

module test(out0, in1, in2, in3, sel);input [1:0] in1, in2, in3, sel;output [1:0] out0;reg [1:0] out0;always @(in1 or in2 or sel)case (sel)2'b00: out0 = in1;2'b01: out0 = in2;2'b10: out0 = in3; //case not full, warningendcaseendmodule

DIP 24

Rule 23011

incomplete sensitivity listAny incomplete sensitivity list

always @(a) //"b" is also sensitive signal, which will cause//simulation problem, warning

c = a + b;

DIP 25

Rule 23013

extra signal in sensitivity listAny extraneous signal in the sensitivity list

always @(in1 or in2 or in3)//"in3" is not referenced in block,//not a sensitive signal, warningout = in1 & in2;

DIP 26

Rule 23015(verilog) illegal assignment in edge-triggered block

Not allowed assignment by default used in an edge triggered block, ex: blocking assignment

always @(posedge clock)begina = b;c = a; // choose BLOCKING, IGNORE_DEPEND;

//block assignment in edge-trigger block will cause//mismatch between pre-synthesis and//post-synthesis simulation

end

always @(posedge clock)begina = b;c = a; // choose BLOCKING, CHECK_DEPEND;

//no warning hereend

suppressed by synopsys compiledirective "synopsys translate_off"

DIP 27

Rule 23016(verilog) illegal assignment in combinational block

Not allowed assignment like non-blocking assignment by default used in a combinational block

always @(in)begina

DIP 28

Rule 23029race condition in sequential logic

Potential race condition due to a signal being updated in one block and, simultaneously, being referenced in another

module test(y1, y2, clk, a, b);output y1, y2;input clk, a, b;reg y1, y2;always @ (posedge clk)begin : firsty1 = a; //"y1" is assigned when "posedge clk"endalways @(posedge clk)begin : secondif (y1 == 1) //"y1" is referenced when "posedge clk", the

//value will depend on simulator, warningy2 = b;elsey2 = 0;endendmodule

DIP 29

Rule 23030race condition in combinational logic

A signal is shared in two blocks under same condition, the simulation result will be implement-dependent and difference

module tt( d2, a, b, sel );output d2;input a, b, sel;wire a, b, sel;reg d1, d2;always @( sel or a or b )if ( sel )d1 = a;elsed1 = b; // "d1" assigned under @(a) when (!sel)always @( sel or a )if ( sel )d2 = ~a;elsed2 = ~d1; // "d1" referenced under @(a) when (!sel)endmodule

DIP 30

Rule 23031

(verilog) Z or X used in conditional expression

Usage of 'x' or 'z' in conditional expression

(vhdl) metalogic value in conditional expression

Metalogic values used in conditional expression

module test(dataout, s, datain);parameter WIDTH = 4;output dataout;input s;input [WIDTH-1:0] datain;reg dataout;always @(s or datain)beginif (s == 'bz)//"'bz" in conditional expression, warningdataout = datain[0];elseif (s == 'bx)//"'bx" in conditional expression, warningdataout = datain[1];elseif (s == 'b0)dataout = datain[2];elsedataout = datain[3];endendmodule

DIP 31

Rule 23053

(verilog) UDP instance not synthesizable

UDP invocation because it cannot be synthesized

module testing;reg a, b, cin;wire sum;test u_test_0(sum, cin, a, b);//non-synthesizable, warningendmoduleprimitive test(sum, cin, a, b);output sum;input cin,a,b;table0 0 0 : 0;0 0 1 : 1;0 1 0 : 1;0 1 1 : 0;1 0 0 : 1;1 0 1 : 0;1 1 0 : 0;1 1 1 : 1;endtableendprimitive

DIP 32

Rule 23057

(verilog) initial block not synthesizableAny initial block cannot be synthesized

initial //non-synthesizable, warningbegin....end

DIP 33

Rule 23059

(verilog) task not synthesizableAny task used because it cannot be synthesized

task multiply; //non-synthesizable, warningbegin...endendtask

DIP 34

Rule 23075

(verilog) delay ignored by synthesisAny delay which may cause difference between simulation result of pre-synthesis and post-synthesis

and #(3,5) and_test(c, a, b);//ignored by synthesizer, warning

DIP 35

Rule 23131(verilog) operation on X/Z not make sense

Any operation performed on metalogic value X/Z or directly assigned by X/Z, which will cause simulation mismatch between pre-synthesis and post-synthesis

module test( a, b );input b;output a;wire c;assign c = 1'bz;//warning here, Z is directly assigned to some signalassign a = b & 1'bx | c; //warning here, X is operatedendmodule

DIP 36

Rule 24001(verilog) VHDL reserved words

Check any VHDL reserved word useddo not use VHDL reserved words to avoid translation error VHDL reserved words:

"abs", "access", "after", "alias", "all", "and","architecture", "array", "assert", "attribute", "begin", "block","body", "buffer", "bus", "case", "component", "configuration","constant", "disconnect", "downto", "else", "elsif", "end","entity", "exit", "file", "for", "function", "generate", "generic", "group", "guarded", "if", "impure", "in","inertial","inout", "is", "label", "library", "linkage", "literal", "loop","map", "mod", "nand", "new", "next", "nor", "not", "null", "of","on", "open", "or", "others", "out", "package", "port","postponed", "procedure", "process", "pure", "range", "record","register", "reject", "rem", "report", "return", "rol", "ror", "select", "severity", "shared", "signal", "sla", "sll", "sra", "srl", "subtype", "then", "to", "transport", "type","unaffected", "units", "until", "use", "variable", "wait","when", "while", "with", "xnor", "xor"

DIP 37

Rule 24003(vhdl) Verilog reserved words

Do not use Verilog reserved words to avoid translation error Verilogreserved words:

"always", "and", "assign", "begin", "buf", "bufif0", "bufif1", "case", "casex", "casez", "cmos", "deassign", "default", "defparam", "disable", "edge", "else", "end",? "endcase", "endmodule", "endfunction", "endprimitive", "endspecify", "endtable", "endtask", "event", "for", "force", "forever", "fork", "function", "highz0", "highz1", "if", "ifnono", "initial", "inout", "input", "integer", "join", "large", "macromodule", "medium", "module", "nand", "negedge", "nmos", "nor", "not", "notif0", "notif1", "or", "output", "parameter", "pmos", "posedge", "primitive", "pull0", "pull1", "pullup", "pulldown", "rcmos", "real", "realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "scalared", "small", "specify", "specparam", "strong0", "strong1", "supply0", "sypply1", "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand", "trior", "trireg", "vectored", "wait", "wand", "weak0", "weak1", "while", "wire", "wor", "xnor", "xor

DIP 38

Rule 24007

(verilog) names distinguishable in letter case onlyAny pair of names that differ in cases only

module test;reg reg1, reg2, reg3, REG1, Reg2, WIRE1;//warning "REG1""reg1"...wire wire1, wire2, wire3, Wire2, tEst;//warning "tEst""test"...Test u_Test(wire3, reg3);Test u_TEST(wire1, reg1); //warning "u_TEST""u_Test"endmodule

DIP 39

Rule 24015

unknown synopsys directiveCheck any unknown synopsys directive being used

module test(); // synopsys aaa warning hereendmodule

DIP 40

nLint UtilizationMain frame of nLint

Import fileof *.v, *.fHierarchy undercompilation

DIP 41

nLint Profile

Report ViewerCode violation enclosed by rectangular box

Rule OrganizerChoose the rules for code checking

DIP 42

Quick Start on nLint

Unix-like command line

> nLint guiStart nLint GUI interfaceUse File->Import Designto specify your design

Import Design

DIP 43

Import Design

press OK to import file

File-> Import Design-> From File

Select our design file(e.g. *.v, *.f)

DIP 44

Open Another Window

Choose file by left click -> Open

Edit different files on another window

mouse left click

DIP 45

Unchecked File

Check/uncheck bottom

Choose files that dont want to be rule checking

choose the file

click the bottom

DIP 46

Hierarchy View

Expand the design hierarchically

Need to wait for compiling time

DIP 47

Rule Organizer

Choose the rules that we want to check

Rules store by different groupsSome rules distribute into two or more groups

rule organizer

group page

DIP 48

Rule Specification

Select rule by mouse clickEnable/disable group

enable/disable

synopsys support

DIP 49

LintingRun->lint

Linting our design after rule specified

Violation store byGroupRule numberRule description

DIP 50

Source Modification

Editor windowClick the rule descriptionto allocate the violated code Output window shows the warning and error message

output window

DIP 51

Tool Preference

Tools->PreferenceReport page->General pageChange the report viewer optionsnTrace/nSchema can turn on Debussy for debugging

DIP 52

Appendix Rule List (I)Rule Group Serial No. Rule ContentsCoding Style 21023 unconventional vector range definition

Coding Style 21043 (verilog) more than one module in file

Coding Style 21043 (vhdl) more than one primary unit in fileLanguage Construct 22003 bit width mismatch in assignmentLanguage Construct 22004 bit width mismatch in bitwise operation

DFT, Design Style 22008 (verilog) expression connected to port instanceSimulation, DFT,

Design Style 22011 combinational loopSimulation, DFT,

Design Style 22013 asynchronous loop

Coding Style 22023 more than one statement per line

Coding Style 22043 (verilog) implicit port connection

DIP 53

Rule List (II)Rule Group Serial No. Rule ContentsCoding Style 22043 (vhdl) implicit port associationDFT, Design Style 22053 gated clockDFT, Design Style 22054 invertor clockDFT, Design Style 22055 buffered clock

Simulation, Language Construct

22089 (verilog) single-bit logical operation on vector

Coding Style 22161 (verilog) wire not explicitly declared

DFT, Design Style 22181 multiple clock signals

Design Style 22225 clock signal active on both edgesSimulation, Language Construct

22247 (verilog) delay in non-blocking assignment

Synthesis 23002 (verilog) inferred storage not in library

DIP 54

Rule List (III)Rule Group Serial No. Rule Contents

Synthesis 23002 (vhdl) inferred storageLanguage Construct 23007 (verilog) case statement not fully-specifiedLanguage Construct 23007 (vhdl) case/select statement not fully-specified

Simulation, Synthesis 23011 incomplete sensitivity list

Simulation 23013 extra signal in sensitivity list

Synthesis 23015 (verilog) illegal assignment in edge-triggered

Synthesis 23016 (verilog) illegal assignment in combinational blockSimulation, Language Construct

23029 race condition in sequential logicSimulation, Language Construct

23030 race condition in combinational logicSynthesis,Language Construct

23031 (verilog) Z or X used in combinational expression

DIP 55

Rule List (IV)Rule Group Serial No. Rule Contents

Synthesis,Language Construct

23031 (vhdl) metalogic used in combinational expression

Synthesis 23053 (verilog) UDP instance not synthesizable

Synthesis 23057 (verilog) initial block not synthesizable

Synthesis 23059 (verilog) task not synthesizable

Synthesis 23075 (verilog) delay ignored by synthesis

Simulation 23131 (verilog) operation on X/Z not make senseHDL

Translation 24001 (verilog) VHDL reserved words

HDL Translation 24003 (vhdl) Verilog reserved words

HDL Translation, Naming

Convention24007 (verilog) names distinguishable in letter case

Language Construct 24015 unknown synopsys directive

DIP

VN-Cover Utilization

DIP 57

Course Objects

VN-CoverCode CoverageFSM Coverage

Tool UtilizingVerification FlowSimulationResults Analysis

DIP 58

VN-Cover

Code CoverageStatementBranchConditionPathToggleTriggeringTracing

FSM CoverageStateArcPath

DIP 59

Statement Coverage

Sequential and concurrent assignments100=

)statements executable ofnumber (Totalexecuted) statement of(Number

coverage Statement

DIP 60

Branch Coverage

Branch definition

Branch not takenIf always b=ain test bench

DIP 61

Branch coverage (cont.)

Calculating branch coverage100=

branches) possible of no. (Totaltaken) branches of(Number

coverage Branch

branch taken

DIP 62

Condition Coverage

DefinitionWhich expression in condition be executed

Four types of condition coverageEXPR (Sum-of-Product Expression Coverage)BSC (Basic Sub-condition Coverage)MSC (Multiple Sub-condition Coverage)FEC (Focused Expression Coverage)

expression

DIP 63

EXPR Coverage

Definition (Verilog only)The combination of value to achieve 100% EXPR:

DIP 64

BSC Coverage

DefinitionSub-expression be both true and false

DIP 65

MSC Coverage

DefinitionExplore all sub-condition value combinationsUseful on testing infeasible sub-condition

DIP 66

FEC Coverage

Definition (default for VHDL circuit)testing minimum input combinations which reduced by Boolean expression :

3 inputs need 3+1 tests

FEC vector

DIP 67

Path Coverage

DefinitionSequence statements executed in a particular order (combination of sequential branches)

DIP 68

Path Coverage (cont.)

Infeasible pathsCant achieve 100% path coverageInefficient logic could be merged into one

DIP 69

Toggle Coverage

Full toggledAt least one rising edge and falling edge

DIP 70

Verilog Toggle Type

Toggle typeInit:

Known value at the end

Full :0->[X|Z]->1 or 1->[X|Z]->0 accepted

activity :Only X->0 can start count toggle

DIP 71

Triggering Coverage

DefinitionSignals in the sensitivity listOnly applied in VHDL

DIP 72

Tracing CoverageTrace methodology

Signal names file must be suppliedUtilizing to error condition detection (deadlock, bus contention) of systemSignal names file

Contain the signal information we want to trace

DIP 73

Tracing ResultsTracing example

We use Done and LSB for tracingVN-Cover accumulate the count of traced signals

DIP 74

FSM Coverage

Control functionalityState

Possible state in FSM

ArcTransition between two adjacent states

PathA valid sequence of states

DIP 75

Path CoverageAutomatic recognition

CycleLinkSupercycle : basic traverse unit

DIP 76

State Machine Properties

Preview FSM properties before simulation

select the file within FSM

State Machine Properties

DIP 77

FSM ExtractionPreview state machine diagram and state path

DIP 78

FSM Path DiagramUse codeview option to display path diagram

Tool utilization (page 35 & 36)

DIP 79

State and Arc Analysis

choose the recognized cycle

chose cycle will be highlight

Path view informationBlack color : not attached supercycleGreen color : attached supercycle, and be traversedRed color : not attached supercycle, and fail traverse

DIP 80

Verification FlowVerification flow of VN-Cover

Set simulator & librarySelect property optionRun simulationView results

DIP 81

Simulator SelectionWe can choose the suitable HDL and whose simulator (Ex: Cadance Verilog-XL)

DIP 82

VN-Cover OptionSelect the Verilog+ to include the top level module

DIP 83

HDL Files LoadingCode and FSM default value

VN-Cover set default options for verification

code within FSM

DIP 84

Coverage Criteria

1. select files

2. select coverage criteria

Select coverage criteriaChoose all the module exclude the test module

DIP 85

Instrument

Instrument HDL filesProduce command file (vnavigator.f) for simulation

default value

DIP 86

Specify Test BenchVerilog HDL

Using command file (vnavigator.f) produced at previous step

choose command file

DIP 87

SimulationProduce results

Progress reported in Log windowNotice the Note and message in the log window

DIP 88

Results StageLoad results files

We load the file of simulation result (default: vnavigator.index)

DIP 89

Loading Result FileCoverage results

Blank means no such coverage for analysisRed proportion means the unfilled coverage (not achieve 100%)

DIP 90

Results Analysis

module hierarchy for code view

code classify

DIP 91

Code View and DetailCode View

Display the coverage belong to statementChoose the coverage in Metrics View can display drawback code in Code View

DIP 92

Detail View

Coverage informationRed line indicate untested situationCoverage = really test / should be test

IP VerificationnLint - Rule CheckerCourse ObjectsRule DefinitionRule 21023nLint UtilizationnLint ProfileQuick Start on nLintImport DesignOpen Another WindowUnchecked FileHierarchy ViewRule OrganizerRule SpecificationLintingSource ModificationTool PreferenceAppendix Rule List (I)Rule List (II)Rule List (III)Rule List (IV)VN-Cover UtilizationCourse ObjectsVN-CoverStatement CoverageBranch CoverageBranch coverage (cont.)Condition CoverageEXPR CoverageBSC CoverageMSC CoverageFEC CoveragePath CoveragePath Coverage (cont.)Toggle CoverageVerilog Toggle TypeTriggering CoverageTracing CoverageTracing ResultsFSM CoveragePath CoverageState Machine PropertiesFSM ExtractionFSM Path DiagramState and Arc AnalysisVerification FlowSimulator SelectionVN-Cover OptionHDL Files LoadingCoverage CriteriaInstrumentSpecify Test BenchSimulationResults StageLoading Result FileResults AnalysisCode View and DetailDetail View