jcap company profile feb, 201528,000 m2 (fab-2) jcap confidential jan 2015 2 employees : 725...

江阴长电先进封装有限公司JIANGYIN CHANGDIAN ADVANCED PACKAGING CO., LTD.

JCAP Confidential Jan 2015 20th April, 2004JCAP Confidential


Company OverviewEstablishment : 2003, August

Shareholder: JCET 75%, APS & others, 25%Shareholder: JCET 75%, APS & others, 25%

Business focus: Wafer Bumping

Wafer Level CSP

Wafer Level Sensor

Si/Glass Level Packaging

Pl t 9 000 2 (F b 1)Plant area : 9,000 m2 (Fab-1)

28,000 m2 (Fab-2)

JCAP Confidential Jan 2015 2

Employees : 725 (Fab-1)/ 115 (Fab-2)


Company Milestones

Formation of JCAP Cu pillar and RDL production

300mm bumping production

2003 2005 2008 2010 2012

2004 2006 2009 2011

2014

Double RDL production

J-WLP (C2W) developed

2015

Encapsulated chip package developed

Completed building. Reach 80kk /month Set up TSV line for Set up FC & RFID line New 12” production linep gSet up bumping line in WLCSP Sensors (Ready by end of 2014)


Passed ISO9001

Passed 14001

Passed TS16949

Passed QC080000

Passed SONY GP 2009 TI SEA award 2011 TI SEA award


Organization Structure



Our Focus- Advanced Packaging ( Middle End )

Wafer Wafer BumpingBumping( ( AuBAuB, , SnBSnB, , CuPCuP, , CuBCuB, , uCuPuCuP…)…)

Flip Chip/ TSVFlip Chip/ TSV// InterposerInterposerWafer Level PackagingWafer Level Packaging

FI WLP FO WLPFC BGA

FC ICsFC ICsBOPBOP Optic WLP J-WLP

2D/2.5D/3D ICsIntegration

2D/2.5D/3D ICsIntegration

2D/2.5D/3D SiIntegration

2D/2.5D/3D SiIntegration

FI WLP Embedded

2P1M2P1M MEMS WLP FC LDF

FC FilmIPD IPD

EmbeddedEmbedded

WLFO

FO -SiP

uCuP Bump

TemporaryBond/ Debond

FC SiP

Embedded

RDL RDL -- FI WLPFI WLP33P3MP3M

FC Film

Stacked/CC2W2W/C2C Assembly2P2M2P2M

EmbeddedEmbedded

FO -3D

Si-CSM(2D)

M2M, SiO/SiO etc. Bonding

SiSi/Glass Interposer

3P2M3P2M 4P3MW2W AssemblyCOF/COG

JCAP Confidential Jan 2015

Mass ProductionMass Production In development Development 1.Key 1.Key technology, 2.Integrationtechnology, 2.Integration, , 3. Patent3. Patent


Wafer Bumping ServicesPad RedistributionP l i id /PBO C TPolyimide/PBO, Cu TraceThin Film with Passive ComponentIPD Min W/S：9x7umApplication: IPD/RDL

Solder Plating

Solder Ball DropSAC material

Gold Bumping

Std height: 5um – 18um

Pitch:>30um

Electroplating Sn/SnAgPitch: >160umApplication: FCOS/FCOL

Application: COF/COG/RFID

Pillar PlatingStd structure :65um Cu + 25um Sn/SnAg

before reflowENIG PlatingStd structure: Ni/Au on Al or Cu


Pitch: >160um (>40um for fine pitch)Application: High density interconnect for FCOS/FCOL

Std structure: Ni/Au on Al or CuApplication: UBM, RDL for flip chip connection or wire bonding


JCAP CuP / CuB Various Structure

2P2M Pillar Bump

Standard Pillar Bump1P2M Pillar Bump

Any Shape Pillar BumpCu on Via Pillar Bump


Note : (X)P(Y)M denotes X layers of Polyimide and Y layers of Metal.

Micro Pitch Pillar BumpAny Shape Pillar Bump


Flip Chip on Lead frame

Silicon Die

Cu Pillar

L/F

FCOL with copper pillar bump offers:L i d d i iLower inductance and resistance propertiesHigher efficiency, dissipate less powerHigh current density carrying capacityLow cost ( replacing gold wire)


Exposed die possible for high current as high to 50A


Flip Chip on Substrate

Solder Bumps Micro Cu Pillar 54um Pitch

COS i i ff

p‐ 200um Pitch

Micro Cu Pillar ‐ 54um Pitch

FCOS with copper pillar bump offers:High power High frequencyHigh frequencyLow parasitic resistance, capacitance, inductanceFine pitch available down to 54um bump pitch


p p p


Bumping & Packaging Fully Turnkey Wafers from

customers or fabShip to customers or their end users

JCAP internal process

UBM **Backside CoatBy JCAP/customer

ForwarderBy JCAP/customer

Forwarder

Electroplating

Back grinding

**Laser Marking

Dicing / Laser Grooving

Flip Chip Assembly & Test

Ball PlacementSorting(TnR)

Probing


Packing


Wafer Level CSP Structure

**

**

**

CSP － 3P3M

CSP － 2P1M

CSP － 2P2MStandard design:

CSP 3P3MStandard design:

1st PI: 5/10um

2nd PI:5/10um

CSP － 1P1MStandard design:

P.I: 5um/10um

CSP 2P1MStandard design:

1st PI: 5um

2nd PI:10um

g

1st PI: 5um

2nd PI:10um

Cu trace:3~7.5um

3rd PI:5/10um

1st Cu trace:3~7.5um

2nd Cu trace:3~7.5umCSP － 1M

Standard design:


UBM:7.5um Cu trace:7.5um UBM:7.5um UBM:7.5umUBM:7.5um


JCAP WLCSP Process CapabilityFor Do ble RDL ProcessFor Double RDL Process

8.60um 8.40um 8.53um6.81um

8.36um8.33um8.40um 7 14um7.14um

Two layers RDL 9um line width/7um line space


Two layers RDL 9um line width/7um line space


2005 2007 2008

For Ball Drop Capability 2005Ball pitch: 500umBall size: 300umStatus: Mass Production

2007Ball pitch: 400umBall size: 250umStatus: Mass Production

2008Ball pitch: 350umBall size: 150umStatus: Mass production

2009Ball pitch: 300umBall size: 150um

2010Ball pitch: 250umBall size: 120um

2013~2014Ball pitch: 150umBall size: 80um

Status: Mass Production

Status: Ready for production

Status: Finish development

99.2um

400um pitch WLCSP 300um pitch WLCSP250 it h WLCSP 400um pitch WLCSP 300um pitch WLCSP250um pitch WLCSP



For Thin Wafer Process capability

Ball Placement Taping Back grinding De-tapingUBMThin wafer process: ball placement followed by back grinding. Wafer thickness can be thinned to ~180um for 12” wafer.

Taping Back grinding De-taping Ball PlacementUBMNormal thickness wafer process: back grinding followed by ball placement. Wafer thickness can be thinned to ~250um.

167um 356um


42.3um


For Laser Grooving Capability

After Laser Groove After Blade Cut Front side After Blade Cut Backside

Laser Grooving + Blade Cut

Reliability test

Dry Bake + MSL3 + 255℃ 3x reflow HTS T1008 THS T1008 TC T1000

(0/231) (0/77) (0/77) (0/77)Note: Electrical function test with die level socket was applied to define


Note: Electrical function test with die level socket was applied to define the test vehicle pass or fail the reliability test.


JCAP WLCSP Production Device StructureBall Ball Die Size Ball Ball Ball Height/Size Package Structure StatusArray Pitch Count Size after reflow Thickness

1x2 240um 0.21x0.41mm 2(bump) NA 11um bump height(No reflow)

185um 1P1M Qualification

1 2 400 0 3X0 6 2(b ) NA 11 b 290 1P1M M P d i1x2 400um 0.3X0.6mm 2(bump) NA 11um bump height(No reflow)

290um 1P1M Mass Production

2x2 350um 0.65x0.65mm 4 150um 105um/180um 295um 1P1M Mass Production

2 2 400 0 77 0 77 4 100 50 /150 280 2P2M M P d ti2x2 400um 0.77x0.77mm 4 100um 50um/150um 280um 2P2M Mass Production





5x5 500um 2.42X2.42mm 9 300um 195um/270um 490um 2P1M Mass Production




JCAP WLCSP Production Device StructureBall Ball Die Size Ball Ball Ball Height/Size Package Structure StatusBall Array

Ball Pitch

Die Size Ball Count

Ball Size

Ball Height/Size after reflow

PackageThickness

Structure Status

7x7 530um 3.49x3.49um 49 200um 160um/210um 460um 2P2M Mass Production

7x8 480um 3 89x3 89mm 56 250um 202um/257um 580um 2P1M Mass Production7x8 480um 3.89x3.89mm 56 250um 202um/257um 580um 2P1M Mass Production

8x8 400um 3.18x3.18mm 64 250um 185um/275um NA 1P1M Mass Production


9 11 400 3 74 4 44 99 250 210 /260 530 1P1M M P d ti9x11 400um 3.74x4.44mm 99 250um 210um/260um 530um 1P1M Mass Production

10x10 500um 5.06x5.06mm 100 300um 235um/320um NA 2P2M Mass Production




Wafer Level CSP for SensorsV-A Structure

V-B StructureReady by end of 2014

V-A: Laser drill process with side contact

V-B: Dry etching with PECVD, full PAD contact


y g ,


Fingerprint Packaging

TSV Structure

Trench + WB


Trench + WB


J-WLP (Chip to Wafer)

Micro bump interconnection C2W Flip Chip Technology

Solder ballDaughter chip

Multi-RDL&IPD integration


J-WLP Package


JCAP Testing ServiceJCAP i t l bilit t d i d k b■ JCAP internal capability to design and make probe cards, eliminating the inconvenience of maintenance and repairing outside and shortening the cycle timeand repairing outside and shortening the cycle time

■ JCAP internal capability of programming

■ Tester ListEagle ETS300/364, Credence ASL1000, AST 2000, Juno DTS1000, FET3600

Agilent V50, Nextest ST64, micro/ultra Flex, T2K…

Laser Trimming Capable: ESI9820

Prober: UF3000,UF200A,UF200SA/190B>150sets



Proportional Revenue by Regions

81.01%75.36% 73.88%

2012 2013 2014

0.02% 2.99% 2.90%

2012 2013 2014

17.67% 16.99% 18.81%

2012 2013 2014

1.30%4.66% 4.42%

2012 2013 2014


America Europe China Korea


Volume Production Customers



CSP & Flip Chip Coverage



What’s more…



Shipment Record for Bumping

•Totally more than 2.2M wafers output till 2013


•1M wafers bump in 2014


Shipment Record for Assembly

•Totally more than 8.8B units output till 2013


•Over 3B forecast in 2014


Manufacturing CapacityCu Pillar and Bumping:FAB 1

• 140,000 wafers/m for 8inch

5 000 f / f 12i h5,000 wafers/m for 12inch

FAB 2

• Ready for qual by Q2 2015, with 40,000Ready for qual by Q2 2015, with 40,000 wafers/month of Phase I plan

WLCSP Backend :420kk/m, expanded to 500kk/m by Q2, 2015

Wafer Level for TSV products (80~90 degree ):• 10,000pcs wafers/month for 8inch

FC for RFID:50M units/month


50M units/month


JCAP New B2 Plant

•Located 10 km from current JCAP B1 plantLocated 10 km from current JCAP B1 plant•Three floors, totally 28,000 square meters•Total plan capacity, more than 300,000 pcs for 8” and 12” wafers•World class FAB with fully automatic operation system


•World class FAB with fully automatic operation system

jcap company profile feb, 201528,000 m2 (fab-2) jcap confidential jan 2015 2 employees : 725...

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