Lab. II - 1

Lab. IIVerilog-XL 을 이용한 SimulationLab. IIVerilog-XL 을 이용한 Simulation

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IntroductionIntroduction

Hardware Description Language(HDL)a programming language that can describe the

functionality and timing of hardware circuitsVerilog, VHDL, etc

Simulatorsoftware which reads the HDL and emulates the

hardware described by the HDLVerilog-XL

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Different Levels of AbstractionDifferent Levels of Abstraction

Architecture / Algorithmicdescribed in the terms of the algorithms it performs

Register Transfer Logic(RTL)describes the flow of data and control signalsschedules assignments at clock edges

Gate interconnection of switch elements(or gates) to check

functionality, performance, or timing of design

Switchdescribes logic behavior of transistor circuits

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Major Data Type ClassesMajor Data Type Classes

Nets represent physical connection between devices

Registers represent abstract storage devices

Parametersdeclare run-time constants

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NetsNets

continuously driven by the device that drive themVerilog automatically propagate a new value onto a net

when the drivers on the net change value types of nets : wire, tri, etc.

Nets

reg_a

reg_sel

reg_b

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RegistersRegisters

holds its value until a new value is assigned to it.used extensively in behavioral modeling and in

applying stimuli.values are applied to registers using behavioral

constructs. types of registers : reg, integer, real, time

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ValuesValues Value can be sized or unsized

default size : 32 bitsdefault base : decimal

Examples

<size>’<base><value>

where

<size> is the size in bits

<base> can be b(binary), o(octal), d(decimal) or h(hexadecimal)

<value> is any legal number in the selected base or x, z, ?

12‘h83a8’b1100_000164’hff019’o1732’bz

Unsized decimalunsized hexadecimal8-bit binary64-bit hexadecimal9-bit octal32-bit Z(X and Z values are automatically extended)

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4-Value Logic System in Verilog4-Value Logic System in Verilog

Zero, Low, False, Logic Low, Ground, VSS, Negative assertion

One, High, True, Logic High, Power, VDD, VCC, Positive assertion

X, Unknown : Occurs at logical conflict which cannot be resolved

HiZ, High impedence, Tri-Stated, Disabled Driver

‘0’

‘1’

‘x’

‘z’

‘0’

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Continuous AssignmentsContinuous Assignments

Continuous assignmentssyntax : <assign> <#delay> <net_name> = <expression>are outside of a procedural block the LHS is updated at any change in the RHS expressioncan model combinational logic with continuous

assignments instead of using gates and interconnect net

Exampleassign #1 z = A & B;

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Operators in Verilog AssignmentsOperators in Verilog Assignments

Givena = 1010, b = 0000, c = 0011

Unary operatorsbit-wise negation : ~a = 0101, ~b = 1111 logical negation : !a = 0, !b = 1unary reduction : &a = 0, &b = 0, |a = 1, |b = 0, ^a = 1, ^b = 0

Binary operatorsbit-wise : a | c = 1011, a & c = 0010 logical : a||c = 1, a&&c = 1

Equality operators== : equality operator

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OperatorsOperators

Conditional operatorsSyntax :<LHS> = <condition> ? <if_expression> : <else_expression>example

assign muxout = (sel == 1’b1) ? A : B;

Concatenation and replication operatorsconcatenation assign #102 {co,sum} = a + b + ci; replication assign byte = {4{2’b01}}; // generate 8’b01010101 assign word = {{8’{byte[7]}}, byte}; // sign extension

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Conditional StatementsConditional Statements

if and if-Else statements Case Statement

if (index == 0 ) begin $display(“Index is zero”); result = regb; endelse begin $display(“Index is non-zero”);end

case(opcode) 3’b000: result = rega + regb; 3’b001: result = rega - regb; 3’b010 , 3’b100: result = rega / regb; default: begin

result = ‘bx; $display(“no match”);end

endcase

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Procedural BlocksProcedural Blocks Procedural blocks are the basis for behavioral

modeling.

Procedural blocks are of two types: initial procedural blocksalways procedural blocks

Procedural blocks have the following componentsprocedural assignment statementshigh level constructs timing controls

alwaysbegin

end

S0:S1:

initialbegin

end

S0:S1:

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Block StatementsBlock Statements

Sequential block statements :enclosed between the keywords begin and end.executed in a sequential manner

Parallel block statements :enclosed between the keywords fork and join.executed concurrently

alwaysbegin

end

S0:S1:

alwaysfork

join

S0:S1:

initialbegin

end

S0:S1:

initialfork

join

S0:S1:

S0->S1 S0,S1 S0->S1 S0,S1

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Procedural AssigmentProcedural Assigment

Assignments made inside procedural blocks the LHS of a procedural assignment : a register-class

data type(reg) the RHS of a procedural assignment : any valid

expression and any data type(wire, reg)

module dff (q, qb, d, clk ); output q, qb; input d, clk; reg q, qb;

always @(posedge clk) begin#5 q = d;#1 qb = ~d;

endendmoule

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Timing Control in Procedural BlocksTiming Control in Procedural Blocks

Simple delay

Edge-Triggered timing control

Level-triggered timing control

#10 rega = regb;#(cycle/2) clk = ~clk;

@(r or q) rega = regb; // triggered by either edge of “r” or “q”@(posedge clk) rega = regb; // triggered by positive edge of clk@(negedge clk) rega = regb; // triggered by negative edge of clk

Wait (!enable) rega = regb; // will wait until enable = 0;

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Declaration Syntax and Choosing Correct Data TypeDeclaration Syntax and Choosing Correct Data Type Declaration syntax of Verilog nets and registers

Choosing correct data type

reg a; // a scalar registerwire w; // a scalar netreg [2:0] v; // a 4-bit vector registerreg [7:0] m, n; // two 8-bit registerswire [31:0] w1, w2; // two 32-bit nets

net/register netnet

net

net net/register

Output portInput port

Module Boundary

Inout port

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Common Mistakes in Choosing Data TypesCommon Mistakes in Choosing Data Types When a procedural assignment is made to a net or

you forget to declare a signal as a reg:“Illegal left-hand-side assignment”example

Signal connected to the output port is a register:“Gate has illegal output selection”“Illegal output port specification”example

module dff( d, clk, q );input d, clkoutput q;

always @(posedge clk) q = d;endmodule

module test;reg q;reg clk, d;dff mydff( .d(d), .clk(clk), .q(q) );endmodule

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Module InstantiationModule Instantiation

A module instantiation must have an instance name.

In positional mapping, port order follows the module declaration.

In named mapping, port order is independent of the position.module comp (o1, o2, i1, i2); output o1, o2; input i1, i2;

…endmodulemodule test; comp c1 ( Q, R, J, K ); // positional mapping comp c2 ( .i2(K), .o1(Q), .o2(R), .i1(J) ); // named mapping comp c3 ( Q, , J, K ); // one port left unconnectedendmodule

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Text Substitution and InclusionText Substitution and Inclusion

Text substitution `define <macro_name> <macro_text>

Text inclusion `include “global.v”

Examples`include “global.v”`define NOT_DELAY 1

module MUX2_1(out, a, b, sel);output out;input a, b, sel; not # `NOT_DELAY not1 (sel_, sel); and #2 and2 (a1, a, sel_); ...

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Behavioral ModelingBehavioral Modeling

Enables you to describe the system at a high level of abstraction.

Is described by specifying a set of concurrently active procedural blocks

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Special Language TokensSpecial Language Tokens

System tasks and functions$<identifier>

`$` sign denotes verilog system tasks and functions

example : $time, $display, $monitor, $stop, $finish

#<delay specification>`#` character denotes the delay specificationexamplemodule MUX2_1(out, a, b, sel);

output out;input a, b, sel; not #1 not1 (sel_, sel); and #2 and2 (a1, a, sel_); …endmodule

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Displaying Signal ValuesDisplaying Signal Values

$displayprints out the current values of the signals in the

argument listautomatically prints a new line $display ( “<format_specifier>”, <argument_list> )supports different bases

$display, $displayb, $displayo, $displayh format specifiers:

escaped literals

%h %o %d %b %c %shex octal decimal binary ASCII string

\t \n \\ \”tab new line backslash double quote

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Displaying Signal Values(cont.)Displaying Signal Values(cont.)

$write identical to $display except that it does not print a new

line charactersupports different bases

$write, $writeb, $writeo, $writeh

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Displaying Signal Values(cont.)Displaying Signal Values(cont.)

Example

module textio; reg flag; reg [31:0] data;

initial begin $writeb(“%d”, $time,, “%h \t”, data,, flag, “\n” ); #15 flag = 1; data = 16; $displayh($time,, data,, flag ); end

initial begin #10 data = 20; $display($time,, data ); data = 30; endendmodule

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Monitoring Signal ValuesMonitoring Signal Values

$monitordisplays the values of the argument list whenever any

of the argument change.supports different default bases:

$monitor, $monitorb, $monitoro, $monitorhexample

$monitor($time, “%b \t %h \t %d \t %o”, sig1, sig2, sig3, sig4 );

$monitor($time, “%b \t”, sig1, “%h \t”, sig2, “%d \t”, sig3, “%o”, sig4 );

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Debugging with SimWaveDebugging with SimWave

System tasks $shm_open(“lab.shm”);

open a simulation database

$shm_probe();select signal whose simulation value changes will enter the simulation database

$shm_close;closes a simulation database

$shm_save;saves a simulation database to task

Initialbegin

$shm_open(“file.shm”);$shm_probe();#1 $stop;// stop simulation at time 1

end

Examples of node specifers $shm_probe(); $shm_probe(alu, adder); $shm_probe(“AS”);

Example

“A” : all node of the specified scope“S” : in, out, inout of the specifiedscope, and in all instantiations below it“C”, “AS”, “AC”

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Using SimWaveUsing SimWave

Open the waveform window wd &

File -> Database -> Load

$shm_open(“file.shm”);

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Using SimWave (cont)Using SimWave (cont)

Edit -> Add Signal

Double clickleft button

select and click-dragthe middle button

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Verilog-XL in the Interactive ModeVerilog-XL in the Interactive Mode

$stop : cause entry into interactive mode

^C : cause entry into interactive mode

$finish : end the simulation

^D : end the simulation

. : continue

$db_help : list and describe the source-level debug commands

$showvars : display status information on variables

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ReferenceReference

Verilog-XL 교육 자료 IC Design Education Center (1998.12.22 ~ 12.24)

Verilog-XL Reference Manual (Vol.1, Vol.2)Cadence

The Verilog Hardware Description LanguageDonald E. Thomas and Philip MoorbyKluwer Academic Publishers

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MISC (Minimal Instruction Set Computer)MISC (Minimal Instruction Set Computer) RISC (Reduced Instruction Set Computer)

Simple hardware 에 의한 clock speed 증가앞으로의 발전 가능성

1) instruction parallelism 을 이용 : VLIW2) 다양한 RISC 명령어를 제한하여 성능 향상 :

MISC

MISC 란초기의 RISC 개념을 사용

1) 현재 RISC 는 초기의 간단한 명령어 집합의 개념에서 벋어나 많은 명령어를 사용한다 .

2) 하드웨어 리소스를 감소프로세서의 구조를 간단히 하여 성능을 향상

1) interrupt, exception, stall 등의 예외 상황을 없애거나 줄인다 .

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MISCMISC

MISC 의 사용 용도controller 또는 제어용 mini computer

MISC 의 적용 분야High speed communication systems Intelligent hard disk controllersRobotic controller

MISC 제작 history제 1 회 IDEC MPW

1) 0.8um SOG (Samsung 공정 ) IDEC-C631 개발

1) 0.6um TLM (LG 공정 )2) test chip 으로 이용3) Test program 과 board 를 통한 동작 확인

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MISC Instruction SetMISC Instruction Set Type 0 - move long

imm[14:0] 을 ra 에 저장ra[15] 는 imm[14] 와 같음

Type 1 - move

mode:100 (move rdst,rsrc)rsrc 의 값을 rdst 로 move

mode:010 (move mbr, [r])외부 메모리 값을 mbr 에

저장mode:001 (move [r],rsrc)

rsrc 의 값을 외부 메모리에 저장

Type 2 - alu

func:100 (add)src1 = src1 + src2

func:001 (adc)src1 = src1 + src2 + CF

func:010 (sub)src1 = src1 - src2

func:011 (sbb)src1 = src1 - src2 - CF

func:100 (and)src1 = src1 & src2

func:101 (or)src1 = src1 | src2

func:110 (xor)src1 = src1 ^ src2

func:111 (cmp)src1 - src2

0 imm15

1 00 mode x x src1 src2

1 10 func x x src1 src2

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MISC Instruction Set (cont)MISC Instruction Set (cont)

type 3 - shift & mul

func:000 (rol)src1 = {src2,src2}<<samt

func:001 (ror)src1 = {src2,src2}>>samt

func:010 (shl)src1 = src2 << samt

func:011 (shr)src1 = src2 >> samt

Type 4 - control

funcjcc : 00x (conditional)jmp : 01x (unconditional)call : 10xret : 11x

cond== (000) : equal!= (001) : not equal>= (010) : greater than or equal<= (011) : less than or equal> (100) : greater< (101) : less thanOF = 1 (110) OF = 0 (111)

1 11 func x x src1 src2 1 01 func x x cond src2

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RegistersRegisters

special registers r0(0x0) - read only r1(0xffff) - read only r2(0x8000) - read only r3(shift amount) - read /

write, 하위 4 비트만 valid r4(npc) - not accessible,

PC+1 의 값을 저장 r5(flag) - read only

type2 instructions update flagCF : carry flagZF : zero flagOF : overflow flagSF : sign flag

r6(pio) - not accessible, parallel port

r7(link) - call 명령어에서 (PC+1) 을 저장 . Return 명령어를 수행할 때 , link register 에 있는 값으로 return 한다 .

general purpose registers 8 16bit general purpose

registers(ra~rh)CFZFOFSFreserved

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Block DiagramBlock Diagram

Decoder

General purposeRegister File

(ra~rh)

ALU

PCBUS

interface

Special Registers(r0~r7)

MBR

Parallel I/O

wb src1 src2

clk

resetDstrobe_

Drw

Ddata

Daddr

Idata

Iaddr

OUTsig

INsig

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System Block DiagramSystem Block Diagram

MISCProcessor

32KROM

32KRAM

clock

LEDpanel

Dstrobe_

Drw

Ddata

Daddr

Idata

Iaddr

OUTsig