verilog hdl.ppt
TRANSCRIPT
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Basic Verilog HDL
By Phan Quoc HuySep 30, 2008
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Agenda
Overview of Digital Design with Verilog HDLBasic conceptsModules
Hierarchical modeling conceptsGate-Level ModelingDataflow ModelingBehavioral ModelingTasks and Functions
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Agenda
Overview of Digital Design with Verilog HDLBasic conceptsModules
Hierarchical modeling conceptsGate-Level ModelingDataflow ModelingBehavioral ModelingTasks and Functions
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Evolution of Computer-Aided Digital DesignVacuum tubes and transitors
Integrated circuit (IC)
Small scale integration (SSI)
Medium scale integration (MSI)
Large scale integration (LSI)
Very large scale integration(VLSI)
Gate count was small
M
o r e s o p
h i s t i c a
t e d
I n c r e a s e
d C o m p u
t e r - a
i d
Hundreds of gates
Thousands of gates EDA began evolve
in logic simulation
>100,000 transistors EDA was critical
BY HAND
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Emergence of HDLs
Digital circuits
Logic synthesis
The need of standardlanguage
HDLs (Verilog, VHDL, )
Programming languages(FORTRAN, C, ) Computer programs
describe
describeDigital Design
Model concurrency inhardware elements
Simulate circuit quicklyusing simulators
Translate to schematiccircuit manually
Use RTL (register transferlevel) design in HDLs
Automatically extractschematic circuit from RTL
c h a n g e
Design methodology:+ Describe complex circuit at abstract level by designing in HDLs+ Logic synthesis tools would implement gates and gate interconnections
Software
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Typical Design FlowDesign Specification
Behavioral Description
RTL Description (HDL)
Functional Verification & Testing
Logic Synthesis / Timing Verification
Gate level netlist
Logical Verification & Testing
Floor Planning Automatic Place and Route
Physical Layout
Layout Verification
Implementation
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Design Specification
Behavioral Description
RTL Description (HDL)
Functional Verification & Testing
Logic Synthesis / Timing Verification
Gate level netlist
Logical Verification & Testing
Floor Planning Automatic Place and Route
Physical Layout
Layout Verification
Implementation
+ Describe the FUNCTIONALITY , INTERFACE , and OVERALL ARCHITECTURE
+ Do not need to think about HOW to implement
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Design Specification
Behavioral Description
RTL Description (HDL)
Functional Verification & Testing
Logic Synthesis / Timing Verification
Gate level netlist
Logical Verification & Testing
Floor Planning Automatic Place and Route
Physical Layout
Layout Verification
Implementation
+ Analyze the design in terms of FUNCTIONALITY , PERFORMANCE ,COMPLIANCE to standards, and OTHER high-level issues
+ Often written with HDLs or EDA tools (combine HDLs and object orientedlanguages such as C++)
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Design Specification
Behavioral Description
RTL Description (HDL)
Functional Verification & Testing
Logic Synthesis / Timing Verification
Gate level netlist
Logical Verification & Testing
Floor Planning Automatic Place and Route
Physical Layout
Layout Verification
Implementation
+ RTL description is manually converted from behavioral description
+ Designers have to describe the DATA FLOW
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Design Specification
Behavioral Description
RTL Description (HDL)
Functional Verification & Testing
Logic Synthesis / Timing Verification
Gate level netlist
Logical Verification & Testing
Floor Planning Automatic Place and Route
Physical Layout
Layout Verification
Implementation
+ Gate-level netlist is converted from RTL description by logic synthesis tools
+ Logic synthesis tools ensure the the gate-level netlist MEETS timing, powerspecifications
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Design Specification
Behavioral Description
RTL Description (HDL)
Functional Verification & Testing
Logic Synthesis / Timing Verification
Gate level netlist
Logical Verification & Testing
Floor Planning Automatic Place and Route
Physical Layout
Layout Verification
Implementation
+ Gate-level netlist is input to an Automatic Place and Route tool to create theLAYOUT
+ The layout is verified and then fabricated on a chip.
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Popularity of Verilog HDL
Verilog, a standard HDL, offers Syntax is similar to C language easy to learnand easy to use Allows different levels of abstraction (switches,gates, RTL, or behavioral code) to be mixed inthe same level Most popular logic synthesis tools supportVerilog Allows the user to write custom C code tointeract with internal data structures of Verilog byusing PLI (Programming Language Interface)
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Agenda
Overview of Digital Design with Verilog HDLBasic conceptsModulesHierarchical modeling conceptsGate-Level ModelingDataflow ModelingBehavioral ModelingTasks and Functions
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Logic value0, 1, x (unknown), z (high impedance)
A 1-bit variable can take any one of these values.(In case of n-bit signal, each bit can take one of these values)
off
on0
Vcc
on
off1
Vcc
off
offz
Vcc
on/off(?)
off/on (?)
Vcc
x
Dont know
x can not be implemented into silicon. On silicon signal must be 0, 1, orz. It can not take the value x.
That is, x has meaning only in simulator
Assignment such as y = 1bx will be neglected by synthesis tool
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Numerical valueliteral integer numbers
10hFA 10 bits hexadecimal number FA (00_1111_1010)
1b0 1 bit binary number 0 (0)
6d30 6 bits decimal number (011110), decimal 30
15o10752 15 bits octal number (001,000,111,101,010),decimal 4586
37 32-bit decimal 37
padding to the left
4b0 is equal to 4b0000
4b1 is equal to 4b0001
4bz is equal to 4bzzzz
4bx is equal to 4bxxxx
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Variables
scalar in_out_controlvector data_in[7:0]
upper_data_out[31:16]
in_out_control
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Variables
Vector part selectIt is possible to address bits or parts of vectorswire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
reg clock; // scalar register, default
reg [0:40] virtual_addr; // Vector register, virtual address 41 bits wide
busA[7] // bit # 7 of vector busA
bus[2:0] //Three least significant bits of vector bus, using bus[0:2] is illegal// because the significant bit should always be on the left of a range// specification
virtual_addr[0:1] // Two most significant bits of vector virtual_addr
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Variables
Variable vector part select[+:width] - part-select increments from starting bit[-:width] - part-select decrements from starting bit
reg [255:0] data1; //Little endian notationreg [0:255] data2; //Big endian notation
reg [7:0] byte;//Using a variable part select, one can choose partsbyte = data1[31-:8]; //starting bit = 31, width =8 => data[31:24]byte = data1[24+:8]; //starting bit = 24, width =8 => data[31:24]byte = data2[31-:8]; //starting bit = 31, width =8 => data[24:31]byte = data2[24+:8]; //starting bit = 24, width =8 => data[24:31]//The starting bit can also be a variable. The width has to be constant. Therefore,//one can use the variable part select in a loop to select all bytes of the vector.for (j=0; j
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Data types
NetsNet data type can be declared by using wire keyword.
Net data types are used to model physical connections.
They do not store values.
The net data types have the value of their drivers. If a net variable hasno driver, then it has a high-impedance value (z).
Net cannot be used as left-hand value of procedural assignments.
wand , wor , tri , triand , trior , tri0 , tri1 , and more keyword areprepared to declare net data type.
However, avoid using those other than wire ,use wire as much as you can
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Data types
Netswire a; // Declare net a for the above circuit
wire b,c; // Declare two wires b,c for the above
Net a will continuously assume the valuecomputed at the output of gate g1
Data type declaration and wire connection declaration can be done in onesentence as shown below.
wire [7:0] q3 = (sel3==1b1)?q1:q2;
However, do not use this expression to avoid troubles. Write typedeclaration and connection separately
wire [7:0] q3;
assign q3 = (sel==1b1)?q1:q2;
In general, avoid type declaration with complex assignment.
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Data typesRegisters
Register data type can be declared by using reg keyword
Register are data types that store assigned values until a newassignment occurs.
A new value can be assigned to registers only by using procedural
assignments.Register data type is intended to declare variables to hold their value,memorize the value.
However, depending the way you program, it may not result in memoryelements.
Write your declaration of reg separately for those memoryelements and for those wiring
reg ff1, ff2, sig1, ff3, sig2; reg ff1, ff2, ff3; // FF output signal
reg sig1, sig2; //combinational logic signals
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Data types
Interger, Real, and Time Register Data Typesdeclaration description
integer 32-bit signed integer variable, integer declarations contain ragespecification.
real
64-bit floating-point variable. Real registers cannot be used withconcatenations ( { } ), case equality (===, !==), bitwise operators,reduction operators, shift operators () and some otheroperators. Bit-selects and part-selects on real type variables arenot allowed
time
64-bit data to store simulation time and to check timing
dependence. Time type registers store values as unsignednumbers. Time declaration cannot contain range specification.
Note: vector declaration for integer, real, and time data types are illegal
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Data types
Arrays Arrays are allowed in Verilog for reg , integer , time , real and vector registerdata types
Multi-dimensional arrays can also be declared with any number of dimensions.
Each element of the array can be used in the same fashion as a scalar orvector net.
Arrays are accessed by []
Note: A vector is a single element that is n-bits wide. On the otherhand, arrays are multiple elements that are 1-bit or n-bits wide.
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Data types Arraysinteger count[0:7]; // An array of 8 count variablesreg bool[31:0]; // Array of 32 one-bit boolean register variablestime chk_point[1:100]; // Array of 100 time checkpoint variablesreg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id is 5 bits wideinteger matrix[4:0][0:255]; // Two dimensional array of integersreg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional arraywire [7:0] w_array2 [5:0]; // Declare an array of 8 bit vector wirewire w_array1[7:0][5:0]; // Declare an array of single bit wires
count[5] = 0; // Reset 5th element of array of count variableschk_point[100] = 0; // Reset 100th time check point valueport_id[3] = 0; // Reset 3rd element (a 5-bit value) of port_idarray. matrix[1][0] = 33559; // Set value of element indexed by [1][0] to 33559array_4d[0][0][0][0][15:0] = 0; //Clear bits 15:0 of the register accessed by
//indices [0][0][0][0]port_id = 0; // Illegal syntax - Attempt to write the entire arraymatrix [1] = 0; // Illegal syntax - Attempt to write [1][0]..[1][255]
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Data types
StringsStrings can be stored in reg Each character in the string takes up 8 bits (1 byte).
If the width of the register is greater than the size of the string, Verilog fillsbits to the left of the string with zeros
If the register width is smaller than the string width, Verilog truncates theleftmost bits of the string
reg [8*18:1] string_value; // Declare a variable that is 18 bytes wide initial
string_value = "Hello Verilog World"; // String can be stored // in variable
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System tasksVerilog provides standard system tasks for certain routine operations in theform $.
Operations such as displaying on the screen, monitoring values of nets,stopping, and finishing are done by system tasks
System tasks Usage Description
$display $display(p1, p2, p3,....., pn); Display values of variables orstrings or expressions
$monitor $monitor(p1,p2,p3,....,pn); Monitor signals when their valueschange
$stop $stop Stop a simulation
$finish $finish Terminates the simulation
Refer to IEEE Standard Verilog Hardware Description Language specification for more
l
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Compiler Directives All compiler directives are defined by using the ` construct.
Directives Example Description
`define 'define S $stop;'define WORD_SIZE 32'define WORD_REG reg [31:0]
Define text macros in Verilog
`include 'include header.v......
Include entire contents of a Verilogsource file in another Verilog fileduring compilation
`ifdef
`timescale
Refer to IEEE Standard Verilog Hardware Description Language specification for more
C E i i F l
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Agenda
Overview of Digital Design with Verilog HDLBasic conceptsHierarchical modeling conceptsModules Gate-Level ModelingDataflow ModelingBehavioral ModelingTasks and Functions
C E i i F l
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Design Methodologies
Top-down design methodology
Top-level blockidentify
enoughto build
Cannot further be divided
C t E i i F lt
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Design Methodologies
Bottom-up design methodology
Top-level block, thefinal block in design
Building blocks that areavailable is identified
build
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Design Methodologies
A combination of top-down and bottom-upflows is typically used Design architects define the specifications of thetop-level block
Logic designers break up the functionality intoblocks and sub-blocks. At the same time, circuit designers are designingoptimized circuits for leaf-level cells. They buildhigher-level cells by using these leaf cells. The flow meets at an intermediate point
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Example: 4-bit Ripple Carry Counter
Ripple Carry Counter T-flipflop
Design Hierarchy
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Modules
A module is the basic building block in Verilog Can be an element or a collection of lower-leveldesign blocks Provide functionality for higher-level block
through its port interface Hide internal implementation Is used at many places in the design Allows designers modify module internals withouteffecting the rest of design
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Example: 4-bit Ripple Carry Counter
Ripple Carry Counter T-flipflop
Design Hierarchy
Module
Module
Module
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Modules
Module descriptionmodule module name ( port name , port name ,);
module_port declaration
data type declaration
logic description partendmodule
A module definition
A part of a chip, orwhole the chip
module
The file name for RTL source mustbe module name.v
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Modules
module module name ( port name , port name ,);module_port declaration
Data type declaration Declare characteristics of variables
wire variable name , variable name , ;
wire variable name , variable name , ;
module
48
11
16
44
wire [3:0] a;wire [7:0] b;wire c, d;wire [3:0] f;wire [7:0] q1, q2, q3, q4;wire sel3, ; .
ab
cd
g
fe
for net data type
SEL
q2
q1
sel3
q3
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Modules
module module name ( port name , port name ,);module_port declaration
Data type declaration
Define signals which are output of FF, registers,and other memory elements as register typevariable.
reg variable name , variable name , ;
reg variable name , variable name , ;
wire [3:0] e;wire [15:0] g;
wire q2;.
for register data type
module
4811
1644a
b
cd g
feq2
Output does not have to be declared as register data type
Input (inout) must not be declared as register data type
Note:
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ModulesNote on register and net data type
module1 module2
reg
reg
reg
reg
wire
wire
wire
regwire
regwire wire
regmodule2_1
wire regregwire wire
The output of memory elementmust be defined as reg
They must be defined as wire atthese points.
: memory element
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ModulesQuestion: correct the type of the variables shown below
module2
reg wire
regmodule2_1
wire reg reg reg
wire
module1
reg
reg
wire
reg
wire
wire
reg
wire
reg
wirewire
wire
wire
reg
wire
wire
wire
wire
regwire
Suppose this part is programmedby using always statement.
Assume gates are not defined byusing always nor function statements
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Modules A sample answer
module2
reg wire
regmodule2_1
wire reg reg reg
wire
module1
reg
reg
wire
reg
wire
wire
reg
wire
reg
wirewire
wire
wire
reg
wire
wire
wire
wire
regwire
Suppose this part is programmedby using always statement.
Note: reg data type cannot be declared as an input !!!
wire wire
reg
wire wire
wire
wirewire
reg
reg
regExplain later
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Modules
module module name ( port name , port name ,);
module_port declaration
Data type declaration
Logic description part
endmodule
The main part of logic
is written here.
Logic is coded in this part using variousoperator including connections to lowerlevel blocks.
module4811
1644a
bcd
gfe
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ModulesInternals of each module can be defined at f o u r levels of abstraction,depending on the needs of the design.
The levels Description
Behavioral oralgorithmic
level
- Focus on the desired design algorithm without concern for thehardware implementation details.- Very similar to C programming
Dataflow level- A module is designed by specifying the data flow- Aware of how data flows between hardware registers and how the data is processed in the design
Gate level- The module is implemented in terms of logic gates andinterconnections between these gates.- Similar to describing a design in terms of a gate-level logic diagram
Switch level- A module can be implemented in terms of switches , storagenodes , and the interconnections between them.- Requires knowledge of switch-level implementation details
High
Low
A b s
t r a c
t i o n
F l exi b i l i t y
Verilog allows the designer to mix all f o u r levels of abstractions.
Register transfer level (RTL): is acceptableto logic synthesis tools
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AgendaOverview of Digital Design with Verilog HDLBasic conceptsHierarchical modeling conceptsModulesGate-Level ModelingDataflow ModelingBehavioral ModelingTasks and Functions
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Gate Types And/Or Gates
One scalar output
Multiple scalar inputs
The first terminal in the list ofgate terminals is an output andthe other terminals are inputs
wire OUT, IN1, IN2; // basic gate instantiations.and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);or or1(OUT, IN1, IN2);nor nor1(OUT, IN1, IN2);xor x1(OUT, IN1, IN2);xnor nx1(OUT, IN1, IN2);
// More than two inputs; 3 input nand gatenand na1_3inp(OUT, IN1, IN2, IN3);// gate instantiation without instance nameand (OUT, IN1, IN2); // legal gate instantiation
Verilog automatically instantiates theappropriate gate.
Terminal list
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Gate TypesBuf/Not Gates
One scalar input
One or more scalar outputs
The last terminal in the port listis connected to the input
// basic gate instantiations.buf b1(OUT1, IN);not n1(OUT1, IN);// More than two outputs
buf b1_2out(OUT1, OUT2, IN);// gate instantiation without instance namenot (OUT1, IN); // legal gate instantiation
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Gate TypesBufif/notif
Gates with an additional control signal on buf and not gates
Propagate only if control signal is asserted.
Propagate z if their control signal is deasserted
bufif1 b1 (out, in, ctrl); bufif0 b0 (out, in, ctrl); notif1 n1 (out, in, ctrl); notif0 n0 (out, in, ctrl);
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Gate Types Array of Instances
wire [7:0] OUT, IN1, IN2;
// basic gate instantiations. nand n_gate[7:0](OUT, IN1, IN2);
// This is equivalent to the following 8 instantiationsnand n_gate0(OUT[0], IN1[0], IN2[0]);nand n_gate1(OUT[1], IN1[1], IN2[1]);nand n_gate2(OUT[2], IN1[2], IN2[2]);nand n_gate3(OUT[3], IN1[3], IN2[3]);nand n_gate4(OUT[4], IN1[4], IN2[4]);nand n_gate5(OUT[5], IN1[5], IN2[5]);nand n_gate6(OUT[6], IN1[6], IN2[6]);nand n_gate7(OUT[7], IN1[7], IN2[7]);
The instances differ from each other only by the
index of the vector to which they are connected
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Gate TypesExample: Gate-level multiplexer
4-to-1 Multiplexer
// Module 4-to-1 multiplexer.
// Port list is taken exactly from the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagramoutput out;
input i0, i1, i2, i3;
input s1, s0;
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Gate TypesExample: Gate-level multiplexer
// Internal wire declarationswire s1n, s0n;wire y0, y1, y2, y3;// Gate instantiations// Create s1n and s0n signals.not (s1n, s1);not (s0n, s0);// 3-input and gates instantiatedand (y0, i0, s1n, s0n);and (y1, i1, s1n, s0);and (y2, i2, s1, s0n);and (y3, i3, s1, s0);// 4-input or gate instantiatedor (out, y0, y1, y2, y3);endmodule
Logic Diagram for 4-to-1 Multiplexer
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Gate TypesExample: 4-bit Ripple Carry Full Adder
1-bit ripple carry full adder
// Define a 1-bit full addermodule fulladd(sum, c_out, a, b, c_in);// I/O port declarations
output sum, c_out;input a, b, c_in;// Internal netswire s1, c1, c2;// Instantiate logic gate primitives
xor (s1, a, b);and (c1, a, b);xor (sum, s1, c_in);and (c2, s1, c_in);xor (c_out, c2, c1);
endmodule
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Gate TypesExample: 4-bit Ripple Carry Full Adder
4-bit ripple carry full adder
// Define a 4-bit full addermodule fulladd4(sum, c_out, a, b, c_in);// I/O port declarationsoutput [3:0] sum;output c_out;input[3:0] a, b;input c_in;// Internal netswire c1, c2, c3;
// Instantiate four 1-bit full adders.fulladd fa0(sum[0], c1, a[0], b[0], c_in);fulladd fa1(sum[1], c2, a[1], b[1], c1);fulladd fa2(sum[2], c3, a[2], b[2], c2);fulladd fa3(sum[3], c_out, a[3], b[3], c3);endmodule
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Gate DelaysRise, Fall, and Turn-off Delays
If only one delay is specified, this value is used for all transitions.
If two delays are specified, they refer to the rise and fall delay values. The turn-off delay is the minimum of the two.
If all three delays are specified, they refer to rise, fall, and turn-off delay values.
If no delays are specified, the default value is zero.
and #(5) a1(out, i1, i2); //Delay of 5 for all transitions
and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off = 5
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Gate DelaysMin/Typ/Max Values
For each type of delay three values, min , typ , and max , can be specified.
Min/typ/max values are used to model devices whose delays vary within a[min max] range because of the IC fabrication process variations.
min The minimum delay value that the designer expects the gate to have
typ The typical delay value that the designer expects the gate to have
max The maximum delay value that the designer expects the gate to have
Min, typ , or max values can be chosen at Verilog run time.
Method of choosing a min/typ/max value may vary for different simulatorsor operating systems
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Gate DelaysMin/Typ/Max Values
// One delay// if +mindelays, delay= 4// if +typdelays, delay= 5// if +maxdelays, delay= 6and #(4:5:6) a1(out, i1, i2); // Two delays// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)// if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)and #(3:4:5, 5:6:7) a2(out, i1, i2);// Three delays// if +mindelays, rise= 2 fall= 3 turn-off = 4// if +typdelays, rise= 3 fall= 4 turn-off = 5// if +maxdelays, rise= 4 fall= 5 turn-off = 6and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);
With Verilog XL TM
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AgendaOverview of Digital Design with Verilog HDLBasic conceptsHierarchical modeling conceptsModulesGate-Level ModelingDataflow ModelingBehavioral ModelingTasks and Functions
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Operators and Control StatementsIn verilog RTL programming, we can write expression by using verilog
operators and identifiers as shown below.Verilog expression example:
( a & b ) | ( c ^ ( ~d ))
operator
identifierUse ( ) to avoid possible misunderstanding of the precedence of the operations
& (and), | (or), ~ (not), ^(eor), ~^(enor)
Operation is applied bit by bit for vector data.
1 0 0 1 0 1 0 1 & 0 0 1 1 0 1 1 0
1 0 0 1 0 1 0 10 0 0 1 0 1 0 0
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Operators and Control Statements + (addition), - (subtraction), * (multiplication),
/ (division), % (quotient)*1 *1
*1: cannot be used for logic synthesis. For simulation only
Use arithmetic operator to get better logic. Synthesis tool can create bettercircuit than human.
> (right shift)*2
*2: logic shift
Example:assign A = B
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Operators and Control Statements (greater), >= (greater or equal)
== (equal), != (not equal)
=== (identical), !== (not identical)*1
a === b will result in true if a = 01xx00 and b = 01xx00,where a == b will result in x.
*1: cannot be used for logic synthesis. For simulation only
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Operators and Control Statements
(Condition)?s1:s2 (conditional operator){, , ,} (concatenate)
-> (trigger an event)*1
This is preferable than if.
*1: cannot be used for logic synthesis. For simulation only
Example:assign sig_y = (ctl == 1b1) ? sig_w : sig_q;
1
0
sig_w
sig_qsig_y
ctl
If (ctl == 1b1) begin sig_y = sig_w;
endelse begin
sig_y = sig_q;end
assign sig_y = {sig_w, sig_q};sig_w
sig_qsig_y
MPX
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Operators and Control Statements if statement, case statement
for statement, while statement
Control statements can be used only in structural procedure , initial statement, always statement, task and function .
Use case instead of if as much as possible.
Check the priority order among operators. (Refer to manual)
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Operators and Control StatementsIf-else and conditional operator
value of ctlexpression
if ( ctl == 1b1 ) sig_y = 2b10; else sig_y = 2b01;
sig_y = ( ctl == 1b1 ) ? 2b10 : 2b01;
1`b1 1`b0 1`bx
2`b10 2`b01 2`b01
2`b10 2`b01 2`bxx
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Operators and Control StatementsThe following operators are not recommended to use
&, ~&, |, ~|, ^, ~^
Do not use because only Verilog support this
assign a = &b;
means a becomes 1, if all the bits of b are 1.
This operator my be used as follow,
wire cache_hit = |{tag_cmp[31:0]};
&& (logical and), || (logical or), ! (logical not)
Do not use to avoid possible misunderstanding
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Continuous AssignmentWe can create various logic by connecting gates with wire. Theseconnection are done by using assign statement as below
assign aa_signal = bb_signal;
bb_signal aa_signal
assign aa_signal = (bb_signal ^ cc_signal) & dd_signal;
bb_signal
cc_signal
dd_signal
aa_signal
assign aa_signal = (cc_ctl)?bb_signal:dd_signal;
bb_signal
cc_ctl
dd_signal
aa_signal
Using conditionaloperator insteadof if or casestatement isrecommended
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Continuous AssignmentBy using this assignment, we can write an RTL code as below
bb_sig
cc_sig
dd_sig
aa_sig outputinput
eor_and_example
module eor_and example(bb_sig, cc_sig, dd_sig, aa_sig);input bb_sign, cc_sign, dd_sign;output aa_sign;wire bb_sign, cc_sign, dd_sign;wire aa_sign;wire sig_eor;
assign aa_sign = sig_eor & dd_sig;assign sig_eor = bb_sig ^ cc_sig;
endmodule
sig_eor
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Continuous AssignmentBy using this assignment, we can write an RTL code as below
bb_sig
cc_sig
dd_sig
aa_sig outputinput
eor_and_example
module eor_and example(bb_sig, cc_sig, dd_sig, aa_sig);input bb_sign, cc_sign, dd_sign;output aa_sign;wire bb_sign, cc_sign, dd_sign;wire aa_sign;wire sig_eor;
assign aa_sign = sig_eor & dd_sig;assign sig_eor = bb_sig ^ cc_sig;
endmodule
Note: Because the assignment isdone always, exchanging thewritten order of the lines ifcontinuous assignment has noinfluence on the logic.
sig_eor
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Continuous AssignmentQuestion: What shall be the result of the following assignment?
(1) wire [3:0] y;assign y[3:0] = -3;
(2) wire [3:0] y;assign y[3:0] = 2b10;
(3) wire [3:0] y;
assign y[3:0] = 6b111000; (4) wire [3:0] y;
assign y[3:0] = 1b0;
(5) wire [3:0] y;assign y[3:0] = 1bx;
(6) wire [3:0] y;assign y[3:0] = 4bx;
(7) wire [3:0] y;assign y[3:0] = 4b1;
In your program,always make bit widthof left-hand side andright-hand side equal
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Continuous Assignment A sample answer
(1) wire [3:0] y;assign y[3:0] = -3;
(2) wire [3:0] y;assign y[3:0] = 2b10;
(3) wire [3:0] y;
assign y[3:0] = 6b111000; (4) wire [3:0] y;
assign y[3:0] = 1b0;
(5) wire [3:0] y;assign y[3:0] = 1bx;
(6) wire [3:0] y;assign y[3:0] = 4bx;
(7) wire [3:0] y;assign y[3:0] = 4b1;
There may be tool dependency on these result.
y = 4b1101
y = 4b0010
y = 4b1000
y = 4b0000
y = 4b000x
y = 4bxxxx
y = 4b0001
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Continuous AssignmentQuestion: Check if the following statements are correct or not?(1) wire [7:0] a, b;
assign b[7:0] = a[3:0] 4b0010;
b[7:0] = 8b1111_1110 if a is 8h00 In your program,always make bit widthof left-hand side andright-hand side equal
(2) wire [7:0] a;assign b[7:0] = 4b1110;
a[7:0] 8hFE (3) wire [7:0] a, b;
assign a[3:0] = b[7:0] 4b0100;
a[3:0] = 4hC if b[7:0] is 8h00
(4) wire [7:0] a, b;assign b[7:0] = a[3:0] 6b11_0001;
b[7:0] = 8b0000_1111 if a is 8h00
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Continuous AssignmentQuestion: Write a Verilog RTL code for the gate diagram shown below.(Compile the part.)
a
b
cw2
w1
w3
w4
y
wire a, b, c, y;
assign y =
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Continuous Assignmenta
b
cw2
w1
w3
w4
y
A sample answer
wire a, b, c, y;wire w1, w2, w3, w4;assign w1 = (~a) & b;assign w2 = b | c;assign w3 = ~(a & c);assign w4 = w1 & w2;assign y = w3 ^ w4;
wire a, b, c, y;wire w3, w4;assign w3 = ~(a & c);assign w4 = ((~a) & b) & (b | c);
assign y = w3 ^ w4;
wire a, b, c, y;assign y = ~(a & c) ^ ((~a) & b) & (b | c);Implicit wire declaration
and implicit continuousassignment
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DelaysDelay values control the time between the change in a right-hand-side operandand when the new value is assigned to the left-hand side.
Regular Assignment Delay
assign #10 out = in1 & in2; Any change in values of in1 or in2 will result in adelay of 10 time units before recomputation ofthe expression in1 & in2 , and the result will be
assigned to out
A pulse of width less thanthe specified assignmentdelay is not propagated tothe output ( inertial delay )
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DelaysImplicit Continuous Assignment Delay
//implicit continuous assignment delaywire #10 out = in1 & in2;
wire out;assign #10 out = in1 & in2;
Net Declaration Delay
//Net Delayswire # 10 out;assign out = in1 & in2;
wire out;assign #10 out = in1 & in2;
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AgendaOverview of Digital Design with Verilog HDLBasic conceptsHierarchical modeling conceptsModulesGate-Level ModelingDataflow ModelingBehavioral Modeling
Tasks and Functions
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Procedural assignments
Assignment
Continuous
assignment
Proceduralassignment
Wire connection:
Assignment is always done.
*1
assign a_sig = b_sig;
Assignment isdone depending
on procedure.
Blocking procedural assignmenta_sig = b_sig;
Execution of the next line is blockeduntil this assignment is done.
Nonblocking procedural assignmenta_sig
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Procedural assignments
left-hand side must be right-hand sidecan be note
continuousassignment
net data type variable
any data type
not applicable instructured procedure:always, initial block
proceduralassignment
register data typevariable.
any data type
applicable only instructuredprocedures: initial,always, function, andtask.
wire a;assign a = ----;
reg a;assign a = ----;
reg a;a = ----;
wire a;a = ----;
Restrictions of continuous / procedural assignment
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Procedural assignmentsblocking vs. nonblocking procedural assignment
In structured procedure, if there are more than one statement to execute,they must be grouped in one block. begin end and fork join are available.
However, use begin end for logics which must be synthesized.
The block defined by begin and end pair is called sequential block
In a sequential block, statement are executed in serial, inorder they are written.
begin
end
Statement are executedin the order they arewritten.
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(1) Nonblocking procedural assignment (continued)
In case of nonblocking procedural assignment, thereis less order dependency. Because it does not blockof execution of the next sentences.
reg wk1, wk2, wk3, wk4, y;
beginy
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Question: Think if the logic on the right below works as intended. If not, correct thefollowing program to save data to buf using a pointer ptr. ptr must be updated by oneafter data_in is stored to buf pointer by ptr.
buffr[0]buffr[1]buffr[2]buffr[3]buffr[4]
ptr (2)
in_data
buffr[0]buffr[1]in_databuffr[3]buffr[4]
ptr(3)
before execution ofthe sequential block
after execution of thesequential block
begin
ptr
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A sample answer
Yes, it works asshown below.
However, the sampleprogram in the right is
just for explanation. Donot program in thisway. It is a confusing
expression.
begin
ptr
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(2) Blocking procedural assignment
If no wk is given value outside this block, everytime this block is executed because of change ofa, their value change as below.
reg wk1, wk2, wk3, wk4, y;
begin
wk1 = a;
wk2 = wk1;
wk3 = wk2;
wk4 = wk3;y = wk4;
end
(1)
(2)
(3)
a
wk1
wk2
wk3wk4
y
a1 a2 a3 a4 a5 a6a1 a2 a3 a4 a5 a6 This means
from a to y,the connection
is direct
1st time2nd time
3rd timeBecause execution of (3) isblocked by (2), (3)s right -hand side is evaluated afterthe execution of (2). (2) isexecuted after (1).Therefore wk2 in (3) shallbe a1 and wk3 becomes a1.
awk1 wk2 wk3 wk4 y
a1 a2 a3 a4 a5 a6
a1 a2 a3 a4 a5 a6a1 a2 a3 a4 a5 a6
a1 a2 a3 a4 a5 a6
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(2) l ki d l i ( i d)
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(2) Blocking procedural assignment (continued)
Blocking procedural assignment has order dependency.Check an example on the left if the sequential block isexecuted because of the change of a.
(1)(2)(3) This result is
same to thatof nonblocking
assignment.
1st time2nd time
3rd time
When (1) is executed wk4 isnot given a value. When (3)is executed wk2 is not givena value yet, therefore wk3becomes x
reg wk1, wk2, wk3, wk4, y;
beginy = wk4;wk4 = wk3;wk3 = wk2;wk2 = wk1;wk1 = a;
end
(4)
a
wk1
wk2
wk3wk4
y
a1 a2 a3 a4 a5 a6a1 a2 a3 a4 a5 a6
a1 a2 a3 a4 a5x
a1 a2 a3 a4a1 a2 a3
a1 a2
x xx x x
x x x x
awk1 wk2 wk3 wk4 y
an element to keep the previous value
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(2) Bl ki d l i ( i d)
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(2) Blocking procedural assignment (continued)
Because assignment is done in serial in case of
blocking procedural assignment, exchanging the orderof statements will have large influence over the result.
begin
a = b & c;b = d | e;
end
dec
ba
dec
ba
latch
If the sequential blockon the left is executed
because of the changeof c, d or e, then theresults are differentdepending on theorder of those twostatements
You must be very careful to write statements whichhave mutual dependency like these two sentences.
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(3) Mix of blocking and nonblocking procedural assignment
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(3) Mix of blocking and nonblocking procedural assignment
This is just for explanation
Do not mix!!!Synthesis tool may report error.
reg wk1, wk2, wk3, wk4, y;
beginwk1 = a;
wk2
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Question: Suppose the following sequential block is executed every time a is givennew value. Complete the chart to show how wk are changed in simulation when achanges its value as show in the chart.
reg wk1, wk2, wk3, wk4, y;
begin
wk1
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A sample answer.
reg wk1, wk2, wk3, wk4, y;begin
wk1
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Summary blocking vs. nonblocking
1. Use blocking procedural assignment to create combinational logic.
nonblocking procedural assignment is not allowed in function.Use nonblocking procedural assignment in always statement forcombinational logic.
2. Use nonblocking procedural assignment to create sequential logic.
3. Otherwise, use nonblocking procedural assignment unless orderdependency needed.
Basically avoid order dependent code.However if order dependency is needed, use blocking procedural
assignment.
Be careful not to causepunch through
b = a;c = b;d = c;
This will result ind = a
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Structured procedure(1) Control statements
In structured procedure, we can use control statements, such as if and
case statements.
if statement case statement
syntax
if (Boolean expression )sentence1;
elsesentence2;
case ( Variable1 )value1: sentence1;
value2: sentence2;default: sentence3;endcase
description
sentence1 is executed if theexpression is true, if not,sentence2 is executed.
If variable1 is equal to value1 thensentence1 is executed. casestatement uses === for
comparison.
NoteTo describe combinational logicby using if statements, else partshall not be dropped.
Always wirte default part, to detectpossible bugs and to avoid createlatches.Use case statement as much as
possible. Why ?
case expression
case item
if and case statement Difference from C language: break is not needed.
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EDA tool handles case statement same to if statement, therefore anexpression like below can work, however, avoid using the following expression.It can be used only when it is assured that case items never take the samevalue at the same time.
case (2b01)
indx_sig1: qreg_out
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case statement is processed as below;
first, case is evaluated by using === (identical) if not match, next case is evaluated.if no case item match, then default part is executed.
The following code is just to show how case works
begincase ( d )
1bx : q
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casex statement treats x, z and ? as the dont care values.
This means that if case item is 3b1x0 as shown below then second bit of caseexpression is ignored in the comparison with the case item 3b1x0 .
if sel contains no x;
casex ( sel )3b1x0: ---; sel[2] === 1 & sel[0] === 03b011: ---; sel[2] === 0 & sel[1] === 1 & sel[0] === 1
if sel contains x such as sel is 3b1x1;
casex ( sel )3b110: ---; sel[2] === 1 & sel[0] === 03b011: ---; sel[2] === 0 & sel[0] === 1
If case expression contains x, case items are compared as belowdont care
This is very dangerous, because if all bits of case expression are x(3bxxx) then first case item matches always.
Do not use casex in any occasion!!
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casez statement treats z and ? as the dont -care values.
if sel contains no z;
casez ( sel )3b1?0: ---; sel[2] === 1 & sel[0] === 03b011: ---; sel[2] === 0 & sel[1] === 1 & sel[0] === 1
if sel contains z such as sel is 3bz01;
casez ( sel )3b1?0: ---; sel[0] === 03b011: ---; sel[1] === 1 & sel[0] === 1
If case expression contains x, case items are compared as belowdont care
This is also dangerous, however sel has less chance to have zcompared to having x.Use casez is not recommended. However if it is necessary to usewild card, use casez instead of casex.
In verilog ? is a shorthand for z.
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case ( sel )First choice
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case ( sel )
3b000, 3b001, 3b100, 3b101 : y
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p
We can use loop statement in verilog RTL programming. There are fourloop instructions available. They are forever, repeat, while, and for.
Syntax for loop instructions:
forever statement;Continuously repeat the statement forever.
repeat (expression) statement;Execute the statement a fixed number of times. The number ofexecutions is set by the expression. If the expression evaluates tounknown, high-z, or a zero value, then no statement will be executed.
while (expression) statement;Execute the statement until the expression is true. If a while instruction
starts with a false value, then no statement will be executed.
*1
*1
*1
*1: In many cases these are not synthesizable or there may be heavy tooldependency. Therefore avoid using these statements in a synthesizablecode.
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for ( assignment; expression; assignment) statement;
Execute the statement ultil the expression is true. At the initial step, thefirst assignment will be executed. At the second step, the expression willbe evaluated. If the expression is false ( an unknown, high-z, or zero),then the for statement will be terminated. Otherwise, the statement andsecond assignment will be executed. After that, the second step isrepeated.
If loop instructions are used in a module whichhas to be synthesized, care must be taken. Youhave to be aware what structure will begenerated with loop instructions.
You have to be aware that they are differentfrom those in C programming language.
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for loop is used to reduce code lines where similar patterns are repeated
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for loop is used to reduce code lines where similar patterns are repeated.
8
addr_in[7:0]
256
decoded_addr[255:0]
addr_dcd
Take an example of logic whichcreate 256-bit one hot signalfrom 8-bit input data addr_in .For example, if addr_in = 5 ,decoded_addr = 256b0000 -----00100000 . If addr_in = 255 ,decoded_addr = 256b1000 ----00000 .
module addr_dcd (addr_in, decoded_addr);parameter ADDRESS = 8;parameter RAMSIZE = 256;input [ADDRESS 1 : 0] addr_in;
output [RAMSIZE - 1 : 0] decoded_addr;integer i;
reg [RAMSIZE 1 : 0] decoded_addr;always @ (addr_in) begin
for( i=0; i < RAMSIZE ; i=i+1)decoded_addr[ i ] = (addr_in == i);
endendmodule
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Question: Will the following code work same to the code on the previous page?
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Question: Will the following code work same to the code on the previous page?
8
addr_in[7:0]
256
decoded_addr[255:0]
addr_dcdmodule addr_dcd (addr_in, decoded_addr);parameter ADDRESS = 8;parameter RAMSIZE = 256;input [ADDRESS 1 : 0] addr_in;output [RAMSIZE - 1 : 0] decoded_addr;integer i;
reg [RAMSIZE 1 : 0] decoded_addr;always @ (addr_in) begin
for( i=0; i < RAMSIZE ; i=i+1)decoded_addr[ i ]
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A sample answer
Yes, it will.
always @ (addr_in) begin
// for( i=0; i < RAMSIZE ; i=i+1)decoded_addr[0i ]
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Note: In case of the program on the previous page, without using for loop, it canbe written as below. Sometimes DA tools create smaller logic for the code belowcompared to the code on the previous page.
module addr_dcd (addr_in, decoded_addr);parameter ADDRESS = 8;parameter RAMSIZE = 256;
input [ADDRESS 1 : 0] addr_in;output [RAMSIZE - 1 : 0] decoded_addr;
integer i;reg [RAMSIZE 1 : 0] decoded_addr;
always @ (addr_in) begin
i = addr_in;
decoded_addr = 0;decoded_addr[ i ] = 1b1;
endendmodule
Computer Engineering Faculty
Question: Check if the following logic can find the maximum value in lst
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Question: Check if the following logic can find the maximum value in lst.
reg [3:0] mx;reg [3:0] lst [0:3];
always @ (lst[0] or lst[1] or lst[2] or lst[3]) begin
mx
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reg [3:0] mx;reg [3:0] lst [0:3];always @ (lst[0] or lst[1] or lst[2] or lst[3]) begin
mx
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Computer Engineering Faculty
Question: Rewrite the code below so that it can find the maximum value in lst
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Question: Rewrite the code below so that it can find the maximum value in lst.
reg [3:0] mx;reg [3:0] lst [0:3];
always @ (lst[0] or lst[1] or lst[2] or lst[3]) beginmx = mx ) mx = mx ) mx = mx ) mx = mx ) mx
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reg [3:0] mx;reg [3:0] lst [0:3];
always @ (lst[0] or lst[1] or lst[2] or lst[3]) beginmx = mx ) mx = lst[0];
if ( lst[0] >= mx ) mx = lst[1];
if ( lst[0] >= mx ) mx = lst[2];
if ( lst[0] >= mx ) mx = lst[3];
end
A sample answer
Use blocking procedural assignment instead of nonblockingprocedural assignment.
lst = e,2,0,c, mx=elst = 5,2,0,c, mx=c
lst = 5,2,1,c, mx=clst = 5,2,1,6, mx=6lst = 5,d,1,6, mx=dlst = 5,1,9,6, mx=9lst = d,1,1,6, mx=d
lst = d,9,1,9, mx=dlst = 3,1,c,2, mx=clst = 8,1,4,5, mx=8
lst[0], lst[1], lst[2], lst[3]
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Computer Engineering Faculty
(2) function
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Function is one of structural procedures. It provides a means of splittingcode into small parts that are frequently used in a model.
We can use control statements , such as if, case, for, etc
We must use procedural assignment.
function type_or_range identifier ;input_declaration;
register _declaration;
statement;
endfunction
declaration of functionThis must be written inside amodule declaration
must have at least one input
Internal variables must bedeclared as register datatype.
Functions cannot have outputor inout arguments.
...
...
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Computer Engineering Faculty
execute timing of a function
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execute timing of a function
In RTL simulation, function is executed whenever there is any change of
the value of the parameters.
assign sig_y = func_ff ( a, b, c );
assign sig_w = func_ff ( e, f, g );
function func_ff;input p1, p2, p3;begin
endendfunction
...
...
... ... The sequential block isexecuted wheneverinput variables changestheir values.
When input parameter a, b, or cchange their value, functionfunc_ff will be executed.
When input parameter e, f, or gchange their value, functionfunc_ff will be executed.
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Internal variables used in function must be declared by register data type.
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Internal variables used in function must be declared by register data type.
Example:
function [7:0] avrg_four;input [7:0] a, b, c, d;reg[ [8:0] wk1, wk2;reg [9:0] wk3;
beginwk1[8:0] = {1b0, a[7:0]} + {1b0, b[7:0]}; wk2[8:0] = {1b0, c[7:0]} + {1b0, d[7:0]}; wk3[9:0] = {1b0, wk1[8:0]} + {1b0, wk2[8:0]}; avrg_four[7:0] = wk3[9:2];
endendfunction
These internal variables mustbe declared as register datatype, not wire data type.
Computer Engineering Faculty
Function can not handle a memory element. However, if there is a path in which
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Function can not handle a memory element. However, if there is a path in whicha variable is not given its value, RTL simulator will assign previous value for thevariable in such path. This causes latching.
You have to give values to all variables in every paths.
function [1:0] abcde;input a, b;if ( a == 1b1)
beginabcde[1] = 1b0; abcde[0] = b;
endelse If ( b == 1b0)
beginabcde[1] = b;abcde[0] = ~a;
endelsebegin
abcde[1] = ~b;end
endfunction
In the sample code on the left, when a=0 and b=1,abcde[0] is not given any value. A synthesis tool willcreate logic by treating abcde[0] as dont care in thispath. Therefor, the result of gate level simulation and
RTL simulation will be different. For the same reason above, in the followingexample, default path is indispensable.
function [3:0] dec2to4;input [1:0] d_code_in;begin
case (d_code_in)2b00: dec2to4 = 4h1; 2b01: dec2to4 = 4h2; default: dec2to4 = 4bxxxx;
endcaseendendfunction
Computer Engineering Faculty
Question: Check the following code has any problem or not for creating
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Question: Check the following code has any problem or not for creatingcombinational logic by function statement.
function [1:0] abcde;input a, b;beginif ( 1 == 1b1)
beginabcde[1] = 1b0; abcde[0] = b;
endelse if ( b == 1b0 )
beginabcde[1] = b;
abcde[0] = ~a;end
endendfunction
Computer Engineering Faculty
A sample answer
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p
function [1:0] abcde;input a, b;beginif ( 1 == 1b1)
beginabcde[1] = 1b0; abcde[0] = b;
endelse if ( b == 1b0 )
beginabcde[1] = b;
abcde[0] = ~a;end
endendfunction
else part is missing
Computer Engineering Faculty
(2) always statement
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Always statement defines a procedure which is executed always. That is,it defines infinite loop.
always begin
end
always createsan infinite loop
always @ (..)begin
end
sensitive list
waiting for signal in the
sensitivity list change.
By adding @ ( ) to always statement, thisalways statement means wait for change ofsignals listed in the sensitivity list and when thechange takes place, sequential block ( frombegin to end ) is executed.
Computer Engineering Faculty
execute timing of always statement
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always @ (..)
begin
end
sensitive list
Always statement is executed at time 0, and with@, waits for the event designated by a sensitivitylist. Thus, the sequential block, begin-end part, isexecuted whenever the event happens.
description timing
always @ ( posedge clk )
always @ ( negedge rst_n )
always @ ( a or b )
when signal clk rises
when signal rst_n falls
when signal a or b change
level signal edge signal
Do not write edge signal(posedge / negedge) andlevel signal together.
always @ ( sig_a or posedge clk )
Computer Engineering Faculty
@ and sensitivity list help us to control the execution timing of a structured
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procedure.
Example:
reg wk1, wk2, wk3, wk4, y;begin
wk1
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reg wk1, wk2, wk3, wk4, y;always @ ( a ) begin
wk1
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reg wk1, wk2, wk3, wk4, y;always @ ( a or wk1 or wk2 or wk3 or wk4 )
beginwk1
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reg a, b, c, d, y;reg wk1, wk2;
always @ ( a or b or c or d or wk1 or wk2 )begin
wk1
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the right, Style 1 is recommended comparedto Style 2 because of the simulation efficiency.
b
cd
wk1
wk2
y
reg a, b, c, d, y;
reg wk1, wk2;
always @ ( a or b or c or d )begin
wk1 = a | b;wk2 = c & d;y = wk1 ^ wk2;
end
reg a, b, c, d, y;
reg wk1, wk2;
always @ ( a or b or c or d or wk1 or wk2 )begin
wk1
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y g
As is shown in the previous pages, always statement can be used to
define combinational logic
To create combinational logic by using always statement, we have to:
(1) Declare all the signals in a sensitivity list used in the right hand sideof the statements in always statement, and
(2) Give values to all the signals appearing on the left hand side of thestatements in any case,
and then such always statement can generate combinational logic.
*1
Why?
*1 If missing any signal in the list, simulation resultmay be different from the actual logic created.
Computer Engineering Faculty
always statement and combinational logic
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To avoid troubles caused by poor sensitivity list, we can use * in a
sensitivity list. By using *, the rule for always statements forcombinational logic becomes a little bit simple as follows.
To create combinational logic by using always statement, we have to:
(1) Use always statement
always @ * begin end
(2) Give values to all the signals appearing on the left hand side of thestatements in any case,
and then such always statement can generate combinational logic.
*1
* is supported in Verilog 2001, check tools default setting supportsVerilog 2001 or not before using * notation.
Computer Engineering Faculty
always statement and combinational logicab
wk1
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c
d wk2
y
always @ *begin
wk1 = a | b;wk2 = c & d;y = wk1 ^ wk2;
end
Best style
always @ ( a or b or c or d ) begin
wk1 = a | b;wk2 = c & d;y = wk1 ^ wk2;
end
Acceptable style
always @ ( a or b or c or d or wk1 or wk2) begin
wk1
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Computer Engineering Faculty
Question: Draw a gate diagram for the logic created by the following RTL code.
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d
g
q module some_logic ( g, d, q );input g, d;output q;wire g;wire d;reg q;always @ * beginif( g == 1b1) q = d; else q = ~d;end
endmodule
some_logic
Computer Engineering Faculty
A sample answer module some_logic ( g, d, q );i t d
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d
g
q
input g, d;output q;wire g;wire d;reg q;always @ * beginif( g == 1b1) q = d; else q = ~d;
endendmodule
some_logic
D
QG QD
G
Computer Engineering Faculty
Important!!
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Important!!
Failing to give values to all variables in every pathcauses many trouble again and again.
You must be careful in using always statement tocreate combinational logic.
The same problem occur with case statement
Be sure to give all the variablesvalues in every path
Computer Engineering Faculty
The following is a code intended to create combinational logic. Correct the codeh i ill i d d l i
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so that it will generate intended logic.
wire a, b, c;wire d;req q1, y;always @ ( a or b or c ) beginq1 = a ^ b;
if( d == c) beginy = b | q1;endelse begin
q = ~d;endend
Computer Engineering Faculty
A sample answer
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wire a, b, c;wire d;req q1, y;always @ ( a or b or c ) beginq1 = a ^ b;
if( d == c) beginy = b | q1;endelse begin
q = ~d;endend
*
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Computer Engineering Faculty
How to avoid generating latch always @ * beginif( a == b) begin
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req q1, q2;
always @ * beginif( a == b) begin
q1 = c;q2 = d;
endelse begin
q1 = d;endend
always @ * beginq2 = d;if( a == b) begin
q1 = c;endelse begin
q1 = d;endend
Move q2 out of ifblock so that q2 isdefined in any paths
if( a == b) beginq1 = c;q2 = d;
endelse begin
q1 = d;q2 = d;
end
end
Define q2 in else pathsame as true case
always @ * beginif( a == b) begin
q1 = c;q2 = d;
endelse begin
q1 = d;q2 = 1bx;
endend
Give x (unknown) valuetp q2 in else part
Computer Engineering Faculty
The best way to avoid latch in general cases is to give value to variables before
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The best way to avoid latch in general cases is to give value to variables beforeany conditional branch takes place.
always @ * beginsig_y = ------;case ( ----) begin
-----; beginsig_y = -----;
end-----; begin
sig_y = -----;
endendcaseend
By giving value to sig_y at first, wecan assign value to sig_y only inpaths where it has to be assigneddifferent values.
Computer Engineering Faculty
When using case statement same care must be taken to prevent creating latches
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When using case statement, same care must be taken to prevent creating latches.
always @ * begincase ( state )
yyy1: beginww = ---;end
yyy2: begin
ww = -----------;endyyy3: begin
ww = ------;end
endcaseend
If these case items listed doesnot cover all the possiblecases, synthesis tool will
create latches to take care ofthe cases that case expressiondoes not match with any one ofcase items.
Add default to prevent creating latches
Computer Engineering Faculty
Question: The following is a part of a program intended to create combinationallogic Correct the code so that it will create combinational logic
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logic. Correct the code so that it will create combinational logic.
always @ (posedge clk or negedge rst_n)
beginif(rst_n == 1b0) begin
state
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case (state)INTL: begin
if ( ! flick) next_state
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logic. Correct the code so that it will create combinational logic.
always @ (posedge clk or negedge rst_n) begin
if( rst_n == 1b0)a_lamp [7:0]
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always @ ( f_state or a_lamp or flick ) begincase ( f_state )
3b000: begin
if ( flick == 1b1 ) next_lamp[7:0]
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guaranteed that case expression never becomes 2 b11. If so, the following code isOK or not?
always @ ( a ) begincase ( a[1:0] )
2b00: begin b[1:0] = 2b10; end
2b01: begin b[1:0] = 2b00; end
2b10: begin b[1:0] = 201;
endendcase
end
Case items cover only three cases, 00,01, and 10, out of four possible cases.But it is guaranteed that 11 case will
never happen.
Computer Engineering Faculty
A sample answer
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No, this code is not OK because synthesis tool will create a latch to keep valueof b for such cases that case expression becomes 2b11. We have to use
default to prevent creating latch.Synthesis tool can not know that a[1:0] never becomes 2b11.
always @ ( a ) begincase ( a[1:0] )
2b00: begin
b[1:0] = 2b10; end2b01: begin
b[1:0] = 2b00; end
2b10: begin
b[1:0] = 201; end
endcaseend
default: beginb[1:0] = 2bxx;
end
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Computer Engineering Faculty
Question: Will the following code create a latch?
always @ ( a ) begin
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y @ ( ) gcase ( a[1:0] )
2b00: begin b[1:0] = 2b10; end
2b01: begin b[1:0] = 2b00; end
2b10: begin b[1:0] = 201; end
2b11: begin end
default: beginb[1:0] = 2bxx; end
endcaseend
11 case never happenstherefore null statementis added for 11 case
Computer Engineering Faculty
A sample answer
always @ ( a ) beginYes, this code will create a latchb l i i t b i
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y @ ( ) gcase ( a[1:0] )
2b00: begin b[1:0] = 2b10; end
2b01: begin b[1:0] = 2b00; end
2b10: begin b[1:0] = 201; end
2b11: begin end
default: beginb[1:0] = 2bxx; end
endcaseend
This code will create a latch
because no value is given to b in11 case
Computer Engineering Faculty
Note on combinational logic using always
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Defining many variables in one big always statement is not recommended. Becauseit makes logic complicated and debugging difficult.
Divide it into small always blocks which define small numbers of outputs.
always @ *begin--------------abc = ------;--------------------efg = ----;-------------------
jlk = ----;-------end
This large alwaysstyle is notrecommended.
always @ *begin--------------abc = ------;endalways @ *begin--------------efg = ------;endalways @ *begin--------------
jlk = ------;end
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Computer Engineering Faculty
How to use module, function and always
d l U d l d ib h l i
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c1
c1
c1
module
c1
c1
module
Use module to describe these logic
c2
c2
module
Use function to describe these logic
c4
module
*1
Use always or function todescribe this logic
c3
module
*1
Use always to describe this logic
*1: unique to this module and appear only once
Computer Engineering Faculty
Logic simulation and test bench
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(1) Structure of test bench
A test bench is a program which cangive arbitrary inputs to modules undertest and observe their outputs.
Moduleunder test
Provideinputs
ObserverOutputs
module test bench;reg [7:0] dat, declaration of signals
Connection of module under test
The description of the clock
initial begin . end Test input declaration..
endmodule
A description of test bench in Verilog-HDL
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Computer Engineering Faculty(2) Always statement for test bench
Always statement creates infinite loop Typical usage is tol k i l
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y pcreate lock signals
parameter HALF_CYCLE = 500;
always begin
clk = 1b0;
#HALF_CYCLE clk = 1b1
#HALF_CYCLE;
end
Sentences between begin andend is repeated forever
A sample code on the leftgenerates a clock signal having
500*2 time units cycle time.
Computer Engineering Faculty
# is used to define a delay time
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How to use of # delay
wire [15:0[] #delay d_bus;
# delay sig_in
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end
When the executionreached the bottom,control is passed to thefirst sentence
Control statementscan be written here tomake branch or loopof the procedure
first statement.Therefore, if there is no delay nor waitin the second sentence, the first andthe second sentences ( and so on )are executed at the same time.
#20;
Sig_a = 1b0;
Sig_b = 1b1;
sig_c = 4b0101;
#100 sig_d = 1b0;
All of the threesignals are giventhe values at thesame time.
Note that depending on assignment type (blocking /nonblocking) the behavior is different.
Computer Engineering Faculty
What will happen if the following always statement is executed?
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always begin
sig_a = 1b0; sig_b = 1b1;
end
Computer Engineering Faculty
A sample answer
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always begin
sig_a = 1b0;
sig_b = 1b1;
end
This may hang up a simulator by infinite loop.
Remember that always statement must have atleast one procedural timing control
Computer Engineering Faculty
(2) Initial statement for test bench
Initial statements are executed only one time. If there are several initialt t t th t d t th ti
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statements, they are executed at the same time.
begin begin
end
When the executionreached the bottom, nomore execution is to bedone.
Control statement can be written here tomake branch or loop of the procedure.
The first sentence is executes at time zero.The next statement executed right after thefirst statement.
Therefore, if there is no delay nor waitin the second sentence, the first and
the second ( and so on ) is executed atthe same time.
for (i = 0 ; i < 100; i = i + 1 )
begin
#20 ss_in = s_data[i];
end
Computer Engineering Faculty
Each sentences between begin and end are executed sequentially.
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$finish is a system task is to stop simulation.
initial begin
rst_n = 1b0;
s_rdy = 1b0;
sig_input = 1b0;
#100 rst_n = 1b1;
#40 s_in = 4h9;
#5 s_rdy = 1b1;
$finish;
end
rst_n
s_rdy
s_in100
40
5
9
Computer Engineering Faculty
initial begin t = 0 t = 20t = 10
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g
a
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initial begin //signal sig_aa
sig_aa
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initial begin
end
Generally allthestatementsare executedin sequence.
initial fork
# 20 sig_in = 1b1; # 5 s_out = 1b0; # 15 aa_in = 8hFF;
join
Parallel execution ofthe statementsbetween fork and join
5s_out = 1b0;
15aa_in = 8hFF;
sig_in = 1b1;
Do not use fork/join if you do not have to
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(3) Task statement for test bench
Tasks are almost same to functions, but they can return several outputs.
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They are very useful for creating structured test bench by providing
functionalities such as bus operation or CPU operation.sask task_identif ier ;
parameter_declaration;
input_declaration;output_declaration;
inout_declaration;
register_declaration;
event_declaration;statement;
endtask
Task arguments
Register data types
Memory referencesConcatenations of register ormemory referencesBit-selects and part-selects ofreg , integer and time registers.
Net declaration is illegal
A begin-end block is required forbracketing multiple statements.
Computer Engineering Faculty
In task
(1) Control statements ( if and case statements) can be used
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(2) Assign must be procedural assignment ( = or
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Computer Engineering Faculty
With output arguments, outputs are given to values when the task is completed.
Only the last assignment to an output or an inout argument is passed tothe corresponding task enabling arguments If no output argument given
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the corresponding task enabling arguments. If no output argument given,it refers to external signals (global variables) directly. And the variables
are given values when they are assigned values. In such case, allchanges of these variables are effective immediately.
. . bus_tsk ( sig_a );.
. task bus_task ;output out1;.
out1 = a;.
out1 = b; endtask
With output argument
. bus_tsk;. b = sig_a;. task bus_task ;.
sig_a = a;. endtask
Without output argument
Only the lastassignment ispassed to theoutput argument Effective immediately
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Tasks can enable other tasks and functions.
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A task may be enabled several times in a module. If one task is enabled
concurrently, then all registers and events declared in that task should bestatic, i.e., one variable for all instances.
Care must be taken in case that two or more instances areenabled concurrently.
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(4) Wait control
@ is used to wait for a event
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@event d_ready ;
always @ (posedge clk or complete_calc)begin
if(complete_calc == 1b1) #delay_1 -> d_ready;
end
initial begin. #delay ; .. @ d_ready req_d = 1b1; #...... end
When complete_calc becomeson, then after delay_1 time units,event d_ready is set. And thisevent d_ready activates @ statement, which sets req_d on.
This sentence waits for theevent d_ready.
When the event occurs, thissentence is executed andcontrol is passed to the nextsentence.
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Another example of using @
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. @ event signal_up = 1b1; # delay@ event signal_up = 1b0; . .
Wait until event occurs, and when itoccurs, assign 1 to signal_up.
Wait delay time units
Again, wait for event occurs, and
when it occurs, assign 0 to signal_up.
Question: If an event is issued before an wait for the event is executed,what happens to the wait?
Do not write a sophisticated or tricky program using wait andother control statements. Always simple is the best
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The term, race condition, originates with the idea of two signals racing each
Race condition
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Wait for event
The term, race condition, originates with the idea of two signals racing eachother to influence the output first.
Verilog RTL programming may cause race condition between two or morestatements as shown below.
reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;end
initial begina = 1; b = 2;
end
Change ofa or b
event
a and b changefrom x to 1 and 2respectively.
t=0 t
a 1
b 2
c 3
waitexecutedfirst
a 1
b 2c x
event
occurredfirst
c keeps the value x until a orb is given a new value
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Because there is no standard rule for execution sequence of statements, asimulation result may have tool dependency.Some tools execute from top to bottom while others from bottom to top
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Some tools execute from top to bottom, while others from bottom to top.
This means that there is order dependency in what sequence thosestatements are coded.
The following two programs may have different simulation results.
reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;end
initial begina = 1; b = 2;
end
reg [7:0] a, b, c;
initial begina = 1; b = 2;
end
always @ (a or b)begin
c = a + b;end
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One way to avoid race condition between always and initial statements,using #0, delay zero, may be recommended.
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g , y , y
reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;
end
initial #0begin
a = 1; b = 2;end
This means yield toall other statements.
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Question: For the verilog RTL code shown below, draw the expected resulton the time chart below.
t = 0 5 10 15 20 25 30
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reg clk;
reg [7:0] a, b, c;
always @ (posedge clk)begin
c = a + b;end
initial begina = 1; b = 2;#15 a = 3; b = 1;
end
always begin
clk = 1;#5 clk = 0;#5;
end
t = 0 5 10 15 20 25 30
1 0 1 1 10 0clk
1 3a
2 1b
c
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There exists a race condition between the two always statements, the resultmay be different depending on tools.
A sample answer.
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y p gThere are two possible results as shown below.
reg clk;reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;end
initial begina = 1; b = 2;#15 a = 3; b = 1;
end
always beginclk = 1;#5 clk = 0;#5;
end
1 0 1 1 10 0clk
1 3a
2 1b
c 3 4
c x 43
t = 0 5 10 15 20 25 30
Depending on the simulation tool, the resultsare different.
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Question: By using #0, avoid race condition as shown below.Which one of the codes will work without race condition?
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reg clk;reg [7:0] a, b, c;
always #0 @ (a or b)begin
c = a + b;end
initial begina = 1; b = 2;#15 a = 3; b = 1;
end
always beginclk = 1;#5 clk = 0;#5;
end
reg clk;reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;end
initial #0 begina = 1; b = 2;#15 a = 3; b = 1;
end
always beginclk = 1;#5 clk = 0;#5;
end
reg clk;reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;end
initial begina = 1; b = 2;#15 a = 3; b = 1;
end
always #0 beginclk = 1;#5 clk = 0;#5;
end
Code 1 Code 2 Code 3
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A sample answer.
Code 1 and Code 3 may not cause racing. With code 2, wait is executedafter the first clock rise. With code 3, clock rises after wait for clock rise is
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executed. Code 2 can not solve the racing between two always statements.
From this viewpoint if eliminating x appearing in the result, code 3 may be better.
reg clk;reg [7:0] a, b, c;
always #0 @ (a or b)begin
c = a + b;end
initial begina = 1; b = 2;#15 a = 3; b = 1;
endalways begin
clk = 1;#5 clk = 0;#5;
end
reg clk;reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;end
initial #0 begina = 1; b = 2;#15 a = 3; b = 1;
endalways begin
clk = 1;#5 clk = 0;#5;
end
reg clk;reg [7:0] a, b, c;
always @ (a or b)begin
c = a + b;end
initial begina = 1; b = 2;#15 a = 3; b = 1;
endalways #0 begin
clk = 1;#5 clk = 0;#5;
end
Code 1 Code 2 Code 3
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A