CHNG I

Trung tm nghin cu v o to thit k vi mch ICDREC

Mc lc

1CHNG I

1I) TNG QUAN

2II) QUI TRNH THIT K VI MCH

31)System spec

32)System design

33)Logic design

64)Layout

75)Test Design

76)Mask making

8CHNG II

8I) GII THIU

81) S lc

82) Tm quan trng ca HDL

93)Verilog HDL

9II) THIT K S VI VERILOG

91)Phng php thit k

132)Cc mc m t trong VerilogHDL

14III) CU TRC V CCH VIT MT MODULE

141) Module

162) Cc mc m t

183)Qui c t vng

194)Kiu d liu

295)Cc php ton

336)Cc pht biu

40CHNG III

40I) TNG QUAN

42II) HNG DN THIT K VI QUARTUS II

431)Bt u

452)Khi to mt project

523)Thit k u vo dng Verilog

584)Bin dch mch c thit k:

635)Gn chn (pins assignment)

676)M phng mch c thit k

CHNG I

GII THIU QUI TRNH THIT K VI MCH

I) TNG QUAN

thit k ra cc chip ICs s thng thng ngi ta da trn qu trnh Basic platform development flow

Hnh 1.1: Tng quan v thit k chip

Trc khi thc hin mt thit k ta cn phn tch, xc nh cc c tnh k thut ca IC s bng cch tm hiu xu hng th trng, cc yu cu ca khch hng. T a ra cc c trng (spec) ca h thng, cc thng s k thut: hot ng ca h thng (performance), tiu hao nng lng (power dissipation), tin cy, gi c

Trong qu trnh thit k ta cn quan tm:

Ti u ha h thng: rt gn cc phn d, m t khng cn thit.

Cn phn tch trnh cc tnh hung, yu t c th lm thay i h thng. V d: Chiu di dy ni, cu trc cc khi, phn tng thit k c th lm thay i tn s hot ng ti a, cng sut tiu tn ca chip

V mt k thut ta cn quan tm n spec, v cc thng s k thut khc: tn s hot ng, kch thc, cng ngh ch to.

Cc h thng ln thng c xy dng ln bng cch k tha cc h thng nh c sn. Kt hp v pht trin cc h thng nh c c h thng ln. Tp hp cc h thng nh ny c lu gi trong th vin. y chnh l qu trnh hnh thnh cc th vin thit k (cc library cell).

Ngoi cc library cell, khi ch to chip ta cn cn c thm cc th vin cng ngh, cc lut, quy tc thit k

Trn y l tng quan v qu trnh thit k chip. Vy qui trnh thit k vi mch s gm cc bc no?

II) QUI TRNH THIT K VI MCH

hiu v qu trnh thit k ta c th quan st hnh 1.2

Hnh 1.2: Qui trnh thit k vi mch

1) System spec

M t yu cu chc nng ca h thng. Phn ny s c c hai bn l nh sn xut v khch hng cng kt hp thc hin.

Khch hng s a yu cu ca mnh. Nh thit k s da vo cc cng ngh v cc thit k thc t iu chnh thit k cho ph hp.

2) System design

T yu cu chc nng ca thit k, h thng, cc chuyn gia s phn tch v a ra m hnh cc khi chc nng, th t v cc sp xp ca tng khi, ni dung, chc nng ca tng khi.

Xy dng lung thit k v a ra thi gian c lng thit k.

3) Logic design

a) RTL_design: S dng ngn ng m t phn cng VerilogHDL hay VHDL m t thit k.

V d:

module mux (x1,x2,slect,out );

input x1,x2; // tn hiu ng vo

input slect; // tn hiu chn

ouput reg out;// tn thiu ng ra

always @ (x1 or x2 or slect)

begin

if (slect)out = x1; else out = x2;

end

endmodule

b) Thit k sau khi c m t bng HDL s kim tra. Bc ny cn gi l RTL verification

Trong phn ny ta s s dng cc chng trnh VCS, Module_Sim, kim tra syntax, m phng chc nng v timing.

Hnh 1.3: Kim tra chc nng

Vic kim tra syntax l kim tra cu trc h thng da trn cc lut, qui tc thit k. T phn mm s kim tra v thng bo cc li trong thit k.

Hnh 1.4: Kim tra nh th

Thng thng, kim tra chc nng, nh th h thng s c thc hin trn s dng sng (vector waveform). Da trn s nh th ta c th quan st c quan h ng vo v ng ra, s thay i cng nh thi gian delay ca cc tn hiu. T ta c th kim tra c chc nng v a ra tn s hot ng ti a ca mch.

1 Logic synthesis:

H thng c thit k nhiu cp (level) hay cn gi l mc. Trong khi trong library ch cha thng s ca cc cell c bn (standard cell). Chnh v vy ta cn tng hp file HDL ch bao gm cc cell c bn. File ny cn c gi l gate level netlist file (file netlist mc cng).

Cng vic ny c thc hin bi phn mm c tn l Design Compiler (DC)

2 Logic Verification

Sau khi tng hp ra c file netlist mc cng ta phi kim tra li v chc nng cng nh timing mt ln na. Phn ny cn c gi l Logic Verification. Vic kim tra Logic Verification bao gm:

i. Function Simulation: Kim tra qu trnh thay i ca cc tn hiu khi c 1 s kin xy ra (thay i ca tn hiu ng vo)

ii.Timing Verification: C 2 phng php kim tra nh th ca mt h thng

1.(STA) Static Timing Analysis

2.(DTA) Dynamic Timing Analysis

Phn tch timing tnh (STA) l phng php phn tch timing da trn l thuyt. C 2 cng thc chnh trong phn ny cn c quan tm

Hnh 1.5: STA

Phn tch timing ng (DTA) da trn hot ng ca mch phn tch. Cc yu t c quan tm phng php ny l qu trnh np x ca t k sinh, nhiu cross-talk

4) Layout

a)Floorplan: Thit k hnh dng v kch thc IC. Th t kch thc cc pin, kch thc v cch phn b cc pad (chn).

i. Yu cu ca bc ny l thit k to ra vng chip ln cha cc cell v c th chy cc lp kt ni.

ii. Kch thc ca chip cng ln cng khng tt nhng li d i dy hn v ngc li.

iii. Trong qu trnh thc hin layout ta cn ch n h s Cell/Chip. H s ny th hin t l gia tng din tch cc Cell trn tng din tch Chip. L tng th h s ny s bng 1. Trn thc t iu ny khng th thc hin c. i vi cc chuyn gia thc hin layout c kinh nghim th c th thc hin c cc chip c h s cell/chip ti u l 0,7 0,8.

b)P&R: Gm vic

i.t cc cell, macro (Place)

ii.Rout cc net

5) Test Design

Sau khi thc hin layout xong ta cn kim tra li ln cui. Lc ny ta c c kch thc, cc kt ni vt l tht ca chip. V vy vic kim tra timing v function lc ny l chnh xc nht. V lc ny ta cng c th d on, v phn tch trc cc nhiu c th xy ra. c bit l cc nhiu cross-talk

y cng l khu quan trng v:

Sau phn ny l khu sn xut chip.

Chi ph sn xut mt loi chip rt cao. Chnh v th nu IC thit k c li m phn ny khng pht hin ra th sn phm ra s b li v khng c kh nng sa cha.

6) Mask making

y l cng on thit k vt l. Da vo cc m hnh, file cha cc thng s ca cc lp ngi ta s to ra cc mt n (mask) cho tng lp.

Khu ny s c thc hin nh my (Factory). V y cng chnh l mt khu trong qu trnh sn xut chip.

CHNG II

HDL (Hardware Description Language)

I) GII THIU

1) S lc t rt lu cc ngn ng lp trnh nh FORTRAN, Pascal, v C c s dng m t cc chng trnh ca my tnh, l mt chui cc lnh s c my tnh thc thi. n gin trong vic thit k s, ngi thit k cn mt ngn ng chun m t cc mch in. T Hardware Description Languages (HDLs) hay cn gi l ngn ng m t phn cng ra i

Ngn ng m t phn cng (HDL) l mt loi ngn ng th hin cc thit k phn cng thng qua bng cc pht biu bng li (ch vit).

C 2 ngn ng thng dng: Verilog HDL v VHDL.

2) Tm quan trng ca HDLHDL cho php ngi thit k m t thit k ca mnh cp rt tru tng. Ngi thit k m t thit k ca mnh m khng cn quan tm n cng ngh ch to. Cc cng c tng hp logic c th t ng chuyn i thit k cho ph hp vi cng ngh ch to mong mun. Khi c mt cng ngh ch to mi ra i th ngi thit k khng cn phi thit k li h thng. Cng c tng hp s tng hp li thit k c file netlist mc cng mi, c ng dng cng ngh ch to mi. Cng c tng hp logic s ti u ha din tch mch in v nh th cho ph hp vi cng ngh mi.

Khi m t thit k trong HDLs, phn kim tra chc nng ca thit k s c lm sm nht trong thit k mch. Khi lm vic mc RTL, ngi thit k c th ti u ha, thay i m t t c thit k c chc nng mong mun. Hu ht tt c cc li thit k c loi tr, chnh sa trong bc ny.

Thit k vi HDLs cng ging nh lp trnh my tnh. Cc mu m t vi cc ch thch s lm n gin hn cho vic pht trin v kim tra li. N cn cung cp nhng trnh by ngn gn cho thit k hn so vi thit k mc cng. Thit k mc cng th y chi tit nhng li qu phc tp.

3)Verilog HDLVerilog HDL l mt ngn ng m t phn cng a mc ch d hc, d s dng. N c cu trc n gin tng t ngn ng lp trnh C. i vi ngi thit k c kinh nghim trong lp trnh vi ngn ng C s thy d dng khi hc v Verilog.

Verilog cho php ngi thit k m t thit k nhiu cp : m t hnh vi, m t lung d liu, m t mc cng, thanh ghi hoc kt hp gia cc mc ny. Do ngi thit k ch cn hc mt ngn ng duy nht cho nhiu loi thit k khc nhau.

Hu ht cc cng c tng hp u h tr ngn ng Verilog. Do , Verilog ngy cng tr nn ph bin v l s la chn ca cc nh thit k.

Tt c cc nh sn xut u cung cp th vin VerilogHDL tng hp thit k. Do , vic s dng Verilog cho php chng ta la chn nh sn xut.

II) THIT K S VI VERILOG

1) Phng php thit k

d thit k ngi ta thng chia nh cng vic ra gii quyt.

Sau khi chia nh thit k ngi ta c th thc hin thit k theo 2 phng php t trn xung (top-down) hay t di ln (bottom-up).

Top-down l phng php thit k thc hin thit k cc khi top trc sau mi thit k cc khi chnh, cui cng mi thit k cc khi cell l (leaf cell). Top-down design i hi ngi thit k rt cn thn v tun th cht cc nguyn tc trong thit k. Cc module con c gi khi cha c thit k. Hnh 2.1 m t phng php thit k Top-down

Hnh 2.1 Phng php thit k Top-down

Bottom-up l phng php thit k m trong chng ta s xy dng cc khi nh trc. Sau cc khi thit k ln hn s c xy dng t cc khi thit k nh ny. Tng bc xy dng ln cc khi cp cao hn cho n khi xy dng ln c top module. Hnh 2.2 m t v vic thit k Bottom-up

Hnh 2.2: Phng php thit k bottom_up

Ch :

1 Ngy nay ngi ta thng kt hp c 2 phng php trn rt ngn thi gian thit k chip.

2 V tnh c lp tng i ca hai phng php ny nn ta c th cho php c nhiu nhm cng hot ng thit k tng b phn ca chip. ng thi cng c nhm ghp cc module ny li vi nhau.

3 Vic thit k theo phng php ny i hi ngi qun l phi c kh nng kim sot tin cng vic tt. V cng cn c quy tc chung cho cc nhm khi thit k sn phm c th n khp vi nhau.

V d: Thit k b m ln 4 bit.

Hnh 2.3: B m ln 4 bit s dng T_FFs

Phn tch thit k, ta thy b m ln ny gm cc T_FFs. Vy ta c th coi cc T_FFs nh l cc Sub_cell, hay macro cell.

c T_FFs, ta c th c xy dng t cc D_FFs v cc cng Not.

Hnh 2.4: Bng chn tr v cu to ca T_FFs.

Ta c th chia nh thit k trn thnh cc thit k n gin hn. T ta c s thit k ca b m 4 bit nh sau

Hnh 2.5: S phn cp ca thit k.

i vi phng php Top-down th ta s thit k b m bng cc ni cc T_FFs li vi nhau. Sau mi thit k cc T_FFs. Trong thit k cc T_FFs c s dng ti cc D_FFs nhng cc khi m t ca D_FFs vn cha c xy dng. Cui cng l ta s xy dng cc cell l, chnh l D_FFs v cng o.

i vi phng php Bottom-up thit k s c thc hin t di ln. C th l cc cell l (D_FFs v cng o) s c xy dng trc. Sau mi kt hp cc cell l xy dng ln cell T_FFs. B m s c xy dng cui cng

2)Cc mc m t trong VerilogHDLTrong Verilog ta c nhiu cp m t:

M t mc trng thi (hnh vi).

M t mc lung d liu.

M t mc cng.

M t mc Switch.

Verilog cng cho php ngi thit k kt hp bn mc m t ny trong cng mt module.

Trong Verilog mi khi m t c gi l mt module. Trong mt module ta c th gi th hin ca cc module cp thp hn.

So snh C language v HDL:

C language

L ngn ng vit iu khin CPU.

Cc lnh trong C c thc hin mt cch tun t.Verilog HDL

L ngn ng thit k mt h thng trong c th c c CPU.

Cc khi (module) chc nng trong HLD c thc hin song song, hoc tun t ty vo ngi lp trnh.

III) CU TRC V CCH VIT MT MODULE

1) Module Verilog a ra mt khi nim l module. Module l mt khi c bn c xy dng trong Verilog. Mt module c th l mt thnh phn hoc mt tp hp cc khi thit k nh hn. Mt module phi din t, th hin c cc giao tip bn ngoi cng nh ni dung bn trong ca khi. Ni dung ny c th c m t mc cu trc, lung d liu hay m t hnh vi.

Hnh 3.1: V d v module n ginTrn y l mt module nh c m t gm cc php tnh logic n gin.

Vy cu trc ca mt module gm nhng g?

Hnh 3.2: Cu trc mt module

Thng thng cu trc ca mt module s bao gm 4 phn chnh:

Khai bo, nh ngha module.

Khai bo port xut, nhp v tn hiu bn trong module.

M t chc nng ca module.

Kt thc module.

Quay li phn tch v d trn ta c th hiu r hn v cu trc ca module.

Phn tch v d.

1 Trong module th cc port xut nhp phi c khai bo bng cc t kha: input, output.

2 Cc tn hiu bn trong ca module cng c khai bo dng cc Register hoc cc Net

3 Cc Register c dng cho cc tn hiu c kh nng t lu tr d liu.

4 Cc Net trong Verilog din t mt kt ni vt l trong phn cng. N c th c dng ni cc module hay cng li vi nhau, nhng bn thn n khng th t lu tr gi tr.

5 Mt wire c th c dng bt c ch no trong module, n ch c gn bi:

Ng ra ca mt module, cng.

Gn vi mt php gn lin tc.

Cc php gn lin tc c khai bo bng lnh assign. Tt c cc php gn lin tc u c thc hin ng thi

Ta s phn tch chi tit kt cu ca mt module trong phn sau. By gi ta cn lm quen vi cc khi nim trong Verilog.2) Cc mc m t

Verilog h tr cho ngi thit k m t h thng nhiu cp khc nhau.

Mc m t hnh vi: L cp m t tru tng cao nht. Module c hin thc trong cc iu kin mong mun thit k v mt logic. M khng quan tm n vic thc hin v mt phn cng. Do vy cp thit k ny Verilog s ging vi ngn ng C nht.

Mc m t lung d liu: mc ny ngi thit k phi ch r lung d liu. Ngi thit k phi hiu c lung d liu gia cc thanh ghi, hiu c d liu s c x l nh th no trong thit k.

Mc m t mc cng: Module c th hin gii hn mc cng v s kt ni gia cc cng

Mc m t Switch: L mc m t cp thp nht m Verilog cung cp. Module c thc hin da vo cc iu khong ca cc switch, cc storage nodes, v kt ni ca chng. 3)Qui c t vng

Cng ging vi ngn ng C, Verilog cha mt chui cc k t qui c (token). Cc k t c th l ch thch, delimiter , s, chui, nh danh v t kha.

a) Khong trng

Cc kiu khong trng: Blank space (\b), tabs (\t) v dng mi (\n) khng c s dng trong Verilog t tn cc bin, v ch c dng tch bit cc token. Trong cc chui, khng c php rt gn cc khong trng. lc ny khong trng cng c coi nh l mt k t: k t khong trngb) Ch thch

Cc ch thch c chn vo code lm r, gii thch thit k

x = y && y; // y l ch thch mt dng

/* y l ch thch nhiu

dng */

/* y l /* ch thch */ vi phm */

/* y l //ch thch hp l */Thng thng cc ch thch cn c canh l thng hng vi nhau d c v khng lm ri thm cho ni dung chng trnh. Phn trnh by trong khi vit Verilog s c trnh by k trong phn ph lc cui tp sch.

c) Ton t :

C 3 loi ton t: unary (n nguyn), binary (nh nguyn) v ternary (tam nguyn).

x = ~y; // ton t n nguyn.

x = y || z; // ton t nh nguyn.

x = y ? z : t; // ton t tam nguyn.

d) Ch s:

Trong Verilog ch s c th l cc hng s hoc thng s (parameter). N c th c biu din binary, octal, hexadecimal hoc decimal

Hnh 3.3: Cc kiu nh dng ca s

Tin t i trc mt con s nh ngha cho rng (s bit),v nh dng ca con s . Nu ta khng qui nh kch thc th khi tng hp s qui nh rng bit cho tng tn hiu. Gi tr rng ny ph thuc vo trnh bin dch, v thng cng chnh bng gi tr ca my tnh ang thc hin bin dch.

V d:

8b 11000011 // ch s nh phn 8 bit

20hFE_2ACD// ch s hex 20 bit

e) S m: -8d5 // s -5 8-bit biu din dng b-2.

8d-5// m t khng hp l.f) K t gch di: Trong con s c dng d c.

V d:

12b1111_0000_1010

// s 111100001010

4)Kiu d liu

Verilog nh ngha 3 kiu d liu chnh l:

Net.

Register.

Parameter.

a)Kiu Net: Biu din kt ni gia nhng phn t phn cng. N c ngha nh cc ng ni dy. N c khai bo bi cc t kha:

wire

tri

supply0

supply1

wand

wor

i. Kiu wire v tri l 2 kiu d liu ging nhau v mt s dng (cu trc v chc nng). Chng c 2 tn lm cho thit k c r rng.

Cc Net c li bi mt cng thng c khai bo kiu wire.

Cc Net c li bi nhiu cng thng c khai bo l tri.

ii.supply1 v supply0 l 2 kiu net m t ngun (VCC) v t (GND).

V d: khai bo mt tn hiu ni t vi tn GND

supply0 GND ;

ii. Kiu wor v wand l kiu m cc kt qu ca n s c or hay and li vi nhau.

V d

b)Kiu Register

Kiu thanh ghi c khai bo bi t kha reg.

Reg c th c coi ging nh mt bin trong Verilog.

Trong khi net khng th lu tr gi tr th reg c th lu tr gi tr .

Khi mt bin c gn gi tr trong mt khi always @ ( ) c kch bng cnh, th cc FFs s c tng hp bi trnh tng hp. Ta cn trnh s cc D_ff lm cc reg.

c)Kiu Parameter

thun tin trong vic thay i gi tr ca cc hng s, Verilog h tr mt kiu d liu l kiu Parameter- Kiu parameter dng khai bo cc constants (hng s) trong Verilog.

- Cc parameter c nh ngha:

parameter n = 8;

- Ta c th thay i cc gi tr ca parameter khi gi th hin ca module cha cc parameter . iu ny s c lm r hn trong phn sau: Gi th hin ca mt module

V d: Thc hin b mux 4( 1

Ch :

ion code trn cho thy s khc bit gia wire v tri.

Nu tn hiu result_int m ta khai bo l wire s b trnh tng hp bo li.

i vi tn hiu wire th ch c php c tn hiu li pha trc.

Cn i vi tri th ta cho php nhiu hn 1 tn hiu li pha trc n.

iion code trn m t chc nng ca b chn knh mux 4 1

iiiTn hiu intreg v result c gn gi tr ngay ti cnh ln ca wrclk nn phi c khai bo l regivTn hiu sel lun nhn gi tr t selector hay ni cch khc sel c th coi nh l ng ni dy t tn hiu selector nn c khai bo l wired)Mng cc regs v mng cc nh

Vector:

- Net hoc cc kiu d liu reg c th c khai bo di dng cc vector ( rng nhiu bit). Nu khng c ch r, mc nh l 1-bit.

- Cch nh a ch cho tng bit c th theo qui tc little endian hoc big endian u c chp nhn

V d:

B nh.

- Trong cc thit k c b nh, ta thng cn m hnh tp thanh ghi (register file), RAM, ROM. Phn t nh c m hnh ha trong Verilog dng di cc thanh ghi.

- Mi phn t ca di c xem l mt word. Mi word c 1 hay nhiu bit.

- Ta ch c th truy cp mt word m khng th truy cp vo bit trong word.

V d

// B nh A c 1k t 1-bit

reg A [0:1023];

// B nh B c 1k t 1-byte

reg [7:0] B [0:1023];

// Tm np t 1-byte a ch 511

membyte[511]e)Cc php gn

i. Php gn lin tc

- Cc php gn lin tc c s dng gn gi tr n cc net v port.

- Php gn lin tc c to ra khi ta mt net c khai bo, hoc bng pht biu assign

V d:

wire [0:1]sel = selector ;

assign [0:1] sel = selector;

V d

y l cch khai bo b mux 41 s dng php gn lin tc thc hin

ii. Cc php gn th tc

- Php gn th tc dng cp nhp gi tr thanh ghi.

- Php gn th tc cho php s dng theo kiu blocking v non-blocking.

- Kiu blocking, c trng bi du =, php gn kiu ny tn hiu c cp nht gi tr c (trc pht biu) ca tn hiu li.

- Kiu non-blocking, c trng bi du

6 Ton t iu kin:

V d:

assign x = t ? a : b

Gii thch

Nu t = 1: x = a

t = 0 : x = b

6)Cc pht biu

a)Pht biu if () else

Pht biu iu kin if() else l mt cu trc pht biu c dng ch cc iu kin quyt nh.

V d: M t mch chn knh 4:1module mux_case (source, ce, wrclk, selector, result);

input [0:3]source;

input ce, wrclk;

input [0:1]selector;

output result;

reg [0:3]intreg;

reg result, result_int;

always @(posedge wrclk)

begin

// if statement for chip enable on register

if (ce)

intreg = source;

result = result_int;

end

always @(intreg or selector)

begin

// if-else construct for multiplexer functionality

if (sel == 2b00)

result_int = intreg[0] ;

else if (sel == 2b01)

result_int = intreg[1] ;

else if (sel == 2b10)

result_int = intreg[2] ;

else if (sel == 2b11)

result_int = intreg[3] ;

end

endmoduleb)Pht biu case

Cu trc:

Nu c nhiu iu kin cng iu khin h thng th s dng pht biu if else s rt phc tp. V vy Verilog cn h tr pht biu case.

V d :

module traffic (clock, sensor1, sensor2,

red1, yellow1, green1, red2, yellow2, green2);

input clock, sensor1, sensor2;

output red1, yellow1, green1, red2, yellow2, green2;

parameter st0 = 0, st1 = 1, st2 = 2, st3 = 3,

st4 = 4, st5 = 5, st6 = 6, st7 = 7;

reg [2:0] state, nxstate ;

reg red1, yellow1, green1, red2, yellow2, green2;

always @(posedge clock)

state = nxstate;

always @(state or sensor1 or sensor2)

begin

red1 = 1b0; yellow1 = 1b0; green1 = 1b0;

red2 = 1b0; yellow2 = 1b0; green2 = 1b0;

case (state)

st0: begin

green1 = 1b1;

red2 = 1b1;

if (sensor2 == sensor1)

nxstate = st1;

else if (~sensor1 & sensor2)

nxstate = st2;

end

st1: begin

green1 = 1b1;

red2 = 1b1;

nxstate = st2;

end st2: begin

green1 = 1b1;

red2 = 1b1;

nxstate = st3;

end

st3: begin

yellow1 = 1b1;

red2 = 1b1;

nxstate = st4;

end

st4: begin

red1 = 1b1;

green2 = 1b1;

if (~sensor1 & ~sensor2)

nxstate = st5;

else if (sensor1 & ~sensor2)

nxstate = st6;

end

st5: begin

red1 = 1b1;

green2 = 1b1;

nxstate = st6;

end

st6: begin

red1 = 1b1;

green2 = 1b1;

nxstate = st7;

end

st7: begin

red1 = 1b1;

yellow2 = 1b1;

nxstate = st0;

end

endcase

end

endmodule

So snh pht biu case vi ifelse

input [0:2] sel;

casex (sel)

3b10x: ...

3bx10: ...

3bx11: ...

3b00x: ...

default: ....

endcasePht biu ny tng ng vi pht biu di y:

wire [0:1] data;

if (data == 2)

...........

else if (data == 1)

...........

else if (data == 3)

...........

else if (data == 0)

...........

else

// Ignored for synthesis purpose

endmodulec)Pht biu for

Cng ging trong C, Verilog cng h tr pht biu for n gin trong cch th hin khi ta cn lp li mt php tnh nhiu ln. V d

...

input clk ;

reg [4:0] input_signal, result ;

reg enable ;

always @ (posedge clk)

for (i = 0; i < 5; i = i + 1)

result[i] = enable & input_signal[i] ;

...

1 Cc pht biu iu kin cn phi nm trong cc khi always mi khng b bo li.

2 Nu cn thc hin cc php tnh c iu kin nm ngoi khi always ta cn rt gn cc php tnh ny cc t hp logic ri biu din, hoc dng ton t iu kin ? : gii quyt.

CHNG III

HNG DN S DNG QUARTUS II

I) TNG QUAN

Bng hng dn ny gii thiu h thng thit k c s tr gip ca my tnh (CAD computer-aided design) Quartus II, cung cp 1 ci nhn tng quan v lung CAD in hnh thit k mch c thc hin trn thit b FPGA ng thi cng ch ra th no lung CAD ny c th c to ra trn phn mm Quartus II. Quy trnh thit k c gii thiu bng cch a ra nhng hng dn tng bc mt dnh cho vic s dng phn mm Quartus II to mt mch rt n gin trn thit b FPGA ca Altera.

H thng Quartus II mang n s h tr hon chnh cho tt c cc phng php a m t mch cn thit k vo trong h thng CAD. Bi hng dn ny s dng phng php thit k u vo dng Verilog trong ngi dng xc nh mch mong mun bng ngn ng m t phn cng VerilogHDL (Hardware description language).

Bc cui cng trong qu trnh thit k lin quan n vic lp trnh mch mong mun ln thit b FPGA thc. ch ra vic ny c thc hin nh th no, gi s rng ngi dng c board Altera DE1 c kt ni vi my tnh ci Quartus II. Ngi c khng c board DE1 vn thy bi hng dn ny hu ch hc ci cch m cng vic lp trnh v cu hnh cho thit b FPGA c thc hin.

Nhng hnh chp mn hnh my tnh trong bi hng dn ny c c t phin bn Quartus II 8.0; nu phin bn khc ca phn mm ny c dng th hnh v s hi khc mt cht.

Phn mm CAD lm cho vic thit k mch lun l mong mun s dng thit b lun l lp trnh (logic programable) chng hn nh chip FPGA. Mt lung thit k FPGA dng CAD in hnh c trnh by minh ha di y:

Hnh 3.1 Lung thit k FPGA

Lung thit k CAD gm cc bc sau y:

Thit k u vo: mch thit k mong mun c th c xc nh bng s mch hay dng ngn ng m t phn cng nh VHDL hoc Verilog.

Tng hp: Mch c thit k s c tng hp thnh mt mch gm cc phn t logic c trn FPGA.

M phng chc nng: Mch c tng hp s c kim tra xc nh tnh chnh xc v chc nng. Vic m phng ny khng c cha cc vn nh thi.

t mch ln board (fitting): Cng c CAD fitter s quyt nh v tr ca cc phn t logic c nh ngha trong s chn (netlist) vo cc phn t logic thc trn chip FPGA. N cng chn nhng ng dy trn chip kt ni cc phn t logic cn thit.

Phn tch nh th: Tr trong qu trnh truyn (propagation delays) rt nhiu ng dn (path) trong mch c gn trn board s c phn tch cung cp nhng thng s hot ng ca mch mong mun.

M phng nh th: Mch c t trn board s c kim tra c v chc nng ln nh th.

Lp trnh v cu hnh: mch c thit k s c np vo mt chip FPGA thc bng cch lp trnh cc kha cu hnh (configuration switches) m to ra cc phn t logic ng thi thit lp cc ng dy ni cn thit.

II) HNG DN THIT K VI QUARTUS II

Bi hng dn ny s cung cp nhng tnh nng c bn ca phn mm Quartus II. N ch ra lm th no phn mm ny c th c s dng thit k v thc hin mch bng cch s dng ngn ng m t phn cng Verilog. N s dng giao din ha khi to cc lnh. Lm bi hng dn ny ngi c s hc v:

Khi to mt project

Thit k u vo dung Verilog

Tng hp mch c xc nh bng Verilog

Gn mch c thit k ln chip FPGA ca Altera

Gn u vo v u ra ln cc chn (pins) trn chip FPGA

M phng mch thit k

Lp trnh v cu hnh cho thit b FPGA trn kit DE1 ca Altera

Kim tra mch thit k

1) Bt u

Mi mch logic hay mch con c thit k trong Quartus II c gi l mt project. Phn mm s lm vic trn mt project trong mt thi im v lu tr tt c nhng thng tin cho project mt th mc n trong tp tin h thng (system file). bt u mt thit k logic mi, bc u tin l to ra mt th mc cha tt c cc tp tin (file) ca n. lu tr cc tp tin cho bi hng dn ny chng ti s dng th mc introtutorial. V d sp ti cho bi hng dn ny s l mt mch n gin dng cho vic iu khin n hai chiu.

Khi ng Quartus II chng ta s thy mt ca s c hin th nh hnh 3.2. S hin th ny bao gm vi ca s cung cp truy xut n rt nhiu tnh nng ca Quartus II m ngi dng s la chn bng chut (computer mouse). a s cc lnh m phn mm Quartus II cung cp u c th truy xut bng mt tp hp cc trnh n (menu) t di thanh tiu (title bar).V d trong hnh 3.2, nhp chut tri vo trnh n c tn File s m ra th mc c trnh by hnh 3.3. Nhp tri chut ln u vo Exit s thot khi phn mm Quartus II. Ni chung bt k khi no s dng chut chn mt th g th ta dng chut tri. Do chng ta thng s khng xc nh nt (botton) no c bm. Trong mt vi trng hp khi chut phi c dng th s c ch ra mt cch tng minh.

Hnh 3. 2: Hin th chnh ca Quartus

i vi mt vi cu lnh c khi cn thit phi truy xut hai hay nhiu hn trnh n tun t. Ta s s dng thng l Menu1>Menu2> Item ch ra rng chn cu lnh mong mun ngi dng u tin phi nhp chut tri ln Menu1 sau trong trnh n ny nhp Menu2 v sau trong trnh n Menu2 nhp Item. V d: File >Exit dng chut thot khi h thng. Rt nhiu lnh c th c kch khi bng cch nhp chut ln biu tng (icon) c hin th trn mt trong s cc thanh cng c (toolbar). xem thng tin lin quan n mt biu tng no , ta tr chut ln trn biu tng v mt ci tooltip (mo cng c) s xut hin v hin th tn lnh.

Phn mm Quartus II cung cp nhng ti liu hc thut trc tuyn (online) tr li rt nhiu nhng cu hi c th ny sinh trong qu trnh s dng phn mm. Ti liu c th c truy xut thng qua trnh n Help. c mt vi tng v tm vc ca ti liu c cung cp, i vi ngi c vic duyt qua (browse) trnh n Help l rt ng gi. V d chn Help > How to use Help a ra nhng kiu tr gip c cung cp.

Ngi dng c th nhanh chng tm kim cc ch tr gip bng cch chn Help > Search s m ra mt hp thoi (dialog box) trong bn c th nhp cc t kha. Mt phng php na l tr gip hng ng cnh (context sentivity) c cung cp dnh cho vic tm kim ti liu nhanh chng nhng ch xc nh. Trong khi s dng a s cc ng dng (application) nhp phm chc nng F1 m phn tr gip c cha cc cu lnh sn c cho ng dng.

2) Khi to mt project

bt u lm vic trn mt thit k mi chng ta u tin phi nh ngha mt project thit k mi. Phn mm Quartus gip cho cng vic ca ngi thit k tr nn d dng bng cch cung cp tr gip di dng mt wizard. to ra mt project mi nh sau:

a) Chn File > New Project Wizard tip cn ca s nh hnh 3.3 (i vi phin bn 6.0) m ch ra kh nng ca wizard ny. Bn cng c th b qua ca s ny bng cch nhp vo hp (box) Dont show me this introduction again. Tip theo nhp Next i n ca s hnh 3.4.

Hnh 3.3: Nhng cng vic c thc hin bi Wizard

Hnh 3.4: Khi to mt project mi

b) Khi to th mc lm vic l introtutorial, tt nhin bn c th s dng nhng th mc khc m bn thch hn. Project phi c mt ci tn thng l phi trng vi i tng thit k cp cao nht (top level entity) c a vo trong d n. Chn light cho c Project v i tng thit k cp cao nht nh c ch ra hnh 3.4. Nhp Next, bi v chng ta cha to ra th mc introtutorial, Quartus II s hin th mt hp pop-up hi xem n c nn to ra th mc mong mun. Nhp Yes s dn n hnh 3.6.

Hnh 3.5: Phn mm Quartus II c th to ra mt th mc cho d n

Hnh 3.6: Wizard c th a vo nhng tp tin thit k m ngi dng xc nh

c) Wizard lm cho vic xc nh nhng tp tin c sn (nu c) c a vo project mt cch d dng. Gi s chng ta khng c tp tin c sn no, nhp Next dn n hnh 3.7.

Hnh 3.7: Chn h thit b v nhng thng s mong mun

d) Chng ta phi xc nh loi thit b m trn mch thit k s c to ra. Cyclone II l h thit b c dng. Ta cng c th cho Quartus II chn thit b trong h (family) nhng ta cng c th chn thit b mt cch tng minh. Ta chn phng php sau. T danh sch nhng thit b sn c chn thit b c tn gi l EP2C20F484C7C6 l FPGA c s dng trn board DE1. Bm Next s hin ra ca s hnh 3.8.

Hnh 3.8: Nhng cng c EDA c th c xc nh

e) Ngi dng c th xc nh bt k cng c EDA ca hng th ba c th c dng. Mt thut ng thng c s dng trong thit k CAD cho mch din t l EDA l cm t vit tc ca Electronic Design Automation ( T ng ha thit k in t). Thut ng ny c dng trong Quartus II ch nhng cng c ca hng th ba (third-party), l nhng cng c c pht trin v a ra th trng bi nhng cng ty khc Altera. Bi v chng ta s da hon ton vo Quartus II nn s khng chn bt k cng c no. Nhn Next.

f) Mt bng tm tt cc thng s xut hin trn mn hnh nh ch ra hnh 3.9. Nhp Finish s tr v ca s Quartus II chnh vi light c ch ra nh l Project mi trn thanh tiu nh hnh 11.

Hnh 3.9: Tm tt nhng thng s d n

Hnh 3.10: Hin th ca Quartus II cho Project c to ra

3) Thit k u vo dng Verilog

Nh l v d thit k, chng ta s s dng mch iu khin n hai chiu nh ch ra hnh 3.11. Mch c th c s dng iu khin mt n dng hai kha x1 v x2 mt kha ng tng ng vi mc logic 1. Bng s tht (truth table) cng c cho trong hnh v ny. Lu l ch l hm Exclusive OR ca hai u vo x1 v x2 nhng ta s xc nh n bng cch dng cng

Hnh 3.11: Mch iu khin n

Mch c m t bng Verilog nh hnh 3.12. Lu l module Verilog c gi l light cho trng vi tn hnh 3.4 m c xc nh khi Project c to ra. M ny c th c g vo mt tp tin bng cch s dng bt k mt b son tho vn bn no c lu tr tp tin ASCII hoc dng tin tch son tho vn bn ca Quartus II. Tp tin c th c t tn bt k nhng trong thc t thit k thng s dng tn trng vi tn ca module Verilog cp cao nht (toplevel). Tn tp tin phi c phn m rng l .v ch ra l tp tin Verilog. Do chng ta s dng tn light.v.

Hnh 3.12: M Verilog cho hnh 3.11

a) S dng b son tho vn bn Quartus II

Phn ny s ch ra lm th no dng phn mm son tho vn bn QuartusII. Bn c th b qua phn ny nu bn thch dng mt b son tho vn bn khc to ra tp tin m ngun Verilog m chng ta s t tn l light.v.

Chn File > New n ca s hnh 3.13 chn VerilogHDL file. Nhp OK, ca s son tho. Bc u tin l xc nh tn cho tp tin s to ra. Chn File > Save as m hp popup minh ha hnh 3.14. Trong hp c nhn l Save as Type chn VerilogHDL File, trong hp c nhn File name g light. t mt du chn (checkmark) trong hp Add file to current Project . Nhp Save s lu tp tin vo trong th mc introtutorial v dn n ca s son tho nh hnh 3.15. M rng cc i ca s son tho v nhp m Verilog trong hnh 13 vo. Lu tp tin bng File > Save hay nhn t hp phm Clt + S.

a s nhng cu lnh c sn trong b son tho u c tnh nng t gii thch (selfexplainatory). Vn bn c nhp vo im nhp (insertion point), c ch ra bi mt ng thng dc mng. im nhp c th di chuyn c bng cch dng ci phm di chuyn trn bn phm hay bng chut. Hai tnh nng c bit thun tin cho vic son tho m Verilog. Trc tin, b son tho c th hin th cc cu lnh khc nhau bng nhng mu khc nhau, y l mt s la chn mc nh. Th hai l b son tho t ng li dng cho nhng an m mi sao cho ph hp vi dng m trc . Nhng ty chn c th c iu khin bng cc thng s Tool > Options > Text Editor.

Hnh 3.13: Chn la chun b mt tp tin Verilog

Hnh 3.14: t tn tp tin

Hnh 3.15: Ca s trnh bin son

Trong bi ny ta cn thc hin mch t hp ca hai tn hiu ng vo l x1 v x2. Di y m t code ca chng trnh c thc hin:module light (x1,x2,f);

input x1,x2;

output f;

assign f = (x1&~x2) | (~x1&x2);

endmodule

i vi ngi thit k c php (syntax) ca Verilog i khi rt kh nh. tr gip vn ny, b son tho cung cp mt tp hp nhng khun mu Verilog. Khun mu bao gm nhiu kiu cu lnh Verilog chng hn nh: khai bo module, khi always v nhng cu lnh gn.

b) a nhng tp tin thit k vo d n:

Nh chng ta ch ra khi ni v hnh 3.16, chng ta c th ni cho phn mm Quartus II nhng tp tin thit k no n c th dng nh l nhng thnh phn ca Project hin ti. xem danh sch cc tp tin c a vo trong Project light, chn Assignments > Settings s dn n ca s nh hnh 3.16. Pha bn tri ca hnh v, nhp vo Files. Mt cch thc hin vic chn la ny l dng Project > Add and remove files from Project .

Nu bn s dng phn mm son tho Quartus II v nh du chn vo hp c nhn Add file to current project , nh trnh by phn 3.1 th tp tin light.v l mt phn ca project v c lit k ca s hnh 3.16. Nu khng th phi a tp tin vo d n. Do , nu bn khng s dng phn mm son tho Quartus II bn mt bn sao ca light.v m bn to ra s dng mt trnh son tho no khc vo trong th mc introtutorial. a tp tin vo d n, nhp nt File name trong hnh 3.16 c c hp popup nh hnh 3.17. Chn tp tin light.v v nhp Open. Tp tin c la chn by gi c ch ra trong ca s Files ca hnh 3.18. Chn OK a tp tin light.v vo trong d n. Chng ta nn ch l trong mt vi trng hp phn mm Quartus II c kh nng t ng tm c ng cc tp tin cn thit s dng cho tng i tng (entity) c tham kho trong m Verilog thm ch khi tp tin cha c a vo project mt cch tng minh. Tuy nhin trong nhng project phc tp c nhiu tp tin nn a tng tp tin mong mun vo trong project nh cch lm trn l mt kinh nghim thc t hu ch.

Hnh 3.16: Ca s thng s

Hnh 3.17: La chn tp tin

4) Bin dch mch c thit k:

M Verilog trong tp tin light.v c x l bi rt nhiu nhng cng c ca Quartus II phn tch m, tng hp mch v to ra mt thc thi cho chip ch (target chip). Nhng cng c ny c iu khin bi mt chng trnh ng dng gi l trnh bin dch (Complier).

Chy b bin dch bng cch chn Processing > Start compilation hay nhp vo biu tng trng ging nh mt hnh tam gic mu tm. Qu trnh bin dch tri qua nhiu giai on, tin trnh ca n c bo co ca s bn tri ca mn hnh Quartus II. Vic bin dch thnh cng hay tht bi c ch ra trong mt hp popup. Xc nhn iu ny bng cch nhp OK. Dn n mn hnh Quartus II trong hnh 3.18. Trong ca s thng ip, trong ca s pha di ca hnh v rt nhiu thng ip c hin th. S c nhng thng ip ph hp c hin th trong trng hp c li xy ra.

Hnh 3.18: Hin th sau khi bin dch thnh cng

Hnh 3.19: Bng tm tt sau khi ch chy Analysis & Syntheis

Khi bin dch hon thnh, mt bo co bin dch c to ra. Mt ca s bo co t ng c hin th nh ch ra hnh 3.18. Ca s c th c thay i kch thc, m rng ti a hay ng theo cch thng thng v c th c m bt c lc no bng cch chn Processing > Compilation report bng cch chn tiu hnh . Bo co bao gm mt s phn c lit k bn tri ca ca s ny. Mt bng tm tt ca trnh bin dch (hnh 3.18) ch ra rng ch cn dng mt phn t lun l v 3 chn (pins) to ra mch ny trn chip FPGA c chn. Mt phn na c ch ra hnh 3.19. Thc hin iu ny bng cch chn Analysis & Synthesis > Equations bn tri ca ca bo co bin dch. y chng ta thy biu thc logic c to ra bi b bin dch c tng hp mch c thit k. Nhn thy l c dn ra bi:

F = x1 $ x2

y du $ c dng ch Exclusive OR ton t. R rng trnh bin dch nhn ra rng biu thc lun l trong tp tin thit k ca chng ta tng ng vi biu thc ny.

Phn mm Quartus II hin th cc thng ip c to ra trong qu trnh bin dch ca s thng ip (message window). Nu tp tin thit k Verilog l ng, mt trong s nhng thng ip s ch ra rng bin dch thnh cng v khng c li. Nu trnh bin dch c thng bo li, c ngha l c t nht mt li trong m Verilog. Trong trng hp ny mt thng ip tng ng vi li c tm thy hin th trong ca s thng ip. Nhp kp vo mt thng ip li s lm ni bt cu lnh vi phm trong m Verilog ca s son tho. Tng t, ca s thng ip cng hin th nhng cnh bo (warnings). Chi tit v n cng c th c khm ph theo cng mt cch nh trong trng hp ca thng ip li. Ngi dng c th ly nhiu thng tin hn v thng ip li hay cnh bo bng cch chn thng ip v nhn phm chc nng F1.

thy nh hng ca li, m tp tin light.v. Loi b du chm phy trong cu lnh assign s minh ha mt li cu trc (topographical) thng mc phi. Bin dch tp tin thit k c li bng cch nhp chut vo tiu hnh . Mt hp popup s hi xem nhng thay i trong tp tin light.v c c lu tr khng? Nhp Yes. Sau khi c gng bin dch mch thit k, phn mm Quartus II s hin th mt hp popup ch ra s bin dch khng thnh cng. Xc nhn iu ny bng cch nhp OK. Bng tm tt bo co bin dch cho hnh 3.20 khng nh kt qu tht bi. M rng phn Analysis and Synthesis v chn Message c nhng thng ip c hin th hnh 3.21. Nhp kp thng ip li u tin. Phn mm Quartus II s p ng bng cch m tp tin thit k light.v v lm ni bt (hightlight) cu lnh b nh hng bi li nh ch ra hnh 3.23. Sa li v bin dch li thit k.

Hnh 3.20: Bo co bin dch cho thit k b tht bi

Hnh 3.21: Thng ip li

Hnh 3.22: Xc nh v tr ca li

5) Gn chn (pins assignment)

Trong qu trnh bin dch trn, b bin dch Quartus II la chn bt k chn no trong thit b FPGA c chn lm u vo v u ra. Tuy nhin board DE1 c nhng kt ni dy c nh gia chn ca FPGA v nhng linh kin khc trn board. Chng ta s s dng hai kha bt tt (toggle switches) c gn nhn SW1 v SW2 cung cp nhng u vo bn ngoi x1 v x2 cho mch v d ca chng ta. Nhng kha ny c kt ni n chn N25 v N26 tng ng ca FPGA, chng ta s kt ni u ra n 1 LED mu xanh l cy c dn nhn l LEDG0 c ni cng vo trong chn AE22 ca FPGA.

Hnh 3.23: Ca s gn chn

Vic gn chn c thc hin bng Assignment Editor. Chn Assignments > Pins n ca s hnh 3.23. Category chn Pin. Nhp kp vo entry c lm ni bt bng mu xanh dng ct c dn nhn To. Mt trnh n s xung (drop down menu) s xut hin. Nhp vo x1 l chn u tin c gn. iu ny s a x1 vo trong bng hin th. Tip theo nhp kp vo hp bn tay phi ca entry x1 hp dn nhn l Location. By gi mt trnh n s xung nh hnh 3.25 s xut hin. Cun xung v chn chn PIN_N25. Thay v cun xung chn chn mong mun bn c th ch g ci tn ca chn (N25) trong hp Location. Dng cng mt th tc gn u vo x2 ti chn N26 v u ra f n chn AE2 kt qu nh hnh 3.26. lu nhng php gn ny chn File > Save. Bn cng c th n gin ng ca s Assignment Editor, trong trng hp ny mt hp popup s hin ra v hi bn c mun lu nhng thay i v vic gn khng. Nhp Yes. Bin dch li mch m n c th c gn chn ng nh mong mun.

Hnh 3.24: Hp thoi s xung hin th u vo v ra

Hnh 3.25: Nhng chn sn c

Hnh 3.26: Gn hon chnh

Board DE1 c gn chn c nh. Khi hon thnh mt thit k ngi dng mun s dng cng mt php gn cho nhng thit k sau . Mt c tnh hu dng ca Quartus II cho php ngi dng va nhp v xut gn t mt nh dng tp tin c bit thay v to ra chng bng tay nh vi Assignment Editor. Mt nh dng tp tin n gin c th c s dng cho mc ch ny l nh dng command separated value (CSV) l mt dng tp tin vn bn thng dng cha nhng gi tr khng b gii bn bi du phy. nh dng tp tin ny thng c dng lin kt vi tp tin bng tnh Excel ca Microsoft. Nhng tp tin cng c th to ra bng tay dng bt k trnh son tho ASCII no. nh dng tp tin cho v d n gin ca chng ta l:

ToLocation

X1PIN_N25

X2PIN_N26

FPIN_AE2

Bng cch a nhng dng ny vo tp tin bt k mt php gn no cng c th c to ra. Chng hn nhng tp tin csv c th c nhp vo Project thit k.

Nu bn lm php gn chn cho mt Project no , bn c th xut n s dng cho mt Project khc. thy vic ny c lm nh th no, mt ln na m Assignment Editor c ca s hnh 3.26. By gi chn File > Export dn n ca s hnh 3.27. y tp tin light.csv sn sng xut. Nhp vo Export. Nu by gi bn nhn vo th mc introtutorial bn s thy tp tin light.csv c to ra.

Hnh 3.27: Xut gn chn

Bn c th chn Assignments > Import assignments s m hp thoi nh hnh 3.28 chn tp tin s nhp vo. G tn ca tp tin bao gm phn m rng .csv v ng dn ton phn (full path) ti th mc cha tp tin trong hp File Name v nhp OK. Tt nhin bn cng c th duyt tm tp tin mong mun.

Hnh 3.28: Nhp php gn chn cho thun tin khi s dng nhng thit k ln, tt c nhng php gn chn tng ng cho board DE1 c cho trong tp tin DE1_pin_assignments.csv trong th mc DE1_tutorials\design_files trong CD ROM i km vi board DE1 ng thi cng c th tm thy trn trang web ca DE1 altera. Tp tin ny dng tn c tm thy trong DE1 User Manual (S tay ngi dng DE1). Nu bn mun gn chn cho mch v d ca chng ta bng cch nhp tp tin ny chng ta phi s dng cng mt tn trong tp tin Verilog vi tn l SW[0], SW[1] v LEDG[0] cho x1, x2 v f tng ng. Bi v ba tn hiu ny c xc nh trong tp tin DE1_pin_assignments.csv nh l nhng phn t vector SW v LEDG chng ta phi tham kho chng theo cng mt cch trong tp tin Verilog. V d trong tp tin DE1_pin_assignments.csv c 18 ci kha bt tt c gi t SW[0] n SW[9]. Trong m Verilog chng c th c tham chiu nh l vector SW[9:0].

6) M phng mch c thit k

Trc khi thc hin mch thit k ln chip FPGA trn board DE1, m phng n xc nhn tnh chnh xc. Phn mm Quartus II c mt cng c m phng c th dng m t c tnh (behavior) ca mch thit k. Trc khi mch c th m t, cn thit phi to ra nhng dng sng mong mun (waveforms) c gi l vector kim tra biu din tn hiu u vo. Cng cn phi xc nh u ra cng nh nhng im bn trong mch m ngi thit k mun thy. B m phng p dng nhng vector kim tra cho m hnh ca mch c thc thi v quyt nh p ng mong mun. Chng ta s s dng Quartus II Vector Waveform v nhng vector kim tra ny nh sau:

a. M Waveform Editor bng File > New s dn n ca s hnh 3.30. Chn Vector Waveform file v nhp OK.

b. Ca s Waveform Editor c m t hnh 3.31. Lu tp tin di tn l light.vwf. Lu l iu ny s lm thay i tn trong ca s c hin th. Thit lp thi gian m phng mong mun t 0 n 400 ns bng cch chn Edit > End time v nhp 400 ns vo hp thoi m ra. Chn View > Fit in window hin th ton b di m phng trong ca s nh hnh 3.32. Bn c th mun thay i kch thc ca s ln ti a

Hnh 3.30: Chun b mt tp tin vector kim tra

Hnh 3.31: Ca s Waveform Editor

Hnh 3.32: Mt on trong Waveform Editor

c. Bc tip theo ta mun a nhng im (node) u vo v ra ca mch c m phng. Nhp Edit > Insert Node or Bus m ra ca s nh hnh 3.33. C th g tn ca tn hiu vo trong hp Name nhng bm vo nt nhn c nhn Node Finder m ca s hnh 3.34. Tin ch Node finder c mt b lc dng tm cc loi node. Bi v ta mun tm chn u vo (inputs) v u ra (outputs) thit lp b lc n Pins: all. Bm nt List tm u vo v ra nh bn tri ca hnh v.

Hnh 3.33: Hp thoi nhp Bus hay Node

Hnh 3.34: Chn node a vo Waveform Editor

Nhp vo tn hiu x1 trong hp thoi Node found v nhp k hiu > a n vo trong hp cc node c chn bn pha bn phi ca hnh v. Lm ging nh th cho x2 v f. Nhp OK ng ca s Node Finder v sau nhn OK trong ca s hnh 3.33. Ca s Waveform Editor s c hin th hon ton nh hnh 3.35. Nu bn khng chn node ging nh th t trong hnh 3.35 bn c th sp xp li chng. di chuyn mt node ln hay xung trong Waveform Editor chn tn Node (trong ct Name) v th chut. Dng sng (waveform) c lm ni bt ch ra s chn la. Nhp mt ln na vo dng sng v r n ln xung trong Waveform Editor.

Hnh 3.35: Nhng node cn thit cho m phng

d. Chng ta s xc nh cc gi tr lun l c dng cho tn hiu u vo x1 v x2 trong qu trnh m phng. Gi tr u ra f s c to ra t ng trong qu trnh m phng. d v cc dng sng mong mun, Waveform Editor hin th mc nh nhng phng hng (guidelines) v mang n nhng c tnh v chen vo nhng ng ny (hay cng c th c kch khi bng cch chn View > Snap to grid). Bn cng s thy mt ng m dc c th c di chuyn bng cch tr vo u ca n v r theo chiu ngang. ng tham chiu ny c dng cho phn tch nh th mt mch. Di chuyn n n v tr time = 0. Dng sng c th c v dng cng c Selection Tool c kch hot bng cch nhp vo tiu hnh trn thanh cng c hay Waveform editor tool c kch hot bng tiu hnh .

m t c tnh ca mt mch ln p dng mt s y nhng nh tr u vo v nhn thc gi tr mong mun u ra. Trong mt mch ln, s gi tr u vo c th ln nn trong thc t ta s chn mt mu tng i nh nhng gi tr u vo ny. Tuy nhin, vi mch nh ca ta, chng ta c th m phng tt c nhng gi tr u vo cho trong hnh 3.11. Chng ta s dng 4 khong 50 ns p dng cho 4 vector kim tra.

Chng ta c th to ra nhng dng sng u vo nh sau. Nhp vo tn dng sng cho node x1. Mt khi dng sng c chn, nhng cu lnh son tho trong Waveform Editor c th c dng v dng sng mong mun. Nhng cu lnh sn c cho vic thit lp mt tn hiu ti gi tr 0, 1, khng bit (X) (unknown), tr khng cao (high impedance) (Z), dont care (DC), o gi tr tn ti (INV) hay nh ngha mt dng sng xung clock.Mi cu lnh c th c kch hot bng Edit > Value hay thng qua thanh cng c dnh cho Waveform Editor. Trnh n Edit cng c th c bng cch nhp phi vo tn dng sng.

t x1 l 0 trong khong thi gian t 0 n 100ns chc chn c t mc nh. Tip theo t x2 l 1 trong khang thi gian t 100 n 200 ns. Lm iu ny bng cch nhp chut vo u khong v r n n cui khong s lm ni bt khong c chn v chn gi tr 1 trn thanh cng c. t x2 l 1 t 50 n 100ns v cng nh th t 150 n 200ns tng ng vi bng s tht (truth table). iu ny s to ra hnh 3.36. Nhn thy l u ra f c hin th c gi tr unknown trong khong thi gian ny c ch ra bng nhng mu gch cho. Gi tr ca n s c quyt nh trong qu trnh m phng. Lu tp tin li.

Hnh 3.36: Thit lp nhng gi tr kim tra

e . Thc hin m phngMch c thit k c th c m phng theo hai cch. Cch th nht l gi s cc phn t lun l v dy ni trong FPGA l hon ho do khng gy ra tr trong qu trnh truyn tn hiu qua mch. Ci ny gi l m phng chc nng (functional simulation). Mt phng php phc tp hn xem xt c tr ca mch dn n m phng nh th (timing simulation). Thng th m phng chc nng c dng m phng tnh chnh xc ca mch ang c thit k. Cch ny chim t thi gian v m phng c th c thc hin n gin bng cc biu thc lun l nh ngha mch.

- M phng chc nng: thc hin m phng chc nng, chn Assignments > Settings ca s Settings. Bn pha bn phi ca ca s ny nhp vo Simulator hin th ca s hnh 3.37 chn ch m phng functional v nhn OK. B m phng Quartus II ly u vo v to u ra c nh ngha trong tp tin light.vwf. Trc khi chy m phng chc nng cn thit phi to ra s ni dy (netlist) bng cch chn Processing > Generate functional simulation netlist. M phng c kch khi bng Processing > Start Simulation hay bng cch nhp biu tng . Cui giai on m phng, Quartus II s hin th mt bo co m phng nh hnh 3.38 bo hon tt vic m phng. Nu ca s thit k khng ch ra ton b khong thi gian m phng nhp vo ca s bo co m phng chn n ri dng View > Fit in Window. Xem xt u ra f c xc nh trong bng s tht.

Hnh 3.37: Xc nh ch m phng

Hnh 3.38: Kt qu m phng chc nng

- M phng nh th: xc nhn rng chc nng ca mch thit k l ng. By gi chng ta s thc hin m phng nh th xem n s c thc hin nh th no khi c thc hin trn chip FPGA thc chn. Chn Assignments > Settings > Simulator c ca s nh hnh 3.37 v chn ch m phng Timing, nhp OK. Chy b m phng s to ra dng sng nh hnh 3.39. Thy rng c mt s tr khong 6ns trong vic to ra s thay i gi tr ca f khi gi tr ca hai tn hiu u vo x1 v x2 thay i gi tr. S tr ny l do s truyn tr (propagation delays) trong cc phn t lun l v dy ni trong thit b FPGA. S khng ng u (glitch) cng do s tr truyn trong thit b FPGA do s thay i ca x1 v x2 khng n chnh xc thi m cc phn t mch to ra f.

Hnh 3.39: Kt qu m phng nh th

f. Lp trnh v cu hnh thit b FPGA

Thit b FPGA phi c lp trnh v cu hnh thc hin mch thit k. Tp tin cu hnh c to ra bi Quartus II Compliers Assembler. Board DE1 cho php vic cu hnh c thc hin theo 2 cch l ch JTAG v AS. D liu cu hnh c truyn t my tnh (c ci chng trnh Quartus II) bi mt si dy cp kt ni cng USB trn my tnh vi kt ni USB ngoi cng bn tri trn board. s dng kt ni ny cn USB Blaster driver. Nu driver ny cha c ci tham kho Getting started with Alteras DE1 Board cho nhng thng tin v ci t driver. Trc khi dng board phi kim tra xem cp USB c ni ng cha v cp ngun c bt cha.

Trong ch JTAG, d liu cu hnh c np trc tip ln FPGA. Cm t JTAG vit tt ca Joint Test Action Group, nhm ny nh ngha mt cch n gin cho vic kim tra mch in t s v np d liu vo chng tr thnh mt chun ca IEEE. Nu FPGA c cu hnh theo cch ny n s vn gi nhng thng tin cu hnh min l ngun cn m. Thng tin cu hnh s mt khi tt ngun. Cch th hai l dng AS (active serial). Theo cch ny th thit b c cu hnh c b nh Flash lu tr thng tin cu hnh. Phn mm Quartus II t d liu cu hnh vo thit b cu hnh trn board DE1. Sau , thng tin ny s c np vo FPGA. Do FPGA khng cn phi cu hnh nu ngun b tt hay m. Vic chn la gia hai ch ny c thc hin bng kha Run/Prog trn board DE1. V tr RUN dnh cho JTAG cn PROG dnh cho AS.

- Ch JTAG

Cng vic lp trnh v cu hnh c thc hin nh sau. Chuyn kha RUN/PROG n v tr RUN. Chn Run > Programmer tin n ca s hnh 41. y cn phi xc nh phn cng lp trnh v ch cu hnh. Nu cha c chn mc nh chn JTAG trong hp Mode. Nu USB Blaster cha c chn mc nh nhn Hardware Setup v chn USB Blaster trong ca s m ra nh hnh 3.40.

Hnh 3.40: Ca s b lp trnh

Thy rng tp tin cu hnh light.sof c lit k trong ca s hnh 3.40. Nu tp tin cha c lit k th chn Add files v chn n. N l mt tp tin nh phn c to ra bi Compliers Assembler cha nhng d liu cn thit cho vic cu hnh thit b FPGA. ui m rng .sof vit tt ca SRAM Object File. Lu l thit b FPGA c chn l EP2C20F484C7 l FPGA s dng trn Board DE1. Nhp vo chn Program/configure nh hnh 3.42.

Hnh 3.41: Ca s ci t phn cng

Hnh 3.42: Ca s b lp trnh c cp nht

- Ch lp trnh Active Serial (AS)

Trong trng hp ny d liu cu hnh c np vo thit b lp trnh trn board DE1 c xc nh bng EPCS16. xc nh thit b cu hnh chn Assignments > Device dn n ca s hnh 3.43. Nhn vo nt Device & Pin options ti ca s hnh 3.44. By gi nhp th Configuration c ca s hnh 3.45. Trong hp Configuration device (c th c t t ng) chn EPCS16 v nhp OK. Tr v ca s 3.43 nhp OK. Bin dch li mch.

Hnh 3.43: Ca s thng s thit b

Hnh 3.44: Ca s ty chn

Hnh 3.45: Xc nh thit b lp trnh

Phn cn li ca th tc tng t phn JTAG. Chn Tools > programmer c li ca s 3.42. Trong phn Mode chn Active Serial Programming.

Lc ny s xut hin ca s nh hnh 3.47, bn hy trong mc Hardware setup c dng USB-Blaster. Nu file cu hnh cha c lit k trong ca s, nhn ADDFILE. Mt khung xut hin nh hinh 3.48, chn file light.pof trong th mc introtutorial ri click OPEN. Lc ny file light.pof s c lit k trong ca s. y l file nh phn cha d liu c ti v t EPCS16. Quay li ca s proprammer, nhn chut vo phn bn di Program/Configure nh hnh 3.49.

Hnh 3.47. ca s chng trnh vi chui chng trnh c chn

Hnh 3.48: chn file cu hnh

Hnh 3.49: ca s chng trnh c cp nht

Trn kit DE1, ti v tr RUN/PROG , y qua v tr PROG. Nhn Start trong ca s hnh 3.49. Mt led s sng trn kit khi d liu cu hnh c ti thnh cng.

Khi qu trnh cu hnh v thc hin c hon tt, Progress s hin th nh hnh 3.50

Hnh 3.50: chng trnh c hon tt

e. Kim tra mch thit k

Sau khi ti d liu cu hnh trong trong thit b FPGA, bn c th kim tra mch c thc hin. y v RUN trn kho RUN/PROG. Th tt c 4 gi tr u vo t 2 gi tr x1 v x2 bng cch thay i trng thi ca cc kho SW0 v SW1. Kim chng li bng bng s tht hnh 3.11

Nu bn mun thay i mch thit k, trc ht phi ng ca s chng trnh li, sau thay i trong file thit k Verilog, bin son v thc hin li mch nh gii thch trn.

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