* MIPS R-type - I-type : add, sub, or, xor, and, slt, lw, sw, beq, j : bne, addi, jal, jr

ALU

*

* (1) FETCH = " -PC.(2) DECODE = ( ).(3) EXECUTE = -ALU , .(4) MEMORY = : (Store) (Load).(5) WRITE BACK = .

*

- , ( )

* Single cycle data pathsProcessor uses synchronous logicdesign (a clock).

fT1 MHz1 s10 MHz100 ns100 MHz10 ns1 GHz1 ns

* Edge-Triggered D Flip FlopsValue of D is sampled on positive clock edge.Q outputs sampled value for rest of cycle.DQ

* Single cycle data paths: DefinitionAll instructions execute in a single cycle of the clock (positive edge to positive edge)Advantage: a great way to learn CPUs.Drawbacks: unrealistic hardware assumptions,slow clock period

* Recall: MIPS R-format instructionsFetch next inst from memory:012A4020 Retrieve register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program.Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10

* Separate Read-Only Instruction MemoryReads are combinational: Put a stable address on input, a short time later data appears on output. () (Instruction Memory & Data Memory)

* 1: Straight-line Instruction FetchFetching straight-line MIPS instructions requires a machine that generates this timing diagram:Why +4 and not +1?Why do we increment every clock cycle?

Single-cycle Implementation of MIPSOur first implementation of MIPS will use a single long clock cycle for every instructionEvery instruction begins on one up (or, down) clock edge and ends on the next up (or, down) clock edgeThis approach is not practical as it is much slower than a multicycle implementation where different instruction classes can take different numbers of cyclesin a single-cycle implementation every instruction must take the same amount of time as the slowest instructionin a multicycle implementation this problem is avoided by allowing quicker instructions to use fewer cyclesEven though the single-cycle approach is not practical it is simple and useful to understand first

Note : we shall implement jump at the very end

* New Component: Register (for PC)In later examples, we will add an enable input: clock edge updates state only if enable is high32DinClkPCDout32

* New Component: A 32-bit adder (ALU)

* Design: Straight-line Instruction FetchClk32AddrDataInstrMem32DPCQ3232+32320x4+4 in hexadecimalState machine design in the service of an ISA

* Fetch next inst from memory:012A4020 Retrieve register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program.Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10Goal #1: An R-format single-cycle CPU

* Register files:R1R2...R31Why is R0 special?QQQDDDEnEnEn32

* Register File Schematic SymbolWhy do we need WE (Write Enable)?If we had a register file w/o WE, how could we work around it?

Datapath: Instruction Store/Fetch & PC Increment Three elements used to store and fetch instructions andincrement the PCDatapath

Animating the DatapathInstruction

Datapath: R-Type InstructionTwo elements used to implementR-type instructionsDatapath

Animating the Datapathadd rd, rs, rtR[rd]

Datapath: Load/Store InstructionTwo additional elements usedTo implement load/storesDatapath

Animating the Datapathlw rt, offset(rs)R[rt]

Animating the Datapathsw rt, offset(rs)MEM[R[rs] + sign_extend(offset)]

Datapath: Branch InstructionDatapathNo shift hardware required:simply connect wires from input to output, each shiftedleft 2 bits

Animating the Datapathbeq rs, rt, offsetif (R[rs] == R[rt]) then PC

MIPS Datapath I: Single-CycleInput is either register (R-type) or sign-extendedlower half of instruction (load/store)Combining the datapaths for R-type instructions and load/stores using two multiplexorsData is either from ALU (R-type)or memory (load)

Animating the Datapath: R-type Instructionadd rd,rs,rt

Animating the Datapath: Load Instructionlw rt,offset(rs)

Animating the Datapath: Store Instructionsw rt,offset(rs)

MIPS Datapath II: Single-CycleAdding instruction fetchSeparate instruction memoryas instruction and data readoccur in the same clock cycleSeparate adder as ALU operations and PC increment occur in the same clock cycle

MIPS Datapath III: Single-Cycle Adding branch capability and another multiplexorInstruction address is eitherPC+4 or branch target addressExtra adder needed as bothadders operate in each cycleNew multiplexorImportant note: in a single-cycle implementation data cannot be stored during an instruction it only moves through combinational logicQuestion: is the MemRead signal really needed?! Think of RegWrite!

Datapath Executing addadd rd, rs, rt

Datapath Executing lwlw rt,offset(rs)

Datapath Executing swsw rt,offset(rs)

Datapath Executing beqbeq r1,r2,offset

* Fetch next inst from memory:012A4020 Retrieve register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program.Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10Goal #1: An R-format single-cycle CPU

* Computing engine of the R-format CPUDecode fields to get : ADD $8 $9 $10 LogicWhat do we do with WE?

* Putting it all together ...LogicIs it safe to use same clock for PC and RegFile?To rs1,rs2, ws, op decodelogic ...

* Reminder: How data flows after posedgeDPCQ

* Next posedge: Update state and repeatDPCQ

* A CPU capable of R-type instructions onlyInstructionMemoryPCAdder46[31:26]6[5:0]=funct ?

* . -decode( -write back)Readregister 1RegistersReadregister 2Write registerWriteDataReaddata 1Readdata 2 Data

* Arithmetic Logic operationReadregister 1RegistersReadregister 2Write registerWriteDataReaddata 1Readdata 2ALUZeroALU operationInstructionALUALUresultALU operation R-type

* A CPU capable of R-type instructions onlyReg FileInstructionMemoryPCALUAdder46[31:26]6[5:0]=funct ?

* A CPU capable of R-type instructions onlyReg FileInstructionMemoryPCALUAdder46[31:26]6[5:0]=funct ?

* The internal structure of the Register File3232323232323232323232Read data 2write dataRead data 1555Rd reg 2 (= Rt)Rd reg 1 (= Rs)RegWriteWr reg (= Rd) 3232E ( )

* A CPU capable of R-type instructions onlyReg FileInstructionMemoryPCALUAdder46[31:26]RegWrite

* A CPU capable of R-type instructions onlyReg FileInstructionMemoryPCALU

* A CPU capable of R-type instructions onlyReg FileInstructionMemoryPCALU4

* A CPU capable of R-type instructions onlyReg FileInstructionMemoryPCALUAdder46[31:26]RegWrite6[5:0]=functALUcontrol

* 2: I-format ALU instructionsSyntax: ORI $8 $9 64Semantics: $8 = $9 | 64

Zero-extend: 0x8000 0x00008000Sign-extend: 0x8000 0xFFFF8000Some MIPS instructions zero-extend immediate field, other instructions sign-extend.

* Computing engine of the I-format CPUDecode fields to get : ORI $8 $9 64 In a Verilog implementation, what should we do with rs2?3232

* Merging data paths ...I-formatR-formattwo read portsHow many ?Where ?

* The merged data path ...ALUctr

* Load,Store ReadaddressDatamemoryWriteaddressWritedataReaddataWriteRead - data sign extension - imm 16bit

* Loads, Stores, and Data Memory ...Syntax: LW $1, 32($2) Syntax: SW $3, 12($4) Action: $1 = M[$2 + 32]Action: M[$4 + 12] = $3Zero-extend or sign-extend immediate field?Writes are clocked: If WE is high, memory Addr captures Din on positive edge of clock.Note: Not a realistic main memory (DRAM) model ...

* - CPU?CPUInstructionMemoryDataMemoryPC

* A CPU capable of lw instructions onlyReg FileInstructionMemoryPCALUAdder46[31:26]RegWrite=116[15:0]5addSext16->32DataMemoryAddressD. Out

* A CPU capable of lw instructions onlyReg FileInstructionMemoryPCALUAdder46[31:26]RegWrite=116[15:0]5addSext16->32DataMemoryAddressD. Out

* A CPU capable of lw & sw instructions onlyReg FileInstructionMemoryPCALUAdder46[31:26]RegWrite=016[15:0]5addSext16->32DataMemoryD.InAddressMeWrite=1

* A CPU capable of R-type & lw instructions (principle)Reg FileInstructionMemoryPCALUAdder46[31:26]RegWrite16[15:0]5addSext16->32DataMemory6[5:0]=functALUcontrolAddress

* A CPU capable of R-type & lw instructionsReg FileInstructionMemoryPCALUAdder46[31:26]RegWrite16[15:0]5addSext16->32DataMemory6[5:0]=functALUcontrolRdAddressD. Out

* A CPU capable of R-type & lw/sw instructionsReg FileInstructionMemoryPCALUAdder46[31:26]RegWrite16[15:0]5addSext16->32DataMemory6[5:0]=functALUcontrolRdAddressD.InD. OutMemWrite

* Conditional Branches in MIPS ...Syntax: BEQ $1, $2, 12Action: If ($1 != $2), PC = PC + 4Zero-extend or sign-extend immediate field?Action: If ($1 == $2), PC = PC + 4 + 48Why is this encoding a good idea?

* :Branch ALUZeroReadregister 1RegistersReadregister 2Write registerWriteDataReaddata 1Readdata 2InstructionAdderSumShiftleft 2SighExtendBranchTarget 1632PC+4 - FetchIn addresses, we always shift left by two bits

* Design: Instruction Fetch with BranchClk32AddrDataInstrMem32DPCQ32Syntax: BEQ $1, $2, 12Action: If ($1 != $2), PC = PC + 4Action: If ($1 == $2), PC = PC + 4 + 48

* Readdata 1Readdata 2ZeroALUData32memoryWriteRead16Add4PCMuxInstructionADD

* What is single cycle control?ExtRegDestALUsrcExtOpALUctrEqualRegWr

* PCInstructionmemoryReadaddressInstruction1632AddMuxRegistersWriteregisterWritedataReaddata 1Readdata 2Readregister 1Readregister 24MuxALU operation3RegWriteMemReadMemWritePCSrcALUSrcMemtoRegALUresultZeroALUDatamemoryAddressWritedataReaddataMuxSignextendAddALU result

Shiftleft 2

* ControlPCInstructionmemoryReadaddressInstruction[310]Instruction [2016]Instruction [2521]AddInstruction [50]MemtoRegALUOpMemWriteRegWriteMemReadBranchRregister 2SignextendShiftleft 2Mux1ALUresultZeroDatamemoryWritedataReaddataMux1Instruction [1511]ALUcontrolALUAddress

* Control

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Instruction

RegDst

ALUSrc

Memto-Reg

Reg Write

Mem Read

Mem Write

Branch

ALUOp1

ALUp0

R-format

lw

sw

X

1.0

X

beq

X

0.0

X

* ALU controlALU control output 000 AND 001OR 010add 110subtract 111set-on-less-than (sign of rs-rt -> rd)00 = lw, sw 01 = beq, 10 = arithmetic

ALUop

* - jump4 bits 26 bits 2 bits00: : 0110 101 101111011 101 101111011 101 10111101100 101 1011110110110: : 4 : J 101101111011 1111110111001

* JumpShiftleft 2PCInstructionmemoryReadaddressInstruction[310]DatamemoryReaddataWritedataRegistersWriteregisterWritedataReaddata 1Readdata 2Readregister 1Readregister 2Instruction [1511]Instruction [2016]Instruction [2521]AddALUresultZeroInstruction [50]MemtoRegALUOpMemWriteRegWriteMemReadBranchJumpRegDstALUSrcIsultMux010ALUShiftleft 22628Address

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