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stant current charge-to-breakdown: Still a valid tool to study the reli-ability of MOS structures?,” in IEEE Int. Rel. Phys. Symp., 1998, pp.62–69.

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MOS Capacitors on Epitaxial Ge–Si Ge withHigh- Dielectrics Using RPCVD

X. Chen, S. Joshi, J. Chen, T. Ngai, and S. K. Banerjee

Abstract—We report the successful growth of MOS capacitor stacks withlow temperature strained epitaxial Ge or Si Ge ( = 0 9) layer di-rectly on Si substrates, and with HfO (EOT = 9 7 �A) as high- di-electrics, both using a novel remote plasma-assisted chemical vapor de-position technique. These novel MOS capacitors, which were fabricatedentirely at or below 400 C, exhibit normal capacitance–voltage and cur-rent–voltage characteristics.

Index Terms—Ge-epi-on-Si, high- , MOS, remote plasma-assistedchemical vapor deposition (RPCVD).

I. INTRODUCTION

High-� dielectrics on Ge have been recently studied in order to sig-nificantly reduce gate leakage while enhancing channel carrier trans-port in MOSFET application [1], [2]. However, these studies were onbulk Ge substrates, which have poor mechanical and thermal proper-ties, and high cost as compared to Si. Also, extra process complexity isinvolved in cleaning the unstable native oxide on Ge. Using a remoteplasma-assisted chemical vapor deposition (RPCVD) system, we haverecently demonstrated growth of the first MOS capacitor stacks withlow-temperature strained epitaxial Ge or Si1�x Gex(x = 0:9) layer di-rectly on Si substrates, and with HfO2 effective oxide thickness (EOT)= 9:7 �A as dielectric, both using our RPCVD system. The epitaxialGe or Si1�x Gex(x > 0:9) layer is of the order of the inversion layerthickness, which should effectively confine both electrons and holes inthe inversion layer under a gate bias and is potentially beneficial forhigh-mobility channel MOSFET application. In this brief, we investi-gate both physical and electrical characteristics of the MOS capacitors.

II. EXPERIMENTAL

The MOS capacitors were fabricated on p-type silicon substrates,which had 50 to 70 �A Ge or Si1�xGex(x = 0:9) epitaxial layersdeposited on them by RPCVD at 250 �C to 300 �C. Sample growthparameters are listed in Table I. During epitaxial layer deposition,plasma power, chamber pressure, substrate bias, GeH4, SiH4 and Arflows were modulated to control the interface and epitaxial quality.We then deposited 30 to 50 �A RPCVD HfO2 in another chamber inthe RPCVD system at 250 �C using a hafnium t-butoxide precursorwithout oxygen flow. After the samples were unloaded from RPCVDsystem, subsequent processing steps include post-deposition annealing(400 �C, 1 min, N2 ambient), TaN metal deposition using dc mag-netron sputtering, capacitor area patterning and reactive ion etching,and backside Al deposition and sintering (400 �C, 10 min). The entiredevice fabrication was performed at or below 400 �C. For comparison,MOS capacitors directly on Si substrate were also fabricated using thesame procedure.

Manuscript received September 17, 2003; revised April 27, 2004. This workwas supported in part by the Semiconductor Research Corporation (SRC), inpart by the MACRO Focus Center, the Micron Foundation, Texas Instruments,and in part by Applied Materials. The review of this brief was arranged by EditorG. Groeseneken.

The authors are with the Microelectronics Research Center, The Universityof Texas at Austin, Austin, TX 78758 USA (e-mail: banerjee@ece.utexas.edu).

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TABLE ISAMPLE GROWTH PARAMETERS

Fig. 1. High-resolution TEM image of TaN–HfO –Ge-epitaxy–Si-substratestack.

III. RESULTS AND DISCUSSION

The strained Ge and Si1�xGex epitaxial layers were confirmedby cross-sectional high resolution transmission electron microscopy(HRTEM) analysis as shown in Fig. 1. X-ray differential (XRD)characterization of the thin films was attempted but the measurementresults could not be matched satisfactorily to the simulation resultsdue to noise dominated measurement and difficult modeling of thinstrained films. HRTEM on thin bare Ge films and films cappedwith only the thin dielectric are difficult as the films can be easilydamaged due to the sample preparation procedure. Hence we choseto prepare transmission electron microscopy (TEM) samples withthe gate metal deposited on the gate dielectric. Owing to the lowtemperature metastable RPCVD growth, high–quality 65 �A epitaxialGe layer is achieved (Fig. 1), which is well beyond the predictedequilibrium critical layer thickness (CLT) (< 10 �A)). The threadingdislocation density was estimated to be less than 107–cm2 by countingline defects per unit area on plan view TEM images (not shown). TheRMS roughness for Ge and Si1�xGex epitaxial layers as determinedby atomic force microscopy is 1.4–1.5 �A, indicating a smooth surfacefor subsequent HfO2 growth. Smooth HfO2 deposition was achievedon both epitaxial Ge and Si, as shown in Figs. 1 and 2. Notice thatthe interfacial layer is � 10 �A on Si, but is less than 5-�A on a Geepitaxial layer presumably because Ge oxides tend to be volatile at ahigh temperature and under a high vacuum. We have compared (HfO2

deposition at 250 �C with and without plasma. X-ray photon spec-troscopy (XPS) analysis (Fig. 3) shows an Hf metal peak at 15 eV fordeposition without plasma, indicating an incomplete (HfO2 reaction.Also, the growth rate for RPCVD (HfO2 (70 �A=min) was found to betwice as that without a plasma. Hence, RPCVD is a feasible processfor low-temperature, (< 300 �C) high-� material growth.

Fig. 2. High-resolution TEM image of TaN–HfO (IL)–Si-substrate stack.

Fig. 3. XPS analysis of HfO films deposited with (solid line) and withoutplasma (dotted line). A Hf metal peak is observed for deposition without plasma.

The resulting MOS capacitors exhibit normal C–V characteristics,as illustrated in Fig. 4(a)–(c). The low-frequency curves (dotted lines)were calculated from the measured high-frequency capacitance withQM correction, indicating good agreement in accumulation and deple-tion regions and reasonable agreement in the inversion region. The ca-pacitors with Ge and SiGe layers show a flat band voltage shift as com-pared to the control samples which can be attributed to the worse inter-facial quality and even inter diffusion between the layers and the dielec-tric due to inferior oxides of these layers. The values of capacitance andleakage scale linearly with capacitor sizes indicating negligible edgeeffects. Equivalent oxide thickness (EOT) of (HfO2 on Ge is deter-mined to be 9.7 �A, which is significantly less than that on Si (20 �A),due to the lower interfacial thickness between (HfO2 and Ge. The ef-fective dielectric constant is 10–14. If the contribution of interfaciallayer is accounted for, the dielectric constant of HfO2 is 16–24, whichmakes RPCVD (HfO2 a very promising gate dielectric. The interfacestate density (Dit), extracted using the CVC program from NCSU 1 onHfO2–Si stack is � 1011–cm2, which is comparable to currently re-ported values [3]. TheDit on (HfO2–Ge–Si and (HfO2–Si1�xGex–Sistacks are of the order of 1012–cm2, probably due to the less stable in-terface characteristics between HfO2 and Ge or Si1�xGex layers. Thehigher values of the Dit are reflected in the slightly higher stretch outin the capacitance–voltage (C–V) of the samples with the Ge and SiGelayers. Leakage currents densities of these thin (HfO2 films at �1 Vare � 10�2 A/cm�2 with reasonably well behaved J–V characteris-tics (Fig. 5). These values are comparable with recent values with sim-ilar EOTs for gate stacks of (HfO2 on Si [4], [5], and are three ordersof magnitude lower than that of other reported HfO2 on Ge for sim-ilar EOTs [1]. We have attributed this significant leakage reduction toour capability of growing both epitaxial Ge layer and high-� dielectric

1CVC is a Program Developed by Dr. Hauser/N C State University.

1534 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004

Fig. 4. (a) Measured and simulated C–V characteristics of TaN–HfO –Sistack (Dit = 1:5 e cm EOT =20 �A) (b) Measuredand simulated C–V characteristics of TaN–HfO –Ge–Si stack(Dit = 3:7 e cm EOT =9:7 �A) (c) Measured andsimulated C–V characteristics of TaN–HfO –Si Ge –Si stack(Dit = 1:4 e cm EOT =14:5 �A)D and EOT values were extractedfrom the high frequency C–V curve. We used the CVC program by Dr. Hauserfrom NCSU.

layer in the same RPCVD system, thus avoiding possible interfacialcontamination effects. Even though these leakage current densities arelow, they are still not low enough to perform low frequency C–V mea-surements without being dominated by leakage current, especially onthe capacitors with the Ge and SiGe layers where the interface is un-stable.

In summary, we have demonstrated the successful low tempera-ture growth of MOS capacitor stacks with strained epitaxial Ge orSi1�xGex(x = 0:9) layer directly on Si substrates, and with HfO2

(EOT = 9:7 �A) as high-� dielectrics, both using a novel RPCVDtechnique. These well-behaved MOS capacitors showed that theRPCVD process is a very promising technique for low thermal budgetand high device performance applications.

REFERENCES

[1] C. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C.Saraswat, Proc. IEEE Device Research Conf., 2002, pp. 191–192.

Fig. 5. J–V characteristics of RPCVD HfO2on different stacks. The leakagecurrent is 10�2 A/cm2at�1 Vfor (HfO2(EOT � 9:7 �A)–Ge–Si stack.

[2] C. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C.Saraswat, IEDM Tech. Dig., 2002, pp. 437–440.

[3] L. Kang, B. H. Lee, W. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, andJ. C. Lee, IEEE Electron Device Lett., vol. 21, pp. 181–183, Feb., 2000.

[4] S. J. Lee, T. S. Jeon, D. L. Kwong, and R. Clark, J. Appl. Phys., vol. 92,no. 5, pp. 2807–2809, 2002.

[5] P. D. Kirsch, C. S. Kang, J. Lozano, J. C. Lee, and J. G. Ekerdt, J. Appl.Phys., vol. 91, no. 7, pp. 4353–4363, 2002.

Effects of Spacer Thickness on Noise Performance ofBipolar Transistors

Wai-Kit Lee, Sang Lam, and Mansun Chan

Abstract—The effects of spacer thickness on noise performance of abipolar junction transistor with different emitter widths and operationfrequencies are examined. The minimum noise figure ( ) derivedfrom the -parameters as well as the base ( ) and emitter resistance( ) obtained from the device simulation is used as a measure of noisecharacteristics. Furthermore, the noise resistance ( ), optimum sourceadmittance ( ), and the associated gain ( ) are also given inthis brief. To achieve the minimum value of , the spacer thicknessshould be targeted to an optimal value, and its value is frequency andgeometry dependent.

Index Terms—Bipolar transistors, modeling, SiGe heterojunctionbipolar transistors, spacer thickness.

I. INTRODUCTION

Base resistance plays an important role in determining the noiseperformance of a bipolar junction transistor (BJT) device. When theemitter width is scaled down, the spacer thickness becomes more im-portant in determining the overall base resistance. Although reducing

Manuscript received April 19, 2004; revised June 22, 2004. This work wassupported by the Research Grant Council of Hong Kong under Grant HKUST6207/02E. The review of this brief was arranged by Editor M. J. Deen.

The authors are with the Department of Electrical and Electronic Engineering,Hong Kong University of Science and Technology, Clear Water Bay, Kowloon,Hong Kong.

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