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November 2013

FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET

©2008 Fairchild Semiconductor Corporation 1 www.fairchildsemi.comFDS8958B Rev.C

Q1

Q2

Q1

Q2

Q1

Q2

Pin 1

SO-8

D1D1

D2D2

S2

S1G1

G2

S1

G1

S2

G2

D1

D1

D2

D2

1

2

3

4

8

7

6

5

FDS8958B Dual N & P-Channel PowerTrench® MOSFET Q1-N-Channel: 30 V, 6.4 A, 26 mΩ Q2-P-Channel: -30 V, -4.5 A, 51 mΩ

FeaturesQ1: N-Channel

Max rDS(on) = 26 mΩ at VGS = 10 V, ID = 6.4 A

Max rDS(on) = 39 mΩ at VGS = 4.5 V, ID = 5.2 A

Q2: P-Channel Max rDS(on) = 51 mΩ at VGS = -10 V, ID = -4.5 A

Max rDS(on) = 80 mΩ at VGS = -4.5 V, ID = -3.3 A

HBM ESD protection level > 3.5 kV (Note 3)

RoHS Compliant

General DescriptionThese dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor's advanced PowerTrench® process th at has been especially tailored to minimize on-state resistan ce and yet maintain superior switching performance.

These devices are well suite d for low voltage and battery powered applications where low in-line power loss and fast switching are required.

Application

DC-DC Conversion

BLU and motor drive inverter

MOSFET Maximum Ratings TC = 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 UnitsVDS Drain to Source Voltage 30 -30 VVGS Gate to Source Voltage ±20 ±25 V

IDDrain Current - Continuous TA = 25 °C 6.4 -4.5

A - Pulsed 30 -30

PD

Power Dissipation for Dual Operation 2.0WPower Dissipation for Single Operation TA = 25 °C (Note 1a) 1.6

TA = 25 °C (Note 1b) 0.9EAS Single Pulse Avalanche Energy (Note 4) 18 5 mJTJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C

RθJC Thermal Resistance, Junction to Case (Note 1) 40°C/W

RθJA Thermal Resistance, Junction to Ambient (Note 1a) 78

Device Marking Device Package Reel Size Tape Width QuantityFDS8958B FDS8958B SO-8 13 ” 12 mm 2500 units

FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET


Electrical Characteristics TJ = 25 °C unless otherwise noted

Off Characteristics

On Characteristics

Dynamic Characteristics

Switching Characteristics

Symbol Parameter Test Conditions Type Min Typ Max Units

BVDSS Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 VID = -250 µA, VGS = 0 V

Q1Q2

30-30 V

∆BVDSS ∆TJ

Breakdown Voltage TemperatureCoefficient

ID = 250 µA, referenced to 25 °CID = -250 µA, referenced to 25 °C

Q1Q2 24

-21 mV/°C

IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 VVDS = -24 V, VGS = 0 V

Q1Q2

1-1 µA

IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 VVGS = ±25 V, VDS = 0 V

Q1Q2 ±100

±10nAµA

VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 µAVGS = VDS, ID = -250 µA

Q1Q2

1.0-1.0

2.0-1.9

3.0-3.0 V

∆VGS(th) ∆TJ

Gate to Source Threshold VoltageTemperature Coefficient

ID = 250 µA, referenced to 25 °CID = -250 µA, referenced to 25 °C

Q1Q2

-65 mV/°C

rDS(on) Static Drain to Source On Resistance

VGS = 10 V, ID = 6.4 A VGS = 4.5 V, ID = 5.2 A VGS = 10 V, ID = 6.4A, TJ = 125 °C

Q1212931

263939

mΩVGS = -10 V, ID = -4.5 A VGS = -4.5 V, ID = -3.3 A VGS = -10 V, ID = -4.5 A, TJ = 125 °C

Q2386053

518072

gFS Forward Transconductance VDD = 5 V, ID = 6.4 AVDD = -5 V, ID = -4.5 A

Q1Q2

2010 S

Ciss Input Capacitance Q1VDS = 15 V, VGS = 0 V, f = 1 MHZ

Q2VDS = -15 V, VGS = 0 V, f = 1 MHZ

Q1Q2 405

570540760 pF

Coss Output Capacitance Q1Q2

75115

100155 pF

Crss Reverse Transfer Capacitance Q1Q2

55100

80150 pF

Rg Gate Resistance Q1Q2

2.44.4 Ω

td(on) Turn-On Delay Time Q1VDD = 15 V, ID = 6.4 A, VGS = 10 V, RGEN = 6 Ω

Q2VDD = -15 V, ID = -4.5 A, VGS = -10 V, RGEN = 6 Ω

Q1Q2 4.3

6.01012 ns

tr Rise Time Q1Q2 2.0

6.01012 ns

td(off) Turn-Off Delay Time Q1Q2 12

172230 ns

tf Fall Time Q1Q2 2.0

7.01014 ns

Qg(TOT) Total Gate Charge VGS = 10 VVGS = -10 V Q1

VDD = 15 V, ID = 6.4 A

Q2 VDD = -15 V, ID = -4.5 A

Q1Q2

8.314

1219 nC

Qg(TOT) Total Gate Charge VGS = 4.5 VVGS = -4.5 V

Q1Q2

4.17.0

5.89.6 nC

Qgs Gate to Source Charge Q1Q2 1.3

1.9 nC

Qgd Gate to Drain “Miller” Charge Q1Q2 1.7

3.6 nC

FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET


NOTES:1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design.

2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%.

3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.

4. UIL condition: Starting TJ = 25 °C, L = 1 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V . (Q1)

Starting TJ = 25 °C, L = 1 mH, IAS = -4 A, VDD = -27 V, VGS = -10 V. (Q2)

b) 135 °C/W when mounted on a minimun pad

a) 78 °C/W when mounted on a 1 in2 pad of 2 oz copper

Electrical Characteristics TJ = 25 °C unless otherwise noted

Drain-Source Diode Characteristics

Symbol Parameter Test Conditions Type Min Typ Max Units

VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2)VGS = 0 V, IS = -1.3 A (Note 2)

Q1Q2 0.8

-0.8 1.2-1.2 V

trr Reverse Recovery Time Q1IF = 6.4 A, di/dt = 100 A/µsQ2IF = -4.5 A, di/dt = 100 A/µs

Q1Q2

1720

3036 ns

Qrr Reverse Recovery Charge Q1Q2 6

81216 nC

FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET


Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted

Figure 1.

0 0.5 1.0 1.5 2.0 2.5 3.00

6

12

18

24

30

VGS = 4 V

VGS = 4.5 V

PULSE DURATION = 80 µsDUTY CYCLE = 0.5% MAX

VGS = 6 V

VGS = 3.5 V

VGS = 10 V

I D, D

RA

IN C

UR

REN

T (A

)

VDS, DRAIN TO SOURCE VOLTAGE (V)

On Region Characteristics Figure 2.

0 6 12 18 24 300.5

1.0

1.5

2.0

2.5

3.0

VGS = 4.5 V


NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

ID, DRAIN CURRENT (A)

VGS = 10 V

VGS = 6 V

VGS = 4 VVGS = 3.5 V

Normalized On-Resistance vs Drain Current and Gate Voltage

Figure 3. Normalized On Resistance

-75 -50 -25 0 25 50 75 100 125 1500.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

ID = 6.4 AVGS = 10 V

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (oC)

vs Junction TemperatureFigure 4.

2 4 6 8 1015

30

45

60

75

ID = 3.2 A

TJ = 25 oC

TJ = 125 oC

VGS, GATE TO SOURCE VOLTAGE (V)

r DS(

on),

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E (m

Ω) PULSE DURATION = 80 µs

DUTY CYCLE = 0.5% MAX

On-Resistance vs Gate to Source Voltage

Figure 5. Transfer Characteristics

1 2 3 4 5 60

5

10

15

20

25

30

VDS = 5 V


TJ = -55 oC

TJ = 25 oC

TJ = 125 oC

I D, D

RA

IN C

UR

REN

T (A

)

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 6.

0.2 0.4 0.6 0.8 1.0 1.2 1.40.01

0.1

1

10

30

TJ = -55 oC

TJ = 25 oC

TJ = 125 oC

VGS = 0 V

I S, R

EVER

SE D

RA

IN C

UR

REN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Source to Drain Diode Forward Voltage vs Source Current

FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET


Figure 7.

0 2 4 6 8 100

2

4

6

8

10

Qg, GATE CHARGE (nC)

V GS,

GA

TE T

O S

OU

RC

E VO

LTA

GE

(V)

ID = 6.4 A

VDD = 15 V

VDD = 10 V

VDD = 20 V

Gate Charge Characteristics Figure 8.

0.1 1 10 3010

100

1000

f = 1 MHzVGS = 0 V

CA

PAC

ITA

NC

E (p

F)

VDS, DRAIN TO SOURCE VOLTAGE (V)

Crss

Coss

Ciss

Capacitance vs Drain to Source Voltage

Figure 9.

0.001 0.01 0.1 1 10 1001

2

3

456789

TJ = 125 oC

TJ = 25 oC

tAV, TIME IN AVALANCHE (ms)

I AS,

AVA

LAN

CH

E C

UR

REN

T (A

)

1

Unclamped Inductive Switching Capability

Figure 10.

0.01 0.1 1 10 1000.01

0.1

1

10

100

1 s

0.1 ms

10 ms

DC10 s

100 ms

1 ms

I D, D

RA

IN C

UR

REN

T (A

)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS LIMITED BY rDS(on)

SINGLE PULSETJ = MAX RATEDRθJA = 135 oC/WTA = 25 oC

Forward Bias Safe Operating Area

Figure 11. Single Pulse Maximum Power Dissipation

10-4 10-3 10-2 10-1 1 10 100 10000.5

1

10

100

500

P (PK

), PEA

K T

RA

NSI

ENT

POW

ER (W

)

VGS = 10 V

SINGLE PULSERθJA = 135 oC/W

TA = 25 oC

t, PULSE WIDTH (sec)


FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET


Figure 12.

10-4 10-3 10-2 10-1 1 10 100 10000.001

0.01

0.1

12


DUTY CYCLE-DESCENDING ORDER

NO

RM

ALI

ZED

TH

ERM

AL

IMPE

DA

NC

E, Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5 0.2 0.1 0.05 0.02 0.01

PDM

t1t2

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJA x RθJA + TA

Junction-to-Ambient Transient Thermal Response Curve


FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET


Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted

Figure 15. On- Region Characteristics Figure 16. Normalized on-Resistance vs Drain Current and Gate Voltage

Figure 17. Normalized On-Resistance vs Junction Temperature

Figure 18. On-Resistance vs Gate to Source Voltage

Figure 19. Transfer Characteristics Figure 20. Source to Drain Diode Forward Voltage vs Source Current

0.0 0.5 1.0 1.5 2.0 2.5 3.00

6

12

18

24

30VGS = -10 V

VGS = -3.5 V

-VDS, DRAIN TO SOURCE VOLTAGE (V)

-I D, D

RA

IN C

UR

REN

T (A

)

VGS = -4.5 V


VGS = -4 V

VGS = -6 V

0 6 12 18 24 300.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5VGS = -3.5 V

VGS = -6 V

VGS = -4 V

PULSE DURATION = 80 µsDUTY CYCLE = 0.5%MAX

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

-ID, DRAIN CURRENT (A)

VGS = -10 V

VGS = -4.5 V

-75 -50 -25 0 25 50 75 100 125 1500.6

0.8

1.0

1.2

1.4

1.6

ID = -4.5 AVGS = -10 V

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (oC)2 4 6 8 10

0

40

80

120

160

200

TJ = 125 oC

ID = -2.3 A

TJ = 25 oC

-VGS, GATE TO SOURCE VOLTAGE (V)

r DS(

on),

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E (m

Ω) PULSE DURATION = 80 µs

DUTY CYCLE = 0.5% MAX

1 2 3 4 5 60

5

10

15

20

25

30

-VGS, GATE TO SOURCE VOLTAGE (V)

-I D, D

RA

IN C

UR

REN

T (A

)

TJ = 125 oC

VDS = -5 V


TJ = -55 oCTJ = 25 oC

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60.01

0.1

10

30

TJ = -55 oC

TJ = 25 oC

TJ = 125 oC

VGS = 0 V

-I S, R

EVER

SE D

RA

IN C

UR

REN

T (A

)

-VSD, BODY DIODE FORWARD VOLTAGE (V)

FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET



Figure 21. Gate Charge Characteristics Figure 22. Capacitance vs Drain to Source Voltage

Figure 23. Unclamped Inductive Switching Capability

Figure 24. Ig vs Vgs

Figure 25. Forward Bias Safe Operating Area

Figure 26. Single Pulse Maximum PowerDissipation

0 3 6 9 12 150

2

4

6

8

10

Qg, GATE CHARGE (nC)

-VG

S, G

ATE

TO

SO

UR

CE

VOLT

AG

E (V

)

ID = -4.5 A

VDD = -15 V

VDD = -20 V

VDD = -10 V

0.1 1 10 3030

100

1000

2000

f = 1 MHzVGS = 0 V

CA

PAC

ITA

NC

E (p

F)

-VDS, DRAIN TO SOURCE VOLTAGE (V)

Crss

Coss

Ciss

0.01 0.1 1 101

2

3

4

5678

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

-I AS,

AVA

LAN

CH

E C

UR

REN

T (A

)

0 5 10 15 20 25 30 3510-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

VGS = 0V

TJ = 25oC

TJ = 125oC

-VGS, GATE TO SOURCE VOLTAGE(V)

-I g,

GA

TE L

EAK

AG

E C

UR

REN

T(A

)

0.01 0.1 1 10 1000.01

0.1

1

10

100

1 s

0.1 ms

10 ms

DC10 s

100 ms

1 ms

-I D, D

RA

IN C

UR

REN

T (A

)

-VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS LIMITED BY rDS(on)

SINGLE PULSETJ = MAX RATEDRθJA = 135 oC/WTA = 25 oC

10-4 10-3 10-2 10-1 1 10 100 10000.5

1

10

100

200

SINGLE PULSERθJA = 135 oC/WTA = 25 oC

VGS = -10 V

P(PK

), PE

AK

TR

AN

SIEN

T PO

WER

(W)

t, PULSE WIDTH (sec)


Figure 27. Junction-to-Ambient Transient Thermal Response Curve

10-4 10-3 10-2 10-1 1 10 100 10000.002

0.01

0.1

1


DUTY CYCLE-DESCENDING ORDER

NO

RM

ALI

ZED

TH

ERM

AL

IMPE

DA

NC

E, Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5 0.2 0.1 0.05 0.02 0.01

2

PDM

t1t2

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJA x RθJA + TA

FDS8958B

Dual N

& P-C

hannel PowerTrench

® MO

SFET


© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FDS8958B • Rev. C 10

FD

S89

58

B —

Du

al N

& P

-Ch

an

nel P

ow

erT

ren

ch

® M

OS

FE

T

Physical Dimensions

Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150-inch Narrow Body

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/M0/M08A.pdf.

8°0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08Arev15

F) FAIRCHILD SEMICONDUCTOR.

LAND PATTERN RECOMMENDATION

SEATING PLANE

C

GAGE PLANE

x 45°

DETAIL ASCALE: 2:1

PIN ONE

INDICATOR

4

8

1

B5

A

5.60

0.65

1.75

1.27

6.00±0.203.90±0.10

4.90±0.10

1.27

0.42±0.09

0.175±0.75

1.75 MAX

0.36

(0.86)

R0.10

R0.10

0.65±0.25

(1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

0.25 C B A

0.10

0.22±0.30

(0.635)

http://www.fairchildsemi.com/dwg/M0/M08A.pdf

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FDS8958B • Rev. C 11

FD

S89

58

B —

Du

al N

& P

-Ch

an

nel P

ow

erT

ren

ch

® M

OS

FE

T

www.onsemi.com1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patentcoverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customerapplication by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classificationin a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. Thisliterature is subject to all applicable copyright laws and is not for resale in any manner.

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