pacificr5 - 64 channels sipm readout asic for the scifi tracker detector … · 2019. 4. 22. ·...

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PACIFICr5 - 64 channelsSiPM readout ASIC for theSciFi Tracker detector

Data Sheet PACIFICr5apqFEATURES64 channels.Current mode input.Low input impedance (≈50Ω).Zero components interface between sensor and device.High Bandwidth preamplifier (≈250MHz).Relative linearity error ±5%.Adjustable input node DC voltage.Low Power consumption (

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PACIFICr5apq Data SheetPACIFICr5apq Data SheetPACIFICr5apq Data SheetTABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . 1

TYPICAL APPLICATION CIRCUIT . . . . . . . . . . . . 1

APPLICATION . . . . . . . . . . . . . . . . . . . . . . . 1

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 1

REVISION HISTORY . . . . . . . . . . . . . . . . . . . 2

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . 3

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 4

PINS CONFIGURATION AND DESCRIPTION . . . . . . 5

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . 9DC INPUT VOLTAGE SELECTION . . . . . . . . . . . 9THRESHOLDS AND VrefDCFB . . . . . . . . . . . . 9

OFFSET and SLOPE adjustment . . . . . . . . . 9ANALOG DEBUG . . . . . . . . . . . . . . . . . . . . 9CALIBRATION ADC . . . . . . . . . . . . . . . . . . . 10CALIBRATION INPUT . . . . . . . . . . . . . . . . . 10CHARGE INJECTION . . . . . . . . . . . . . . . . . 10OFFSET COMPENSATION . . . . . . . . . . . . . . 11POWER ON RESET . . . . . . . . . . . . . . . . . . 11EXTERNAL INPUT . . . . . . . . . . . . . . . . . . . 11DIGITAL FEATURES & DEBUG . . . . . . . . . . . . 12

COMPARATOR BIAS CURRENT . . . . . . . . . . . . . 12

TRACK and HOLD BOTTOM PLATE . . . . . . . . . . 12

SERIALIZER . . . . . . . . . . . . . . . . . . . . . . . . 13

SLOW CONTROL INTERFACE . . . . . . . . . . . . . . 14CONFIGURATION REGISTERS . . . . . . . . . . . . 15

FLOORPLAN . . . . . . . . . . . . . . . . . . . . . . . 18POWER DISTRIBUTION . . . . . . . . . . . . . . . . 19ESD PROTECTION . . . . . . . . . . . . . . . . . . . 19ESD CAUTION . . . . . . . . . . . . . . . . . . . . . 19

APPLICATION INFORMATION . . . . . . . . . . . . . . 20ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . 20VISUAL INSPECTION . . . . . . . . . . . . . . . . . 20

TEST RESULTS . . . . . . . . . . . . . . . . . . . . . . 21START-UP . . . . . . . . . . . . . . . . . . . . . . . . 21DIGITAL SLOW CONTROL . . . . . . . . . . . . . . . 21ANODE VOLTAGE CONTROL . . . . . . . . . . . . . 22TEMPERATURE SENSOR . . . . . . . . . . . . . . . 22REFERENCE VOLTAGES and DACs . . . . . . . . . 23

OFFSET and SLOPE control . . . . . . . . . . . 25HIGH SPEED SERIALIZER . . . . . . . . . . . . . . 25THRESHOLDS SCAN . . . . . . . . . . . . . . . . . 26TRIMMING . . . . . . . . . . . . . . . . . . . . . . . 26INTERNAL ADC . . . . . . . . . . . . . . . . . . . . . 27PACKAGE MARKING . . . . . . . . . . . . . . . . . . 27SIPM TESTS . . . . . . . . . . . . . . . . . . . . . . 28

KNOWN ISSUES . . . . . . . . . . . . . . . . . . . . . 29

NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

REVISION HISTORY

03/17 - Albert Comerma - First version05/17 - Jose Mazorra - Updated registers and descritpiton08/17 - Albert Comerma - Updated BGA pinout, added testresults11/17 - Jose Mazorra - Added serializer section09/18 - Albert Comerma - Added pq version

rev. A | page 2 of 30

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Data Sheet PACIFICr5apqData Sheet PACIFICr5apqData Sheet PACIFICr5apq

FUNCTIONAL BLOCK DIAGRAM

The analog processing chain used for the Scintillating Fibre Tracker detector at LHCb has been split in different blocks to fit therequirements. The channel block diagram depicted in figure 2 includes:

• Pre-amplifier: it includes the current mode input stage already tested in the previous versions of the ASIC. It has a doublefeedback loop that sets the desired DC voltage at the input node and keeps at the same time a low input impedance overa broad bandwidth. The output structure has been modified to allow the selection over four different output gains. Thecurrent signal is then converted to voltage by means of a transimpedance amplifier (TIA). With respect to previous version,a filter has been added to avoid reaching the maximum slew rate of the TIA.

• Shaper: it has the function to reduce the peak duration of the signal to integrate as much signal as possible in the minimumtime. For that purpose, it reduces the tail produced by the sensor. It must be configurable to cope with the large differencein signal shape from the different manufacturer devices. From the previous version, the shaping time has been changed tofit last SiPM version.

• Integrator: it is formed by two interleaved gated integrators switching at half the system clock frequency (20MHz). Thisstructure allows to reduce the dead time almost to zero.

• Offset trim: a configurable block with trimming DACs allows to individually fine tune the DC voltage of each integrator (2per channel). It is based on a current DAC with some mirrors and pass gates to change in both directions (up and downfrom usual value).

• Track and Hold: two single ended track and hold circuits based on gated capacitors are used to mix the two signals andkeep the output stable between clock edges.

• Digitization: the conversion from analog to digital is based on three comparators with configurable thresholds. Thisscheme allows a non linear conversion adjusted to the desired operating conditions and range.

Figure 2: PACIFICr5 Channel block diagram

Some other blocks are also included to set the correct operation points of the circuit and configure tunable parameters. Thisblocks are a common biasing block controlled by a digital slow control block. This slow control is based on I2C standard. Atthe output of every four channels, an encoder and serialization block is also included. It generates a bit stream at 320MHz,encoding the three outputs of each channel comparators in two bits and concatenating the encoded output of the four channels.


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PACIFICr5apq Data SheetPACIFICr5apq Data SheetPACIFICr5apq Data Sheet

SPECIFICATIONS

TA=25◦C, VDDA = VDD = VDDD = VDDDIFFO = 1.2V , VDDIO = 1.5V

Parameter Conditions Min Typ Max UnitINPUT

Zin Default input stage polarization currents - 44 - ΩBandwidth 15pF input capacitance (min) and 5pF (max) 340 - 540 MHzDC adjustable at input 0.2 - 0.75 V

POWER CONSUMPTIONIV DD 1.2V - 190 - mAIV DDA 1.2V - 200 - mAIV DDD 1.2V - 100 - mAIV DDDIFFIO 1.2V - 60 - mAIV DDIO 1.5V - 1 - mA

DYNAMIC RANGEInput range Gain = 0 - pCInput range Gain = 1 - pCInput range Gain = 2 - pCInput range Gain = 3 - pC

REFERENCE VOLTAGEVREF Default values - 500 - mV

NOISE Integrated rms noise from 10Hz to 300MHz - - µADIGITAL SIGNALS

Clock frequency - 320 - MHzI2C Clock frequency(internal) - 40 - MHz

Table 1: Specifications summary


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PINS CONFIGURATION AND DESCRIPTION

PACIFICr5 is provided in two different formats: on die without packaging and packaged in a BGA format (12x12mm, 196pins, 0.8mm pitch). In figures 3 and 4 both formats can be seen with the corresponding pin numbers. Numbering is from left toright and from top to bottom, looking die or package from top.

Figure 3: Die pin configuration (Top view)

Figure 4: BGA package(Top view)

Several types of pins result from the pad ring. Most of them are analog input and digital output pairs. Additionally, somedigital inputs and outputs are used for controlling the slow control interface and debug functions. Finally, several power padsare also needed due to the different power domains and voltages (core and pad digital buffers).


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In tables 2, 3 and 4 a summary of the pinout is presented with its functionality. The correspondence between packaged(BGA) and die version is also included.

Table 2: Signals pinout

Die Pin BGA Pin Name Die Pin BGA Pin Name Die Pin BGA Pin Name1 C3 VREFOUT 2 D3 EXT 3 A1 CH04 A2 CH1 5 B1 CH2 6 B2 CH37 C1 CH4 8 C2 CH5 9 D1 CH610 D2 CH7 11 E1 CH8 12 E2 CH913 E3 CH10 14 F1 CH11 15 F2 CH1216 F3 CH13 17 G1 CH14 18 G2 CH1527 H1 CH16 28 H2 CH17 29 J1 CH1830 J2 CH19 31 K1 CH20 32 K2 CH2133 L1 CH22 34 L2 CH23 35 L3 CH2436 M1 CH25 37 M2 CH26 38 M3 CH2739 N1 CH28 40 N2 CH29 41 P1 CH3042 P2 CH31 129 A14 CH32 128 A13 CH33127 B14 CH34 126 B13 CH35 125 C14 CH36124 C13 CH37 123 D14 CH38 122 D13 CH39121 E14 CH40 120 E13 CH41 119 E12 CH42118 F14 CH43 117 F13 CH44 116 F12 CH45115 G14 CH46 114 G13 CH47 105 H14 CH48104 H13 CH49 103 J14 CH50 102 J13 CH51101 K14 CH52 100 K13 CH53 99 L14 CH5498 L13 CH55 97 L12 CH56 96 M14 CH5795 M13 CH58 94 M12 CH59 93 N14 CH6092 N13 CH61 91 P14 CH62 90 P13 CH63148 A8 SERM0 149 B8 SERP0 150 A7 SERM1151 B7 SERP1 152 A6 SERM2 153 B6 SERP2154 A5 SERM3 155 B5 SERP3 64 N5 SERM465 P5 SERP4 66 N6 SERM5 67 P6 SERP568 N7 SERM6 69 P7 SERP6 70 N8 SERM771 P8 SERP7 138 A12 SERM8 139 B12 SERP8140 A11 SERM9 141 B11 SERP9 142 A10 SERM10143 B10 SERP10 144 A9 SERM11 145 B9 SERP1174 N9 SERM12 75 P9 SERP12 76 N10 SERM1377 P10 SERP13 78 N11 SERM14 79 P11 SERP1480 N12 SERM15 81 P12 SERP15 21 G3 VrefDCFB22 H3 REF 23 J3 VbOTAfast 24 K3 VREF52 P3 CIN1 53 N3 CIN2 54 P4 ERROR155 N4 ERRORM 56 M4 ERR1GEN 57 M5 DISACLK58 M6 nRESET 59 M7 SYNC 60 M8 SDA61 M9 SCL 62 M10 LDINIT 63 M11 REFRESH110 J12 ADC_IN 111 H12 ADC_TEST_IN 156 C10 LED157 C9 SYNCPAT3 158 C8 SYNCPAT2 159 C7 SYNCPAT1160 C6 SYNCPAT0 166 A4 CLKM 167 A3 CLKP168 C5 DBG_TH 169 C4 DBG_SH 170 B4 DBG_PRE175 B3 CAL


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Die Pins BGA Pins Power supply name

26, 43, 88, 106, 131, 174E4, F4, G4, H4, J4, K4, D11,

VDDAD12, E11, F11, G11, G12, H11, J11, K11, K12, L11

25, 44, 89, 107, 130, 173 E6, F6, G6, H6, J6, K61 VSSA

20, 45, 86, 112, 133, 172E5, F5, G5, H5, J5, K5,

VDDE10, F10, G10, H10, J10, K10

19, 46, 87, 113, 132, 171 E7, F7, G7, H7, J7, K71 VSS

51, 82, 137, 161 D6, D7, D8, D9, D10, L6, L7, L8, L9, L10 VDDD

50, 83, 136, 162 E8, F8, G8, H8, J8, K81 VSSD

47, 48, 164, 165, D4, D5, L4, L5 VDDIO

49, 163 E9, F9, G9, H9, J9, K91 VSSIO

73, 85, 134, 146 C11, C12 VDDDIFFO

72, 84, 135, 1471 VSSDDIFFO

1081 VDDAD

1092 VSSAD1 VDDAD is connected to VDDA on BGA adapter.

2 All VSSA, VSS, VSSD, VSSAD, VSSIO and VSSDDIFFO are connected to a common VSS plane on BGA adapter.

Table 3: Power supply pins

Table 4: Pins function description

Pin name Bus length Type DescriptionCH[0:64] 64 Analog in SiPM anode connection for input signal. Directly to

channel input, no components are needed for connec-tion.

SERP[0:15], SERM[0:15] 32 SLVS out Digital output serialized at 320MHz using customdriver. It includes 2 bits from four consecutive channels(in total 8 bits encoding the output of the 3 discrimina-tors per channel).

VrefDCFB - Analog out Reference voltage for slow feedback loop amplifier, tobe decoupled with external capacitor.

VREFOUT - Analog out Voltge reference, after DAC and derived from BandgapReference. It should be 2*VREF.In version P this pin is pull-down to VSS.In version Q this pin is pull-up to VDDA.

VREF - Analog out Voltge reference used for common bias, after DAC andderived from Bandgap Reference. It should be setaround 0.5V.

VbOTAfast - Analog out Bias reference used for internal amplifiers, to be de-coupled with external capacitor.

REF - Analog out Voltage reference derived from voltage divider used inanode voltage control, to be decoupled with externalcapacitor.

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Table 4 – continued from previous pagePin name Bus length Type DescriptionDBG_PRE - Analog out Pre-amplifier analog debug signal (internally multi-

plexed).DBG_SH - Analog out Shaper analog debug signal (internally multiplexed).DBG_TH - Analog out Integrator (after T&H) analog debug signal (internally

multiplexed).CAL - Analog in Signal to inject an external current/waveform to any

channel (internally multiplexed).CIN1, CIN2 - Digital in Trigger for internal charge injection start. Active high.ADC_IN - Analog out Input signal comming into the ADC.ADC_TEST_IN - Analog in External input to the ADC.EXT - Analog in External input to the ADC.

In version P and Q this pin has a selectable 100µAcurrent source and x5 input gain, see external in-put section

nRESET - Digital in General digital reset. Active low.DISACLK - Digital in Disable of I2C clock (to avoid noise on analog). Active

low.SYNC - Digital in Reset for clock divider to generate integration clock

(20MHz) from main system clock (320MHz). Activehigh.

SDA - Digital in/out Slow control Data line.SCL - Digital in Slow control Clock line.LDINIT - Digital in Forces configuration registers to load the initial values

hardcoded in the slow control logic. Active low.REFRESH - Digital in Refresh from error flags. Active low.ERR1GEN - Digital in Pin to force error on digital memory (for debugging pur-

poses). Active low.SYNPAT[3:0] 2 Digital in External injection of data to the serial links. The data

is directly feed to the serializer when internal synModesignal is enabled.

ERROR1 - Digital out Indicator for single bit fips detected by the Hammingcode in the configuration registers. Active high.

ERRORM - Digital out Indicator for multiple bit fips detected by the Hammingcode in the configuration registers. Active high.

LED - Digital out Bit controlled by internal register.CLKM, CLKP - SLVS in Differential input of main clock (320MHz).VDDA, VSSA - Power Pre-amplifier, shaper and common bias power supply.

1.2V.VDD, VSS - Power Integrator, Trimming, Track and Hold and analog

buffers power supply. 1.2V.VDDD, VSSD - Power Standard cells digital power supply. 1.2V.VDDDIFFO, VSSDIFFO - Power SLVS output buffers power supply. 1.2V.VDDIO, VSSIO - Power Digital PAD ring IO voltage. 1.5V.VDDAD, VSSAD - Power Integrated ADC power supply. 1.2V.

Table 4: Pins function description


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FEATURES

Several features and blocks have been added to the designin order to cope with the different input signals and to allow aneasier testing and debugging of the different features.

In order to debug the different analog blocks of the pro-cessing chain, several features and extra pins have beenadded. On the digital side, also a few operation modes andextra pins have been added to perform different checks.

DC INPUT VOLTAGE SELECTION

Even if high overvoltage operated SiPM array does notshow an important dispersion of gain from channel to chan-nel, the anode voltage can be fine tuned using the configura-tion registers of PACIFIC. To avoid voltage dispersion betweenchannels and to reduce lines and power consumption, a sin-gle common reference (with 16 values) is shared for all chan-nels. The voltage is derived from the Bandgap reference volt-age (multiplied a factor 2) and then divided by equal resistors(see figure 5), giving around 50mV steps.

Figure 5: Anode voltage generation

Each channel can be independently connected to any ofthese references using the variable D_OFF_MUX_* (4 bits)from the channel configuration registers. The four digital sig-nals are delivered to the channel, where a decoder generatesthe corresponding enable signal to the 16 pass gates that im-plement the connection.

THRESHOLDS AND VrefDCFB

VrefDCFB is a voltage reference used in all the analog pro-cessing chain to keep a constant DC value at the output of thedifferent blocks. For this reason the resulting thresholds mustbe evaluated with respect to this voltage. Since the gated inte-grator uses an inverting structure the output signal should besmaller than this voltage.

The threshold generation has been completely modifiedfrom the previous version. The thresholds are generated in-dependently of VrefDCFB by injecting the output of the currentDACs into a ≈50k Ω resistor. The granularity of the currentDACs has been increased to 8 bits, providing a voltage rangebetween ground and 760mV. As a consequence, VrefDCFBcannot be set to values above 700mV without affecting the op-eration of the circuit.

In this version, the threshold generation structure has beeninstantiated only once in the common biasing block, instead ofthree. Additionally, a copy of this structure has been placed inevery channel, allowing to define specific thresholds for eachchannel. The flag D_SELVTH_* from the channel configura-tion register controls the selection between the common andlocal thresholds at a channel level.

OFFSET and SLOPE adjustment

Common and Local thresholds DACs have and adjustableslope and offset. This feature is applied to all the thresholdDACs at the same time and permits to adjust the DACs rangeto the region of interest depending on offset and precision re-quired.

In figure 6 a view of the circuit operation can be observed.It is based on three four bit DACs that are used on one side toadd a fixed amount of current just before the resistor convert-ing it to voltage (adding offset) and in an independent circuitfor adding or removing current to the eight bit DACs mastercurrent reference (changing the slope).

The sign which controls if the slope addition is positive ornegative is controlled by the THOFFen bit, while the rest ofSlope adjustment is controlled by the four LSBs of the THOFFregister, the rest four MSBs are used to control the offsetadded to the DACs.

Figure 6: Slope and offset control of threshold DACs

ANALOG DEBUG

The analog signal from the critical points of the process-ing chain are available through the DBG_PRE, DBG_SH andDBG_TH pins (as seen in figure 2). The flag DBG_EN_OUTfrom the debug configuration registers must be set to en-able this analog readout. Alternatively, when the flagDBG_EN_OUT is not set these output give access to the chan-nel local thresholds.

In order to avoid using a large amount of pads, this out-puts are multiplexed in a single output for the whole 64 chan-nels. The channel connected to this debug output is controlled


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by the variable DBG_MUX (5 bits) from the debug configura-tion registers, accessible through the slow control interface.The debug features require an additional decoder, included inthe slow interface logic.

The output can be connected directly to a high inputimpedance test probe (1MΩ). The output buffers do not fea-ture enough slew rate to drive directly low impedance (50Ω).If needed, external amplifier can be used for this purpose(OPA692 is recommended).

CALIBRATION ADC

In order to simplify the characterization of the differentDACs in the ASIC, a 10 bit ADC has been integrated in thechip. It operates with a 6.67MHz clock generated by the slowcontrol logic. It also uses an specific 1.2V power supply, inde-pendent from the power supplies of the rest of the chip.

The input to the ADC is multiplexed, selecting the de-sired signal by setting the corresponding value in the variableDBG_ADC_ADDR (4 bits) of the debug configuration registers:

• (0:2): Common threshold voltages.• (3:5): Local channel threshold voltages, where the chan-

nel is selected with the the variable DBG_MUX (5 bits)from the debug configuration registers.

• (6): Common bias voltage reference VREF.• (7): Bandgap voltage.• (8): Temperature sensor output voltage.• (9): Channel voltage reference VrefDCFB.• (10:13): Several steps of the input voltage selection circuit

REF[15,12,9,6].

• (14): External input EXT.• (15): External input ADC_TEST_IN.

The selected input signal of the ADC can be readout throughthe dedicated pin ADC_IN after being buffered.

An extra 1V reference output derived from VREF can beused for powering external circuits and is available at VRE-FOUT pin.

The conversion process is triggered by setting theflag DBG_ADC_START from the debug configuration reg-isters. When the conversion is completed, the slow con-trol logic stores the result in the lower bits of the variableDBG_ADC_Out (16 bit). The rest of the bits are fixed at ’0’except the MSB, which is used to indicate the completion ofthe conversion (EOC).

CALIBRATION INPUT

A single calibration input allows to inject electrical signal tothe desired channel for characterization. This calibration input(see figure 7) consists on a pass gate followed by a ≈100 Ω

resistor (to convert external voltage signal to current) in seriesto the input. The connection is in parallel to the sensor in-put to avoid affecting this signal. This feature can be enabledby setting the flag DBG_EN_IN from the debug configurationsregisters. Additionally, the flag DBG_Cin must be not set toselect this charge injection option instead of the internal injec-tion system presented in the next section. The pass gate ofeach channel can be independently selected by using the vari-able DBG_CH from the debug configuration registers. Basedon these three configuration variables, a decoder placed in theslow control logic generates the signal CALCH that appears infigure 8.

Figure 7: Calibration input

CHARGE INJECTION

Similar to the calibration input, a charge injection structurehas been inserted in the channel for characterization.

This structure charges two small on channel capacitors,while CIN1 and CIN2 are in the ’0’ state, and discharges themto the input stage when a rising edge arrives. To fully dis-charge the signal they must be kept during at least 4*RC time.Depending on CIN1 and CIN2 control, three different values ofcharge can be injected.

To avoid interfering with the normal input signal, this featurecan be enabled by setting the flag DBG_EN_IN from the debugconfigurations registers. Additionally, the flag DBG_Cin mustbe set to select this charge injection option instead of the ex-ternal calibration input presented in the previous section. Thepass gate of each channel can be independently selected byusing the variable DBG_CH from the debug configuration reg-isters. Based on these three configuration variables, a decoderplaced in the slow control logic generates the signal CINCHthat appears in figure 8. The slow control logic ensures thatCINCH and CALCH never collide.

Simulation with relatively small capacitors (630fF and 1pF)and relatively large resistor in series (12 kΩ and 9 kΩ respec-tively) to mimic SiPM tail shows a reasonable output.

Using the slow control, any combination of channels canbe selected to use this charge injection, what should allow a


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Figure 8: Charge injection and calibration schematics

much faster but less fine characterization of the whole proto-type, compared to the calibration input.

OFFSET COMPENSATION

MonteCarlo simulations with the full channel presents aproblem in the offset level at the output of the integrators. Firstproblem is the channel to channel variation and a second oneis the intra-channel (integrator to integrator) variation. Accord-ing to simulations, few of the channels are expected to have avariation higher than 1/4phe leading to problematic setting ofthe thresholds for measurements.

The closed loop DC correction mechanism, which automat-ically corrected the channel to channel variations, has beendeprecated. On the other hand, the sub-channel offset trim-ming has been moved to the positive input of the integrator,where VrefDCFB was previously set. The trimming is based ona current output DAC and some mirrors that can feed current inboth direction, leading to positive or negative movement of thereference voltage of the integrator. In figure 9 the schematic ofthe block can be observed. The control lines are reduced to 4bits for the current setting and 1 bit of sign.

Figure 9: Sub-channel DC level trimming

With this configuration, the channel to channel dispersion ofthe offset level can be corrected using the offset trimming, byshifting the baseline of both integrators in parallel, or by adjust-

ing the channel specific threshold to compensate this spread.The intra-channel variation can still be corrected with the offsettrimming as in previous versions.

POWER ON RESET

Previous prototype revealed a random startup of registersvalue after power is applied, leading to some high current con-sumption during the time between powering and generatingcorrect initialization sequence via control signals. To avoid thiscondition a Power On Reset (POR) circuit has been added.The function of this circuit is to generate a clean startup pulseto set all registers to the default value.

This block has been connected to the digital power supply(VDDD) since it will interact with the slow control registres. Aschematic of the POR circuit can be seen in figure 10.

Figure 10: Power on Reset circuit

Since rising time of power supply is not predictable andshould take some µs, an initial block generates a controlledslope of the power supply. This signal is introduced to an in-verter and then delayed using several inverters. The output ofthe first inverter is fed into an XOR together with the delayedoutput, generating a short digital pulse.

EXTERNAL INPUT

On PACIFICr5a the EXT pin is directly connected to theADC channel, while in PACIFICr5p/q it has some extra fea-tures.

Since this pin is expected to be used for external tempera-ture monitoring a constant current can be enabled at this out-put (around 100µA). At the same time an internal buffer witha gain of 5 can be selected before driving the ADC. The be-haviour of this current source and amplifier gain is controlledby the two uppermost bits of register 10 (Vref) as summarizedin table 5.

This configuration permits to use a single pin for externaltemperature resistor monitoring and the resulting VrefOUT pinis free now and being used to distinguish between version Pand Q (pull-down or pull-up respectively).


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DIGITAL FEATURES & DEBUG

On the digital side, three different check structures havebeen added;

• Hamming encoding: All the registered memory bits thathold the configuration are checked by a Hamming encod-ing algorithm. The registers have a length of 8 bits and arecomposed of two equal blocks. Each block implements aHamming(7,4) code with an additionally parity bit, requir-ing 4 parity bits to protect 4 data bits. In this way, if an er-ror occurs (due to Single Event Upset) it can be detected,discriminating whether a single bit or several bits flipped,and corrected on the fly in the case of a single bit flip.

To signal the errors two signals are generated;–ERROR1: Indicates a single error in the register.–ERRORM: Indicates multiple errors.

Once a single error is detected, a low level in the RE-FRESH signal is needed to clear the error signal. Inter-nally, the signal is corrected by the logic inside the registerblocks. In case of multiple errors, the configuration regis-ters must be rewritten to correct the error and clear theerror signal. Internally, ERROR counters are present tocount the number of errors, one 8 bits counter for singleerrors (one bit) and a second 8 bits counter for the multipleerrors. The counter is driven by the state of the error sig-nals of all the registers, being automatically written whenany of these signals changes its state. Consequently, thesingle error counter is cleared by the REFRESH signaland the multiple error counter is cleared when the regis-ters are rewritten.

ERROR1GEN signal is designed to test the functionalityof the Hamming encoding error detection and correction,by setting the LSB of all register blocks and forcing singleerrors in the memory.

• SYNCPAT: an external digital pattern can be introducedin the serializer block to test the serialization and digitallink. This pattern can be generated externally at 40MHzand used in all the channels. This test mode and the cor-responding inputs are selected with the flag synMode inthe debug configuration registers.

In PACIFICr5a the order in which the SYNCPAT is in-jected is thus a change ofhalf a clock period can not be observed, for this rea-son in PACIFICr5p/q the order has been changed to.

• LED: there is a flag in the debug configuration register re-served to control a digital output that should be connectedto a LED on the PCB to allow the verification of the slowcontrol.

COMPARATOR BIAS CURRENT

Since in PACIFICr5a the speed of the hysteresis compara-tors can be close to the 25ns time between bunches the possi-bility to increase this current has been added in PACIFICr5p/q.To avoid adding extra control bits this feature is controlled byregister 9 (Ifbk) two uppermost bits and permit to multiply bythree the bias current if both are enabled (set to "1"). Careshould be taken since a non negligible total current consump-tion will be added in the order of 20mA.

TRACK and HOLD BOTTOM PLATE

In PACIFICr5a the bottom plate of the Track and Hold ca-pacitors is directly connected to the ground line. Then theinput/output signals are directly controlled with the clock withnegate/interleaved behaviour among the two integrators inputand single output.

This arrangement resulted in some spillover measured atthe test-beam campaigns (of around 25% in analog signal)that lead to high possibility of detecting a cluster in the bunchcrossing after the signal (around 60%).

For this reason a different connection has been used inPACIFICr5q to reduce the analog signal injected in the nextperiod. This connection relies on the generation of severalfast signals from the main clock. The new generated signalsclk1 and clk2 will drive the integrators instead of clk and its in-verted. In figure 11 the standard logic cells used to generatethe different clock phases and the capacitors connection canbe observed.

Figure 11: Bottom plate connection and clock generation


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SERIALIZER

The serializer takes the output of four channels in parallel every 25ns and sends them through a serial link at a rate of320Mbps. I receives a single 320MHz clock and produces the 40MHz clock used to sample the comparators, as well as thetwo complementary 20MHz clocks distributed to the channels to manage the switches in the gated integrators. The output ofthe three comparators of each channel is registered on the rising edge of the 40MHz. Then, the three bits of each channelare arithmetically added, generating the two bit format of the channel data. The data from all four channels is latched withthe rising edge of the 40MHz onto a single register(dField), placing at the lowest place the LSB of the lower channel and atthe highest the MSB of the higher channel (dField[7:0]=[CH3(1),CH3(0),CH2(1),CH2(0),CH1(1),CH1(0),CH0(1),CH0(0)]). Afterpassing through a shift register, the bits are sequentially output, starting by MSB of the 8bit register and latching the output onthe rising edge of the 320MHz clock.

Figure 12: Normal operation serializer timeline

When the synMode flag is active(’1’), the serializer takes the input data from a group of four pads: SYNPAT(SP). Since therewere only four available pads, the pattern is concatenated with itself to produce an eight bit word. This also means that the datais considered to be already in a two bit format, so it is latched directly in the eight bit register assembling the data from all thechannels in the normal operation (dField[7:0]=[SP(3),SP(2),SP(1),SP(0),SP(3),SP(2),SP(1),SP(0)]).

Figure 13: External pattern serializer timeline

The serializer receives one additional signal: SYNC. This signal, active low(’0’), resets the state machine inside the clockgenerator. When active, it sets the 40MHz clock and one of the 20MHz clocks to a high value, correspondingly setting the other20MHz clock to a low value. When released, the state machine starts to run, making the SYNC signal in phase with the risingedge of the 40MHz clocks, although no rising edge is apparent in the first cycle. The SYNC acts as a a synchronous reset,evaluated on the rising edge of the incoming clock, assuring that all the cocks are synchronized with the master 320MHz clock.

The serializer is protected with triple modular redundancy, applied both to the clock generator and to the logic performing theconversion from a parallel to a serial stream. However, the two complementary 20MHz clocks controlling the integration of thechannels are not covered. The SYNC signal, before reaching the clock generator, is not protected as well.


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SLOW CONTROL INTERFACE

Slow control is based on standard 10bit addressing I2C. The basic write transmission frame can be observed in figure 14.Auto-increment of address is performed internally to allow more than one consecutive register read or write without repeatingthe preamble (first 2 bytes).

Figure 14: Write example sequence

In the case of a read operation a repeated start must be provided after first byte transmission to start the read process, asseen in figure 15. It introduces the need of an extra byte in the preamble. During read data the nACK must be provided bymaster.

Figure 15: Read example sequence


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CONFIGURATION REGISTERS

Several configuration registers are available for settling different parameters. Configuration words are divided in commonparameters (see table 5), channel parameters (see table 7) and debug parameters (see table 6). Common parameters anddebug parameters are shared among all the 64 channels while channel parameters are different for every channel. A total of2700 control bits are needed, with 339 logical registers. The registers are logically organized in groups of 8 bits.

Signal Name bits Function Length Default* Hex Dec Value UnitVth1 7:0 First comparator lower threshold 8 00101101 2D 45 0.66 VVth2 7:0 Second comparator lower threshold 8 00111010 3A 58 0.62 VVth3 7:0 Third comparator lower threshold 8 01010100 54 84 0.543 VVrefDCFB 5:0 Shaper DC feedback voltage control 6 000111 07 7 0.72 VBLHen 6 Baseline restorarion enable signal 1 1 1 1 ONTHOFFen 7 ThDAC adjustment enable signal 1 1 1 1 OFFTHOFF 7:0 ThDAC offset and slope adjustment 8 11111111 FF 255 0 µAIDCFB 5:0 Shaper DC feedback current control 6 110101 35 53 55 µAISHGRAL 7:0 Shaper reference current 8 11001000 C8 200 250 nAIbias 5:0 Input stage bias current 6 011101 1D 29 51 µAGain 7:6 Input stage gain control 2 10 2 2 1.5 -Ifbk 5:0 Input stage feedback bias current 6 011101 1D 29 46 µAIbComp (p/q only) 7:6 Comparators extra bias 2 0 0 0 OFFVref 5:0 Bandgap fine tunning voltage 6 011111 1F 31 0.5 VItemp (p/q only) 6 EXT pin 100µA current source enable 1 0 0 0 OFFExtGain5 (p/q only) 7 External voltage input gain x5 enable 1 0 0 0 OFFIrefTRIM 5:0 Integrator trimming DAC ref. current 6 100011 23 35 50 µAIrefOTALP 3:0 Correction OTA bias current 4 1010 A 10 50 µAItxslvs 4 Differential output extra current 1 0 0 0 OFFPZConf: Pole zero timing configuration

LowAtLad_PZ1 5 Pole zero 1 low attenuation 1 1 1 1 ONIbofHam 6 Offset current added 1 0 0 0 OFF

00101010 3A 42Rlad_PZ1 2:0 Pole zero 1 Resistor 3 001 1 1 9.2 kΩCap_PZ1 6:3 Pole zero 1 Capacitance Coarse 4 0111 7 7 790 fFCapF_PZ1 7 Pole zero 1 Capacitance Fine 1 0 0 0 OFF 1.8pF

00111001 39 57Rlad_PZ2 2:0 Pole zero 2 Resistor 3 110 6 6 1.9 kΩCap_PZ2 6:3 Pole zero 2 Capacitance 4 0101 5 5 560 fFCapF_PZ2 7 Pole zero 2 Capacitance Extra 1 0 0 0 OFF 1.8pF

00101110 2E 46*Bits order is MSB to LSB

Table 5: Common control register summary

Signal Name bits Function Length Default(MSB to LSB) ValueDBG_CH 63:0 Debug input channel selector 64 0x0000000000000000 OFFDBG_MUX 5:0 Debug analog output channel selector 6 000000 OFFDBG_EN_OUT 6 Debug output signal selector 1 0 VTHsynMode 7 Enable serializer external input 1 0 OFFDBG_EN_IN 0 Debug input enable signal 1 0 OFFDBG_Cin 1 Charge injection system selector 1 0 CALDBG_ADC_ADDR 5:2 ADC input signal selector 4 0000 VTH0DBG_ADC_START 6 ADC conversion trigger 1 0 OFFaLED 7 Debug LED 1 0 OFF

Table 6: Debug control register summary


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Table 7: Eight channel block control registers summary

Signal Name bits Function Length Default* Hex Dec Value UnitD_OFF_MUX_0 3:0 CH0 input offset voltage 4 1000 8 8 0.6 VD_OFF_MUX_1 7:4 CH1 input offset voltage 4 1000 8 8 0.6 VD_OFF_MUX_2 3:0 CH2 input offset voltage 4 1000 8 8 0.6 VD_OFF_MUX_3 7:4 CH3 input offset voltage 4 1000 8 8 0.6 VD_OFF_MUX_4 3:0 CH4 input offset voltage 4 1000 8 8 0.6 VD_OFF_MUX_5 7:4 CH5 input offset voltage 4 1000 8 8 0.6 VD_OFF_MUX_6 3:0 CH6 input offset voltage 4 1000 8 8 0.6 VD_OFF_MUX_7 7:4 CH7 input offset voltage 4 1000 8 8 0.6 VD_TRIM_TDAC_0 3:0 CH0 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_0 7:4 CH0 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TDAC_1 3:0 CH1 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_1 7:4 CH1 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TDAC_2 3:0 CH2 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_2 7:4 CH2 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TDAC_3 3:0 CH3 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_3 7:4 CH3 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TSIGN_0 0 CH0 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_0 1 CH0 Bottom trimming sign 1 1 1 1 DOWND_TRIM_TSIGN_1 2 CH1 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_1 3 CH1 Bottom trimming sign 1 1 1 1 DOWND_TRIM_TSIGN_2 4 CH2 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_2 5 CH2 Bottom trimming sign 1 1 1 1 DOWND_TRIM_TSIGN_3 6 CH3 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_3 7 CH3 Bottom trimming sign 1 1 1 1 DOWND_TRIM_TDAC_4 3:0 CH4 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_4 7:4 CH4 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TDAC_5 3:0 CH5 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_5 7:4 CH5 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TDAC_6 3:0 CH6 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_6 7:4 CH6 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TDAC_7 3:0 CH7 Top Offset trimming 4 1111 F 15 0 µAD_TRIM_BDAC_7 7:4 CH7 Bottom Offset trimming 4 1111 F 15 0 µAD_TRIM_TSIGN_4 0 CH4 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_4 1 CH4 Bottom trimming sign 1 1 1 1 DOWND_TRIM_TSIGN_5 2 CH5 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_5 3 CH5 Bottom trimming sign 1 1 1 1 DOWND_TRIM_TSIGN_6 4 CH6 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_6 5 CH6 Bottom trimming sign 1 1 1 1 DOWND_TRIM_TSIGN_7 6 CH7 Top trimming sign 1 1 1 1 DOWND_TRIM_BSIGN_7 7 CH7 Bottom trimming sign 1 1 1 1 DOWND_Vth1_0 7:0 CH0 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_0 7:0 CH0 middle threshold local value 8 11111111 FF 255 0 VD_Vth3_0 7:0 CH0 higher threshold local value 8 11111111 FF 255 0 VD_Vth1_1 7:0 CH1 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_1 7:0 CH1 middle threshold local value 8 11111111 FF 255 0 VD_Vth3_1 7:0 CH1 higher threshold local value 8 11111111 FF 255 0 VD_Vth1_2 7:0 CH2 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_2 7:0 CH2 middle threshold local value 8 11111111 FF 255 0 V*Bits order is MSB to LSB

– continued on next page


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Table 7 – continued from previous pageSignal Name bits Function Length Default* Hex Dec Value UnitD_Vth3_2 7:0 CH2 higher threshold local value 8 11111111 FF 255 0 VD_Vth1_3 7:0 CH3 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_3 7:0 CH3 middle threshold local value 8 11111111 FF 255 0 VD_Vth3_3 7:0 CH3 higher threshold local value 8 11111111 FF 255 0 VD_Vth1_4 7:0 CH4 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_4 7:0 CH4 middle threshold local value 8 11111111 FF 255 0 VD_Vth3_4 7:0 CH4 higher threshold local value 8 11111111 FF 255 0 VD_Vth1_5 7:0 CH5 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_5 7:0 CH5 middle threshold local value 8 11111111 FF 255 0 VD_Vth3_5 7:0 CH5 higher threshold local value 8 11111111 FF 255 0 VD_Vth1_6 7:0 CH6 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_6 7:0 CH6 middle threshold local value 8 11111111 FF 255 0 VD_Vth3_6 7:0 CH6 higher threshold local value 8 11111111 FF 255 0 VD_Vth1_7 7:0 CH7 lower threshold local value 8 11111111 FF 255 0 VD_Vth2_7 7:0 CH7 middle threshold local value 8 11111111 FF 255 0 VD_Vth3_7 7:0 CH7 higher threshold local value 8 11111111 FF 255 0 VD_SELVTH_0 0 CH0 threshold selection 1 0 0 0 COMD_SELVTH_1 1 CH1 threshold selection 1 0 0 0 COMD_SELVTH_2 2 CH2 threshold selection 1 0 0 0 COMD_SELVTH_3 3 CH3 threshold selection 1 0 0 0 COMD_SELVTH_4 4 CH4 threshold selection 1 0 0 0 COMD_SELVTH_5 5 CH5 threshold selection 1 0 0 0 COMD_SELVTH_6 6 CH6 threshold selection 1 0 0 0 COMD_SELVTH_7 7 CH7 threshold selection 1 0 0 0 COM*Bits order is MSB to LSB

Table 7: Eight channel block control registers summary

Table 8 summarizes the address of the registers, with length and contents. Their contents map directly to control signals intables 7, 6 and 5. LED output is directly driven by the corresponding bit in register.

Name Function Bits used (total) Address RangeCommon Register Controls for common bias block 103 (112) x001h-x00EhChannels 0-7 Register Controls channel specific features 312 (312) x00Fh-x035hChannels 8-15 Register Controls channel specific features 312 (312) x036h-x05ChChannels 16-23 Register Controls channel specific features 312 (312) x05Dh-x083hChannels 24-31 Register Controls channel specific features 312 (312) x084h-x0AAhChannels 32-39 Register Controls channel specific features 312 (312) x0ABh-x0D1hChannels 40-47 Register Controls channel specific features 312 (312) x0D2h-x0F8hChannels 48-55 Register Controls channel specific features 312 (312) x0F9h-x11FhChannels 56-63 Register Controls channel specific features 312 (312) x120h-x146hDebug Register Controls for debug functions 80 (80) x147h-x150hADC Register* ADC output registers 16 (16) x151h-x152hError Register* Counters for Hamming detected errors 16 (16) x153h-x154h*Read only registers.

Table 8: Registers addresses summary


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FLOORPLAN

A total size of 15.4mm2 (4000µm x 3850µm) has been needed to include the described functionality. PACIFICr5 is dividedinto four identical 16 channel blocks, each one placed in one corner of the die. The common biasing generation structure wasplaced between the two left blocks and the ADC between the right ones. The slow control logic and configuration registersare located between the left and right blocks. Some of the signals are common to all the blocks (channels debugging controlbasically) while others are in separated registers (common analog references and voltages setup). In figure 16 the top layoutcan be observed with both sides highlighted.

Figure 16: PACIFICr5 Die of 4000µm x 3850µm with blocks


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POWER DISTRIBUTION

Different power domains are present in the design. The dif-ferent VSS connections are separated logically during designbut are all connected to the same substrate. On the powersupply, different power rails are used until the PCB level (therecould be joined to the same power supply). This allows forexternal filtering if needed, avoiding any noise transmissionbetween power supplies. Several redundant power pad’s (seefigure 17) have been placed in the design to reduce the para-sitic inductance and voltage drop.

Figure 17: PACIFICr5 Power Pads placement

Different power pairs on figure 17 are from the differentpower domains present on PACIFICr5;

• A - VDDA/VSSA Analog power PAD pairs

• S - VDD/VSS Switched power PAD pairs

• D - VDDD/VSSD Digital power PAD pairs

• IO - VDDIO/VSSIO Digital in/out buffers power PAD pairs

• Df - VDDDIFFO/VSSDIFFO Digital differential out bufferspower PAD pairs

• AD - VDDAD/VSSAD ADC power PAD pairs

ESD PROTECTION

TSMC recommendations lead to the inclusion of thePCLAMPA cells to avoid any damage on all the power supplyconnections from the device, except of the digital in/out bufferspower PAD pairs VDDIO/VSSIO. In figure 18 the placement ofthe cells is depicted (highlighted in orange boxes).

Figure 18: PACIFICr5 clamp cells

ESD CAUTIONESD (electrostatic discharge) sensitivedevice. Charged devices and circuitboards can discharge without detection.Although this product features patentedor proprietary protection circuitry, damagemay occur on devices subjected to high en-ergy ESD. Therefore, proper ESD precau-tions should be taken to avoid performancedegradation or loss of functionality.


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APPLICATION INFORMATION

For normal operation of the device some boundary condi-tions must be ensured.

ABSOLUTE MAXIMUM RATINGS

Parameter RatingVDDA,VDD,VDDD,VDDADC ,VDDDIFFIO 1.2 VVDDIO 1.5 VTemperature Range

Operatingjunction -40 to 125◦CStorage -65 to 150◦C

Soldering Conditions TBD

Stresses above those listed under Absolute Maximum Rat-ings may cause permanent damage to the device. This is astress rating only; functional operation of the device at theseor any other conditions above those indicated in the opera-tional section of this specification is not implied. Exposure toabsolute maximum rating conditions for extended periods mayaffect device reliability.

VISUAL INSPECTION

After reception of the prototypes a first visual inspection isperformed on a microscope. In figure 21 and 19 a general andzommed view of the devices can be observed. Top metal (Al)is clearly visible (green) with the power distribution rails.

Figure 19: PACIFICr5 logos zoom

Figure 20: PACIFICr5q logos zoom

The same picture of PACIFICr5p/q show an increase in thetop metal power distribution lines to reduce the voltage dropsinside the ASIC and the corresponding version numbers, asseen in figures 22, 23 and 20.

Figure 21: PACIFICr5 Die

Figure 22: PACIFICr5q Die

Figure 23: PACIFICr5p logos zoom


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TEST RESULTS

As in previous prototypes, test system is based on a digitalprinted circuit board to generate all the needed signals for theASIC (clock, reset and slow control) and control it over a USBconnection. A second analog PCB with the device directly wirebonded and all the needed analog power supply and analogdebugging circuitry is placed over the first one with two matingconnectors (see figure 24).

Figure 24: PACIFICr5 test system

External instruments such as an Arbitrary Waveform Gen-erator, digitally controlled attenuator, oscilloscope and powersupplies have also been used during the test.

For PACIFICr5p/q test a similar updated analog board hasbeen used and the same digital board.

START-UP

Since a Power On Reset (POR) circutry has been added inthis prototype there is no need to apply any sequence to start-up correctly the control registers. Once the device it’s pow-ered it will automatically load the default values to all the regis-ters. In table 9 a summary of the first prototypes (wire bonded)tested startup values on accessible nodes is summarized andcompared with simulation. Note the usual higher values in alltested devices.

For PACIFICr5p/q the initial startup voltage has been re-duced by design to provide a soft start of the electronics. Theeffect can be clearly seen in the first prototypes test (see table10).

DUT VREF V refDCFB V OTAfast REF VREFOUT

Sim 500 720 865 893 1000wb01 577 793 819 1016 1136wb02 565 787 826 994 1104wb03 584 790 817 1015 1141wb04 549 778 826 950 1091

Table 9: Start-up values for PACIFICr5a

DUT VREF V refDCFB V OTAfast REF

Sim 480 720 865 893p-wb01 468 670 890 666p-wb02 451 655 882 644p-wb03 480 698 871 687q-wb01 470 686 874 665q-wb02 476 691 874 681q-wb03 480 678 878 678

Table 10: Start-up values for PACIFICr5p/q

DIGITAL SLOW CONTROL

Slow control is based on a standard 10-bit addressing I2C. Dueto the need of more than 8 bits for the address of the registeraccessed the possibility to change the I2C address via externalpins has been deprecated in this prototype.

Figure 25: PACIFICr5 I2C read

Standard read (figure 25) and write (figure 26) sequencescan be observed with the acknowledge coming from PACIFICand other relevant events highlighted.


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Figure 26: PACIFICr5 I2C write

ANODE VOLTAGE CONTROL

The voltage present on the SiPM anode can be fine tunedusing an internal configuration. This adjustment permits tochange in a range from 100 to 700mV. In figure 27 a mea-surement of only one channel is performed to check the func-tionality of the system (no representative difference has beenfound between channels).

Figure 27: PACIFICr5 Anode voltage control

Again for PACIFICr5pq a slightly modified version of the volt-age divider providing the anode voltage control steps has beenused. In this case it can be observed a slightly smaller adjuststep (around 40mV) with a fully usable range (without satura-tion for higher voltages) as seen in figure 28.

Figure 28: PACIFICr5pq Anode voltage control

TEMPERATURE SENSOR

An internal temperature sensor is available and can be readinternally by the ADC or externally using a multiplexed outputpin. Simulations show a single point should be enough for cal-ibration with reasonable accuracy. The sensor output is mea-sured just at the moment of starting the power supply and isassumed to be room temperature. The evolution (self heating)of the device with time can be seen in figure 29.

Figure 29: PACIFICr5 Temperature sensor output


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REFERENCE VOLTAGES and DACs

Several voltages are generated from an in circuit BandgapReference. In previous measures this reference is close to theexpected value (500mV), but usually higher. Some of the ref-erence voltages can be adjusted and directly measured exter-nally starting from the main bandgap reference itself. In figures30a, 30b several DAC measurements can be observed.

(a) Voltage Reference control

(b) DC feedback voltage control

Figure 30: PACIFICr5 main reference DACs

To achieve the desired soft start in PACIFICr5pq the mainVREF DAC has been modified to reduce it’s adjustment range.In consequence the LSB has also been reduced as seen infigure 31. The rest of DACs have been kept as in previousversion.

Figure 31: PACIFICr5pq Voltage Reference control

It can also be observed a small improvement in local thresh-old DACs uniformity in latest version as seen in figure 32 incomparison to 33d. This is due to the improvement in thepower distribution in PACIFICr5pq.

Figure 32: PACIFICr5pq local threhsold DACs


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In a similar DAC (8 bits now) the Threshold voltages are generated. In figures 33a, 33b and 33c the common thresholdsDACs can be observed with the 8bits resolution. The possibility to adjust the thresholds independently channel by channel isaccomplished using a set of three DACs on each channel. A control bit by channel selects which set of DACs is used (local orcommon). In figure 33d all local DACs are plotted (192).

(a) First threshold adjustment DAC (b) Second threshold adjustment DAC

(c) Third threshold adjustment DAC (d) Local threshold DACs

Figure 33: PACIFICr5 Thresholds DACs


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OFFSET and SLOPE control

An addition to PACIFICr5 is to control the OFFSET and SLOPEof all the threshold DACs at the same DAC. This permits moreflexibility to adapt the conditions for different reference voltageon the analog processing chain and also to cover the full sig-nal range in all channels. The effect of this control can beobserved in figures 34b abd 34a for few values.

(a) Threshold DACs slope control

(b) Threshold DACs offset control

Figure 34: PACIFICr5 Thresholds DACs common control

HIGH SPEED SERIALIZER

The DATA output from PACIFICr5 uses High Speed Serializersat 320MHz. The Serializer encodes 4 channels 3 bits outputsinto 8 bits. For test purposes the possibiliy to change the SLVSdriver current has been added as one general control bit. Infigure 35 the effect of this control bit can be observed. Forsimplicity only one of the two differential outputs is plotted witha single one followed by zeros.

Figure 35: High speed serializer output for different current

An other aspect from the output serializers is the possibleintroduction of internal delays in the ASIC. To check the delayis controlled and thus there is no need to sample the data out-put with different phases a simple output has been measuredfor the 16 differential SLVS outputs and can be observed onfigure 36

Figure 36: High speed serializer outputs difference


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THRESHOLDS SCAN

With the internal DACs and averaging the output of eachchannel an S-Curve can be plotted and looks as expectedshowing sharp transitions to zero level (see figure 37).

Figure 37: PACIFICr5 typical S-curve

TRIMMING

Using the voltage modification circuit present at the integra-tors the transition position can be moved thus permitting thealignment of the channels (offset compensation). If the tran-sition point is plotted we can observe a linear behaviour (seefigure 38). Since a coarse DAC is present on the common biasthe slope of this line can be changed using a global register.

Figure 38: PACIFICr5 trimming

With optimized trimming values a Trimmed S-curve can begenerated (see figure 39a) with a much reduced dispersion(see figure 39b).

(a) Trimmed S-curve

(b) Trimmed dispersion

Figure 39: PACIFICr5 trimmed output


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INTERNAL ADC

An internal ADC (10bit) is also available with the multi-plexed input. It can be used to read all the relevant analogbias voltages from the ASIC and also the temperature sensorand two external inputs to the ASIC (EXT and ADC_TEST).For the purpose of reading external PT1k or NTC sensors a1V reference output is also available (VREFOUT). The calibra-tion of the ADC is performed using an external DAC (12bit)and external ADC (12bit) to correlate the Voltage input to ADCoutput (see figure 40).

Figure 40: PACIFICr5 Internal ADC calibration

As expected due to some comparator offset of the WilkinsonADC the conversion starts at around 150mV input.

PACKAGE MARKING

A packaged version of PACIFIC is already available but yetnot tested. The marking includes a QR code corresponding tothe serial number printed.


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SIPM TESTS

An old SiPM version (2015) has been tested together with some light source to validate the prototype and nice photon peakbands have been observed (see figure 41).

Figure 41: PACIFICr5 light measurements with different intensity


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KNOWN ISSUES

• A bug in the error detection from the Hamming encoding makes the errors from register x0E8h (D_Vth42_3) counted twicewhile the errors of register x0E8h (D_Vth43_1) are not counted. Both of them still trigger the error signals ERROR1 andERRORM.

• PACIFICr5a exhibits usually a higher power consumption after the Power On Reset. This is due to the higher than expectedby simulations voltage at the Bandgap output. After configuration of the calibrated values the power consumption goes tothe expected levels, but this can be an issue in large experiments (such as SciFi).

• PACIFICr5a and PACIFICr5p present higher spillover compared to PACIFICr5q as explained in the Track and hold Bottomplate connection section. A more aggressive shaper configuration can be used to minimize it with the inconvenient that wemay lose some signal.

• Due to the clock generator circuit described in the Bottom plate connection section PACIFICr5q exhibits a different be-haviour regarding the SYNC signal than the other versions. More specifically the integrator order is inverted with relationto the other versions.

• Repeatability of adjustment conditions after a power cycle has been found to be an issue during test-beams. The origin isstill unclear but variations of the analog channel adjustment in the order of 40mV (10 DAC counts depending on conditions)may be expected after power cycles.


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NOTES

c© 2018 ICC-UB / HD-PI / LPC / IFIC, All rights reserved.Trademarks and registered trademarks are the property of their respective owners.http://icc.ub.eduhttp://www.physi.uni-heidelberg.dehttp://clrwww.in2p3.frhttp://ific.uv.es


pacificr5 - 64 channels sipm readout asic for the scifi tracker detector … · 2019. 4. 22. ·...

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