JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, VOL. 7, NO. 2, JUNE 2009 160

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

Wen-Tao Han, Qi Yu, Song Ye, and Mo-Hua Yang

Abstract⎯A 1.34 GHz±60 MHz low noise amplifier

(LNA) designed in a 0.35 μm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure (NF) of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point (IP1dB) of −11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.

Index Terms⎯Impedance matching, linear circuits, low noise amplifier.

1. Introduction Low noise amplifier (LNA) is the first stage of a radio

frequency (RF) receiver and its noise characteristic dominates the overal1 noise performance of the receiver. In general, the requirements of a LNA are, apart from low noise, sufficiently high gain to suppress noise contributions from subsequent stages, high linearity to restrain gain compression, and well-defined input impedance to match the input source[1].

Due to rapid progress and high quality demands in radio communication, the design trends for LNA are high linearity, high gain, low noise, and low power consumption. However, it is well known that the achievement of high linearity will cause the gain to decrease along with the increase of noise figure (NF) and power consumption. Therefore, how to trade off among high linearity, high gain, and low NF while not increasing power consumption and chip size is the most important design challenge nowadays.

Many methodologies are reported to improve the linearity of a LNA, such as harmonic tuning using a low frequency trap[2], third order cancellation using transistors

Manuscript received August 13, 2008; revised October 20, 2008.

W.-T. Han, Q. Yu, and M.-H. Yang are with State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, China (e-mail: hanwentao@gmail.com).

S. Ye is with BroadGalaxy Electronics Technology Ltd., Chengdu, 610065, China. (e-mail: sye@broadgalaxy.com).

with different Gm[3],[4] and predistortion method[5],[6].

However, these methods either require precise control or involve complex circuits, so most times they cannot be easily utilized in practical applications.

This paper presents a high linearity high gain single- ended LNA for a radar receiver by using a linearizing bias circuit. Through steadying the bias point, the linearizing bias circuit offers good linearity performance without degrading other performance. The paper is organized as follows. In section 2, the biasing technique is introduced. Section 3 presents the LNA circuit design and imple- mentation. Simulation results are summarized in Section 4.

2. Biasing Technique Linearity is a crucial consideration in LNA design,

because a circuit’s nonlinearity brings a lot of problems such as gain compression and inter-modulation, which is undesirable. Usually, the small-signal gain of circuit is obtained with the assumption that harmonics are negligible. However, as the signal amplitude increases, the gain begins to vary. In fact, nonlinearity can be viewed as variation of the small-signal gain with the input level. The output is a compressive or saturating function of the input. This effect is quantified by the IP1dB, defined as the input signal level that causes the small-signal gain to drop by 1 dB. At high input signal levels, a high IP1dB is required to ensure linearity. For RF amplifiers with BJT devices including SiGe HBT devices, the design of base bias circuit is a key issue to achieve high IP1dB

[6]. Hence, the bias circuit is one of the most important parts of this design.

Fig. 1 shows the bias circuits for HBTs. Traditional passive mode is composed of two dividing resistors, as shown in Fig. 1 (a). When input power increases, the voltage and current applied to the base-emitter diode will be restrained owing to the clamping characteristic of the diode. The average DC current rectified by the base-emitter diode will increase with the input power. However, the base-emitter voltage Vbe will decrease by ΔVbe. This will result in transconductance drop or gain reduction, which means poor linearity. Consequently, in order to obtain a good linearity performance, the bias point should maintain a constant level when input power changes. An effective

HAN et al.: Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit 161

way to compensate the ΔVbe is to adopt the active biasing technique[7]. As shown in Fig. 1 (b), the linearizing active bias circuit is used as a predistorter in this design. N1 and N2 indicate the emitter area factors of corresponding transistors. The virtual current model ΔIbe shows the increase of base current in the large-signal region. To simplify the analysis, it is assumed that all transistors in the bias circuit have the same forward current gain β and saturation current IS. The ratio of the transistor size used in the bias circuit and the LNA is N1: N2. In order to mirror the current correctly, the resistors ought to satisfy R1N2 = R2N1, and the relation of the currents is IbeN1 = N2Ib1. The current IR3 is ignored as R3 is usually very large.

A HBT’s V-I equation is

1be ln c

TS

IV V

I⎛ ⎞

= ⎜ ⎟⎝ ⎠

(1)

where VT is the thermal voltage (kT/q), 26 mV in room temperature.

According to Kirchhoff laws, the currents flow at each node are expressed as

1 refc 2bI I I= − (2a)

2b2 1

eII

β=

+ (2b)

2 1 be bee bI I I I= + + Δ (2c)

11

cb

II

β= . (2d)

By using (1) and (2), Vb1 is expressed as

ref1

2 1 be 1

( 1)1ln( 1) 1b T

S

IV V

I N N Iβ β

β β⎧ ⎡ +⎪= ⎨ ⎢ + + + + Δ⎪ ⎣⎩ bI

⎫⎤⎪⎬⎥⎪⎦⎭

. (3)

From Fig. 1 (b), Vbe can be expressed as

be 1 bebV V I R= − Δ 2 . (4)

Substituting (3) into (4) gives

refbe be 2

( 1)1ln TI

V V I Rβ β⎧ ⎫⎡ ⎤+⎪ ⎪= −⎨ ⎬⎢ ⎥+ + + + Δ⎪ ⎪⎣ ⎦⎩ ⎭2 1 be 1( 1) 1S bI N N I Iβ β

Δ . (5)

(a) (b)

Fig. 1. Bias circuit: (a) traditional passive and (b) linearizing active mode.

Applying Taylor series in (5), Vbe is obtained as

( )ref

be2 1

( 1)ln

( 1) 1TS

IV V

I N Nβ β

β β+

=+ + +

( )be

be 21 2 1( 1) 1

T

b

V II R

I N Nβ βΔ

− −+ + +

Δ . (6)

Equation (6) can be rewritten as

be 1 2 2 b( )V C C R I e= − + Δ (7) with

( )ref

1

2 1

( 1)ln

( 1) 1TS

IC V

I N Nβ β

β β+

=+ + +

( )2

1 2( 1) 1T

b

VC

1I N Nβ β=

+ + +,

where C1 and C2 are constant. Equation (7) shows that Vbe is almost independent of ΔIbe if R2 is chosen as the minimum value that satisfies the correct current division. Then the LNA will have a good linearity performance because its operating point is hardly changed. However, a small R2 will result in bad NF because it can not effectively prevent RF leakage signal from going into the bias circuit. Therefore, the value of R2 should be traded off between NF and linearity.

3. LNA Circuit Design and Implementation

Fig. 2 shows the architecture of the proposed LNA. The cascode configuration is adopted because of its good trade-off among low noise, high gain, and good isolation[8]. Emitter degeneration is employed to achieve good input matching and low noise figure at the resonance frequency of the input network and improve the linearity of the LNA.

The matching networks are outlined with the dashed boxes[9] in Fig. 2. The input matching network is designed to synthesize the optimum reflection coefficient for mini-

Vout

Lc

II c2ref LIb2

CVb RLQ2

Fig. 2. Cascode architecture with matching networks.

R1

R2

Vbe

I Vb2 OutputIc1 Vine2−

N1

Vb1

Ib1 R1

Vref R3

R2Ibe1 I matchingbe

Vbe−

LbRSN2IR3

ΔIbe

VS

Zin

Input Q1matching

Le

JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, VOL. 7, NO. 2, JUNE 2009 162

mum noise figure from the characteristic impedance[10]. A conventional series-connected inductor Lb is inserted between the source and the input to match the input to 50 Ω. The input impedance can be expressed as

( )in1m e

b eg L

Z j L LCπ

ωω

⎡ ⎤= + + −⎢ ⎥

⎣ ⎦Cπ

. (8)

The degeneration inductor Le achieves the real part input matching[11]. The series-connected inductor Lb provides the imaginary-part input matching combined with Le. To realize input matching, the real part of (8) should be 50 Ω, whereas the imaginary part should be zero at the required operating frequency. According to (8), the required base inductor Lb is usually very large to make the imaginary part be zero. Since integrated inductors with large values exhibit low quality factor and contribute much thermal noise as a result of parasitic resistances. To save the chip area, Lb is realized by off-chip inductors taking into account parasitic inductance due to bonding wires. There are various impedance matching networks to realize output matching, such as L-match, T-match and π-match. An L-match network making up of L and C is introduced to make the output impedance matched in this design. The L-match has least components so that it eases the output matching.

Fig. 3 shows the final circuit of the proposed LNA. The amplification of signal is provided two cascode transistors Q1 and Q2 with inductive degeneration Le. The RF input signal comes into the circuit through the base of Q1. The output signal is accessed from the collector of Q2. The cascode transistor Q2 improves reverse isolation between input and output terminals and lowers Miller multiplied capacitance. Iref1 and Iref2 are reference currents from bandgap current reference. R1 offers a voltage bias to Q2. Q3, Q4, R2, and R3 consist of the bias circuit for Q1. Q1 and Q3 compose a current mirror. To achieve a complete mirror,

Fig. 3. Simplified schematic of the proposed LNA.

R2 is N times of R3. And R3 needs to be bigger enough to prevent RF leakage signal from going into the bias circuit. Q3 should be one Nth of Q1 to lower the power consumption. Q4 offers a base compensation of Q1. Bypass capacitors C1 and C2 are introduced to filter the RF signal in the bias circuit. Q5 and R4 provide a DC loop to ground. The designed LNA shows an IP1dB of −11.52 dBm, a power gain of 21.46 dB, and a NF of 1.27 dB. The amplifier draws 10 mA from a 3.3 V supply.

The proposed LNA is designed in a 0.35 μm SiGe BiCMOS process. This process is chosen because of its balance among performance, cost, and complexity.

4. Simulation Results The small signal S-parameters (S11, S12, S21, and S22),

NF, and IP1dB of the proposed LNA are simulated with Cadence Spectre RF. The operating frequency of the LNA is 1.34 GHz±60 MHz. Post-simulation results show that the LNA achieves comparable performance than previous results with the linearizing bias circuit.

Fig. 4 shows the layout of the LNA. The parasitic effects are extracted and taken into account in the post- layout simulations. The die size is 0.26 mm×0.20 mm including the bias circuits.

Fig. 4. Layout of the proposed LNA.

rfout

rfin

Cin

Lb

Le

Q1 L

CCout

LcIref2 Iref1

Q2

R4 C2Q4

R2

C1 Q5

R3

Q3

R1

1.28 1.32 1.36 1.4020.7

21.0

21.3

21.6

S21

NF

Frequency (GHz)

S 21 (d

B)

1.23

1.26

1.29

1.32

NF (dB

)

NF

(dB

)

Fig. 5. Post-layout simulations of S21 and NF against frequency.

HAN et al.: Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit 163

1.28 1.32 1.36 1.40−16

−15

−14

−13

S11

S22

Frequency (GHz)

S 11 (d

B)

−15

−12

−9

−6

S22

dB)

(dB)

−20 −18 −16 −14 −12 −100

4

8

12

Fig. 6. Post-layout simulations of S11 and S22 against frequency. Fig. 6. Post-layout simulations of S

−20 −18 −16 −14 −12 −100

4

8

12

11 and S22 against frequency.

1st order 1dB/dB

Out

put p

ower

(dB

m)

Input power (dBm)

Input referred 1dB compression = −11.52

1st order freqency = 1.34 GHz

Fig. 7. Post-layout simulation of the IP1dB.

Table 1: Comparison with previous work

Ref. Freq. (GHz)

S21(dB)

NF (dB)

IP1dB(dBm)

Area (mm2)

BiCMOS(μm)

[12] 3-5 11.8 <3.0 −16 1.13 0.35 [13] 5-6 20 <2.5 −16.5 1.56 0.35 [14] 5 18.3 1.65 −12.25 N/A 0.5 [7] 2.14 20 1.65 −12.3 0.83 0.35

This work 1.34 21.46 1.27 −11.52 0.05 0.35

Post-layout simulations of NF and S21 against

frequency are shown in Fig. 5. The power gain S21 is 21.46

dB at 1.34 GHz with gain flatness of ±0.37 dB between 1.28

GHz and 1.4 GHz. The NF is 1.27 dB at 1.34 GHz and keeps below 1.32 dB over the entire band. Fig. 6 shows the post-layout S11 and S22 of the LNA. Return loss S11 is well below −13.33 dB and S22 is better than −8.93 dB. The stability factor has also been calculated from the S-parameters and shows that the LNA is unconditionally stable over the entire working band.

The input power is swept over a range of values such that the IP1dB falls within this range. The range is from −20 dBm to −10 dBm and Fig. 7 shows the post-layout simulation result of the IP1dB. It can be seen that the IP1dB is −11.52 dBm.

The performance of the proposed LNA is shown in Table 1. Comparisons with pervious designs are also included. Compared with the recent reported high gain LNAs, the proposed LNA has a better linearity without

degrading other performance. The linearity enhancement mainly owe to the use of the linearizing bias circuit. Moreover, the proposed LNA has a higher gain, lower NF, better linearity, and smaller area compared to the previously reported works. Good trade-off is obtained while not increasing power consumption. S 2

2 (d

B)

5. Conclusions A high gain LNA with a linearizing bias circuit is

presented in this paper. The active biasing technique has been expounded and compared with traditional passive biasing technique. Formula derivation is also given to explain the principle of linearity enhancement. Since the linearizing bias circuit does not need any area consumptive devices, it can be easily realized on chip. Based on the active biasing technique, both high linearity and high gain characteristic can be obtained with the linearizing bias circuit but no deterioration of other performance. Proved by post-layout simulation results, the proposed LNA achieves a good trade-off among high linearity, high gain, and low NF while not increasing power consumption and chip size. It shows an IP1dB of −11.52 dBm, a power gain of 21.46 dB, and a NF of 1.27 dB with a current consumption of 10 mA from a 3.3 V supply.

Acknowledgment The authors would like to thank BroadGalaxy Electronics

Technology Ltd. for technical assistance. The authors would also like to thank Da Chen, Dong Li, and Lu Shen for their kind help.

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Wen-Tao Han was born in Shaanxi Province, China, in 1983. She received the B.S. degree in microelectronics from the University of Electronic Science and Technology of China (UESTC), Chengdu, in 2006. She is currently pursuing the M.S. degree with State Key Laboratory of Electronic Thin Films and

Integrated Devices, UESTC. Her research interests focus on RF ICs.

Qi Yu was born in Shandong Province, China, in 1972. He received the B.S. and M.S. degrees from UESTC, in 1994 and 1997, respectively, all in microelectronic. Currently he is an associate professor with State Key Laboratory of Electronic Thin Films and Integrated Devices, UESTC. His research interests

include VDSM circuit and SOC, ADC/DAC, and ULSI reliability simulation & monitoring.

Song Ye received the M.S.E.E. in Communi- cations and M.A.Sc. in Microelectronics from the University of Toronto. From 1996 to 2004, he had been with OKI Semiconductor, Motorola, SpaceBridge, and Engim where he has developed RF and analog chips for mobile communications, radars, and satellites. He is a

committee member of IEEE-ISCAS. Currently he is a jointed professor with Southeast University, and the chief technology director with BroadGalaxy Electronics Technology Ltd. His research interests are in wireless RF IC architectures and their building block integrations as well as mixed-signal design using SiGe, CMOS, and GaAs process.

Mo-Hua Yang was born in Sichuan Province, China, in 1945. He received the B.S. degree in radio-electronics from Sichuan University and M.S. degree in microelectronics from UESTC, in 1967 and 1981, respectively. He is currently a professor and Ph.D. advisor with School of Microelectronics and Solid-State Electronics,

UESTC. His research interests include ULSI mixed signal processing, GaN/SiGe device and circuits, and nano-electronics.