sequencing and controlviplab.cs.nctu.edu.tw/course/dsd2015_spring/dsd_lecture_02.pdf · i. the...

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Sequencing and Control

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science National Chiao Tung University

Taiwan, R.O.C. Spring, 2015

Source: Prof. M. Morris Mano and Prof.

Charles R. Kime, Logic and Computer Design

Fundamentals, 3rd Edition, 2004, Prentice Hall.

Digital Systems Design

Lecture 2

Content Connections

Digital System

Design Embedded System: Zedboard

DSP System: Adder, Mul, Filter

Computer Architecture

2

Embedded System: Galileo


Lecture 2

3

Outline

Control Unit

Algorithmic State Machines (ASM)

ASM Chart Example: Binary Multiplier

Hardwired Control

Microprogrammed Control

Summary


Lecture 2

4

Digital System (1/3)

Digital system:

— Datapath + Control unit

Binary information stored in a DSP system and

digital computer:

— data or control information

Timing of a synchronous digital system:

— all regs are controlled by a master clock generator

Two types of digital systems:

i. Programmable system

ii. Nonprogrammable system


Lecture 2

5

Programmed system:

— Instruction: a portion of the input to the processor

specifies the op that the system is to perform

which operands to use for the op

where to place the results of the op

which instr to execute next (optional)

— RAM or ROM: memory stores the instrs

— PC: program counter provides the addr in memory

of the instr to be executed

— Executing an instr: activates the necessary

sequence of -ops in the datapath that are required

to perform the op specified by the instr



Lecture 2

6

Nonprogrammable system:

— needs not obtain instrs from memory no PC

— The control unit determines the ops to be performed

and the sequence of those ops, based on only its

inputs and the status bits



Lecture 2

7

Algorithmic State Machines (ASM)

ASM chart:

— Describe procedural steps and decision paths for the

hardware algorithm.

— Describe a sequence of events and the timing

relationship b/t the states of the control unit, and the

actions that occur in the states in response to clock

pulses.

Hardware algorithm:

— Define the register transfer ops controlled by a

sequencing mechanism of a data-processing task

design both the datapath and the control unit


Lecture 2

8

ASM Chart

Four basic elements: ASM primitives

i. State box ii.Scalar decision box

iv. Conditional output box iii. Vector decision box


Lecture 2

9

State Box

A rectangle-shaped box with:

— The symbolic name for the state marked outside the

upper left top

— Containing register transfer operations and outputs

activated within or while leaving the state

— An optional state code, if assigned, outside the upper

right top

(Symbolic Name)

IDLE

(Register transfers

or outputs)

R ← 0

RUN

(Optional state code)

0000


Lecture 2

10

Scalar Decision Box

A diamond-shape box with:

— One input path (entry point).

— One input condition, placed in the center of the

box, that is tested.

— A TRUE exit path taken if the condition is true

(logic 1).

— A FALSE exit path taken if the condition is false

(logic 0).

(Input)

START

(True Condition) (False Condition)

0 1


Lecture 2

11

Vector Decision Box

A hexagon-shaped box with:

— One input path (entry point).

— A vector of input conditions, placed in the center of the

box, that is tested.

— Up to 2n output paths. The path taken has a binary

vector value that matches the vector input condition.


Lecture 2

12

Conditional Output Box

An oval-shaped box with: — One input path from a decision box or decision boxes.

— One output path

— Register transfers or outputs that occur only if the

conditional path to the box is taken.

(Register transfers

or outputs)

R ← 0 RUN

From Decision Box(es)


Lecture 2

13

ASM Blocks

An ASM block consists

of one state box and all

of the decision and

conditional output

boxes connected

between the state box

exit and entry paths to

the same or other

state boxes.


Lecture 2

14

ASM Timing Behavior (1/2)

ASM timing behavior:

— Any reg transfer for which conditions are satisfied

within the ASM block will be executed when the

clock event occurs.

— Register transfers occur at the clock while exiting

the state - New value occurs in the next state!


Lecture 2

15

ASM Timing Behavior (2/2)

Clock cycle 1 Clock cycle 2 Clock cycle 3

Clock

START

Q 1

AVAIL

IDLE MUL 1

0034 0000

State

A

Q 0


Lecture 2

16

Example: Binary Multiplier (1/3)

Problem description for binary multiplier:

— Design a digital system that multiplies two unsigned binary

numbers by successive shifts and adds.

— (n-bit multiplicand) (n-bit multiplier) = (2n-bit product)

Paper and pencil method: — Look at successive bits of the multiplier, LSB first.

— If the multiplier bit is 1, the multiplicand is copied down to enter into the addition to be performed later. Otherwise, 0’s are copied down.

— The numbers copied in successive lines are shifted one position to the left from the previous number copied.

— Finally, the numbers are added and their sum forms the product.


Lecture 2

17


— E.g.: 10111 × 10011


Lecture 2

18


— E.g.: 10111 × 10011


Lecture 2

19

Block Diagram

C out

n

n

n-1

Counter P

Zero detect

Control

unit

G (Go)

log 2 n

Q o

Z

Parallel adder

Multiplicand

Register B

Shift register A 0 C Shift register Q

Multiplier

Product

OUT

IN

Control signals

n

n

n

4


Lecture 2

20

ASM Chart (1/2) 1. The multiplicand (top operand) is loaded into register B.

2. The multiplier (bottom operand) is loaded into register Q.

3. Register C||A is initialized to 0 when G becomes 1.

4. The partial products are formed in register C||A||Q.

5. Each multiplier bit, beginning with the LSB, is processed (if bit is 1, use adder to add B to partial product; if bit is 0, do nothing)

6. C||A||Q is shifted right using the shift register

— Partial product bits fill vacant locations in Q as multiplier is shifted out

— If overflow during addition, the outgoing carry is recovered from C during the right shift

7. Steps 5 and 6 are repeated until Counter P = 0 as detected by Zero detect.

1. Counter P is initialized in step 4 to n – 1, n = number of bits in multiplier


Lecture 2

21

ASM Chart (2/2)

ASM chart for multiplier:

— Assumption

— Initially, the multiplicand is in B &

the multiplier is in Q. ( The

loading of these two regs is not

handled by the multiplier control

unit)


Lecture 2

22

Microoperation in Datapath

Datapath for the multiplier:

— -ops listed in the ASM chart datapath


Lecture 2

23

Control Part

Implementation of a control unit:

i. The control signals of the -ops for the datapath

ii. The sequencing of the control unit and -ops

ASM chart Control unit

i. A table that defines the control signals in terms of

states and inputs output behavior of C.U.

ii. A simplified ASM chart that represents only

transitions from state to state next-state behavior

of C.U.


Lecture 2

24

Control Signal Table (1/2)

Control Signals for Binary Multiplier

Bloc k Dia g ram

Mod u l e Mi cr oo pe ra ti on

Contr o l

Si gn al N a me

Contr o l

Exp r e ssi on

Register A : A ← 0 I nitia liz e G

A ← A + B Load MUL0 ·

Q0

C || A || Q sr C || A || Q Shift_dec M UL1

Register B : B ← IN Load_B LO ADB

F lip-F lop C : C ← 0 C lea r _C IDLE ·

G + MUL1

C ← C ou t Load —

Register Q : Q ← IN Load_Q LO ADQ

C || A || Q ← sr C || A || Q Shift_dec —

Cou n ter P : P ← n – 1 I nitia liz e —

P ← P – 1 Shift_dec —

IDLE ·

←


Lecture 2

25

Signals are defined on a register basis.

LOADQ and LOADB are external signals controlled from the

system using the multiplier and will not be considered a part of this

design.

Note that many of the control signals are “reused” for different

registers.

These control signals are the “outputs” of the control unit.

Control Signal Table (2/2)


Lecture 2

26

Sequencing Part of ASM

Next-state behavior State diagram

— remove -ops, conditional output boxes, & any

decision box not affecting the next state

0 1

IDLE

MUL0

0 1

01

MUL1 10

00

G

Z


Lecture 2

27

Control Design Methods

— The procedure from Chapter 6

Not suitable for a large amount of input states

— Procedure specializations that use a single signal to

represent each state

Sequence Register and Decoder

Sequence register with encoded states, e.g., 00, 01, 10, 11.

Decoder outputs produce “state” signals, e.g., 0001, 0010,

0100, 1000.

One Flip-flop per State

Flip-flop outputs as “state” signals, e. g., 0001, 0010, 0100,

1000.

Hardwired Control


Lecture 2

28

Sequence Reg and Decoder Design (1/6)

Initially, use sequential circuit design techniques from

Chapter 6.

First, define:

— States: IDLE, MUL0, MUL1

— Input Signals: G, Z, Q0 (Q0 affects outputs, not next state)

— Output Signals: Initialize, LOAD, Shift_Dec, Clear_C

— State Transition Diagram (Use sequencing ASM)

— Output Function

Second, find

— State Assignments (two bits required)

— We will use two state bits to encode

the three state IDLE, MUL0, and MUL1.

State M1 M0

IDLE 0 0

MUL0 0 1

MUL1 1 0

Unused 1 1


Lecture 2

29

Assuming that state variables M1 and M0 are decoded into states,

the next state part of the state table is:

Current State Input

G Z

Next State

M1 M0

IDLE 0 0 0 0

IDLE 0 1 0 0

IDLE 1 0 0 1

IDLE 1 1 0 1

MUL0 0 0 1 0

MUL0 0 1 1 0

MUL0 1 0 1 0

MUL0 1 1 1 0

Current State

M1 M0

Input

G Z

Next State

M1 M0

MUL1 0 0 0 1

MUL1 0 1 0 0

MUL1 1 0 0 1

MUL1 1 1 0 0

Unused 0 0 d d

Unused 0 1 d d

Unused 1 0 d d

Unused 1 1 d d



Lecture 2

30



Lecture 2

31


Finding the state equations for M1 and M0 is easier due

to the decoded states:

DM1 = MUL0

DM0 = IDLE · G + MUL1 · Z

Note that since there are five variables, a K-map is

harder to use, so we have directly written reduced

equations.

The output equations using the decoded states:

Initialize = IDLE · G

Load = MUL0 · Q0

Clear_C = IDLE · G + MUL1

Shift_dec = MUL1


Lecture 2

32


Doing multiple level optimization, extract IDLE · G:

Initialize = IDLE · G

DM1 = MUL0

DM0 = Initialize + MUL1 · Z

Load = MUL0 · Q0

Clear_C = Initialize + MUL1

Shift_dec = MUL1

The resulting circuit using flip-flops, a decoder, and the

above equations is given on the next slide.


Lecture 2

33


IDLE

MUL0

MUL1

Initialize

Clear_C

Shift_dec

M 0

Load

M 1

G

Z

Q 0

DECODER

A0

A1

0

3

2

1

D

C

D

C

Initalize

Two one-bit seq regs + One 2-to-4 line decoder


Lecture 2

34

This method uses one flip-flop per state and a

simple set of transformation rules to implement

the circuit.

The design starts with the ASM chart, and

replaces

1. State boxes with flip-flops,

2. Scalar decision boxes with a demultiplexer with 2

outputs,

3. Vector decision boxes with a (partial)

demultiplexer

4. Junctions with an OR gate

5. Conditional outputs with AND gates.

One Flip-Flop per State


Lecture 2

35

State Box Transformation Rules

Each state box transforms to a D flip-flop

Entry point is connected to the input.

Exit point is connected to the Q output.

STATE

Entry

Exit

D Q

Entry

Exit

STATE


Lecture 2

36

Scalar Decision Box Transformation Rules

Each decision box transforms to a demultiplexer

Entry point is an “enable" input.

The condition is the “select" input.

Decoded outputs are the exit points.

X0 1

Entry

Exit 0 Exit 1

XEntry

Exit 0 Exit 1


Lecture 2

37

Vector Decision Box Transformation Rules

Each Decision box transforms to a demultiplexer

Entry point is an enable input.

The conditions are the select inputs.

Demultiplexer outputs are the exit points.

(Vector of Input

Conditions)

(Binary Vector Values)

00

01

(Binary Vector Values)

10

X1, X0

X1

Entry Exit 0

Exit 1

X0

DEMUX

EN

A1 A0

D0

D2

D1

D3

Exit2

Exit 3

11


Lecture 2

38

Junction Transformation Rules

Entry 1

Exit

Entry 2 Entry 1

Exit

Entry 2

Where two or more entry points join, connect the entry

variables to an OR gate

The exit is the output of the OR gate.


Lecture 2

39

Conditional Output Box Rules

X 1

Entry

Exit 1

OUTPUT

X

Entry

Exit 1

OUTPUT

Entry point is an enable input.

The control OUTPUT is the same signal as the exit

value.

Enable


Lecture 2

40

Multiplier Example: Flip-flop per State Design Logic Diagram

D1 D0


Lecture 2

41

Microprogrammed Control

Microprogrammed control:

— a control unit with its binary control values stored as

words in memory (control memory)

— Microinstruction: -instr

each word in the control memory, specifies one or more -

ops for the system

— Microprogram: -prog

a sequence of -instrs

— Microprogramming: places some representation for

combinations of values of control variables in words

of ROM for use by the rest of the control logic via

successive read ops.


Lecture 2

42

The general configuration of

a -p control:

— CM: control memory

— CAR: control addr reg

— CDR: control data reg

(optional)

— Next-addr generator

Microprogrammed Control Unit Organization


Lecture 2

43

Microprogrammed Control for Binary Multiplier

ASM charts for -p controls:

— the seq ckts must be Moore-type

— no conditional output box is permitted in the ASM chart


Lecture 2

44

Determine the bits in the control word for the -

instrs.

— -instr control word format

Determine the sizes of the ROM (CM) and the

CAR.

Determine the structure of the next-addr

generator and design the sequence

Write the -prog.

Design of a -p Control Unit


Lecture 2

45

-instr Control Word Format

-instr control word format:

— Control signals to datapath

— Control outputs

— Next-address information

(Sequencing)


Lecture 2

46

Next-Address Information

Two typical approaches to define the addrs: — Method 1: two-addr-per- instr method

Include the two addrs in the -instr controlling the decision. Based on the value of the decision variable, one of the two addr values is loaded into the CAR. CAR: a reg w/ parallel load

Adv.: permits the arbitrary assignment of addrs to states (no states need to be added for the desired sequencing)

Disadv.: requires 2 addrs in each -instr (wide ROM)

— Method 2: parallel-load counter method Use a counter with parallel load as the CAR. One of the two

addrs is obtained from the -instr, but the other is obtained by counting up the CAR.

Adv.: requires at most 1 addr per -instr

Disadv.: states may have to be added for the desired sequencing (slower system)


Lecture 2

47

Control Word Format Example (1/3)

-instr control word format of the binary

multiplier:

— Control signals:

DATAPATH

— Control outputs: none

— Sequencing: 2 addr fields

NXTADD1

NXTADD0

SEL


Lecture 2

48

Control signals: DATAPATH



Lecture 2

49



Lecture 2

50

Sizes of the ROM and the CAR


Lecture 2

51

Structure of the Next-Addr Generator

CAR

NXTADD1

NXTADD0

SEL


Lecture 2

52

Structure of the Microprogrammed Control Unit


Lecture 2

53

Microprogram


Lecture 2

54

Summary

Interaction b/t datapaths and control units

Programmed vs. Nonprogrammed systems

Algorithmic state machine (ASM): a means for

representing and specifying control functions

Example: Binary multiplier

Hardwired control

— Basic design procedure

— Sequence reg plus decoder

— One flip-flop per state

Microprogrammed control

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