soc-06：digital control of dc-dc...

Digital Control of DC-DC Converters

NCTU 2005 Course Notes: SoC & SoP for Power Electronics 1

page 1

2005421

Filename: \A02 ()\SoC-06Digital Control of DC-DC Converters.ppt

Digital Control of DC-DC Converters- An Introduction

DSPPower Electronics IC Design & DSP Control Lab., NCTU, Taiwan

http://powerlab.cn.nctu.edu.tw/

POWERLABNCTU

DSPPower Electronics IC Design & DSP Control Lab.

page 2

Contents

1. Analog PWM IC2. Digital PWM IC3. Digital PWM IC: Future Outlook4. Digital Control Loop Design 5. Digital Controller Realization



page 3

1. Analog PWM Control IC

Power Electronics IC Design and DSP Control Lab., NCTU, Taiwan


page 4

UC3845: PWM Control ICs from TI (Unitrode)



page 5

UC3845: Features and Block Diagram

Optimized for Off-line and DC-DC ConvertersLow Start Up Current (



page 7

UCC3960: First primary side start-up PWM uses digital feedback

FeaturesOver current protection with soft startProgrammable maximum duty cycle clamp (UCC3960)Programmable volt second clamp (UCC3961)Programmable UV and OV sense (UCC3961)Self-bias regulator for external start switch in UCC3961Provides primary-side start-up functions for secondary-side controlled convertersIsolated PWM command through a pulse transformerLow current start-up with optional disconnectUp to 400-kHz synchronizable switching frequencyHigh-current FET drive (1.5-A sink, 0.75-A source)Packaging: Available in 8-pin SOIC, PDIP for the UCC3960 and 14-pin SOIC, PDIP for the UCC3961Suggested resale price starts at $1.18 each in quantities of 1,000 for the UCC3960 and $1.28 each for the UCC3961

Vin

out

CSVS

RT FB out

startUVS/OVS

FB

Vout

f eedbackStart-upOSC

UV&OVProtection*

OptionalRegulator*

ControllogicV*S

Clamp*

VDD

+1A

*UCC3961 only

SecondarySide

controller

page 8

Buck DC-DC Regulator: LM1575/LM1575HV/LM2575/LM2575HV SeriesSIMPLE SWITCHER 1A Step-Down Voltage Regulator (National Semiconductor)

Features3.3V, 5V, 12V, 15V, and adjustable output versionsAdjustable version output voltage range,23V to 37V (57V for HV version) 4% max over line and load conditionsGuaranteed 1A output currentWide input voltage range, 40V up to 60V for HV versionRequires only 4 external components52 kHz fixed frequency internal oscillatorTTL shutdown capability, low power standby modeHigh efficiencyUses readily available standard inductorsThermal shutdown and current limit protectionP+ Product Enhancement tested

ApplicationsSimple high-efficiency step-down (buck) regulatorEfficient pre-regulator for linear regulatorsOn-card switching regulatorsPositive to negative converter (Buck-Boost)

Gnd 4-feedback3-ground2-output1-VIN

/OFFON5

7V-40V (60V)Unregulated

DC input 1

3 52

4L1

D1IN5819

GND

+5VRegulatedOutput1 A load

feedback

/OFFONH330

output

INV+

F100INC

F330outC

+ +

LM2575/LM2575HV

5.0



page 9

Functional Description of the Buck Regulator

LM1575

For adjustable version

R1 = open, R2 = 0

1.7k3.1k

8.84k11.3k

3.3V5.0V12V15V

R2

()Output

Voltage version

+

+

+

Latch

Reset52 kHzoscillator

1.235VBand-gapreference

Thermalshutdown

3.1V internalregulator1

4

R2

R11.0k

Fixed gainError amplifier Comparator

FreqShift18kHz

feedback

UnregulatedDC input

Currentlimit

Driver

Cout3

21.0Ampswitch

output

Gan D1

L1

Load

Regulatoroutput

Vout

5

+Vin

Cin+

+

+

/OFFON/OFFON

page 10

Switching Regulator: Analog or Digital Control IC?

+

PWMControl IC

L

C

np

vgn

Vbat vsw(t)

vL(t)

iL(t) Iload

vo(t)

iC(t)+ + +

Vref

vgp

Main switchSynchronous rectifier

drivers

Bandgapreference

p

n

td1 td2dead times



page 11

2. Digital PWM Control IC



A New Frontier!

page 12

Advantages of Using Digital Control Schemes

Low sensitivity to process and parameter variationsProgrammability

Improved Flexibility / Reduced Design Time Elimination Of Discrete Component Tuning Self Calibration for Accuracy

Improved FlexibilityImproved System ReliabilityConfigurabilityReduction or elimination of passive components for tuningEase of integration with digital systemsEase of implementing multi-phase converters Ability To Implement Advanced Control TechniquesSystematic design software to shorten development time



page 13

Programmability ProgrammabilityElimination Of Discrete Component Tuning

Loop Coefficient Readjustment Compensation Filter is Digital Frequency Response is set by Coefficients stored in Memory

Digital PID Compensator No fixed, externalcompensation componentslike analog

Analog equivalent

Vout VrefVrefTo PWM

+

DigitalERR

To digitalPWM

Z-1

Z-1

+

+

++

+

+

iK

pK

dK

page 14

Improved Flexibility

Eases Ability to Connect Multiple Controllers and Power Stages

Easier System Integration Communication Bus Eases Layout & Routing



page 15


DigitalPWM

Control IC

LOAD

+ +

)(sd )(siL

C

Cr

LLr

dcV oV

)(sVo

)(sio

)(sVdc

Characterization of a Buck Converter Modeling and Control of DC-DC ConvertersArchitecture Digital PWM Control IC Realization of a First-Order Digital Compensator VHDL Realization of the Digital Controller ModelSim Verification of the Digital-Controlled Buck Converter

page 16

Simulink Block Diagram

Linear Model of the Buck Converter

Digital Controller

R. R. Boudreaux, R. M. Nelms, and J. Y. Hung, "Simulation and modeling of a DC-DC converter controlled by an 8-bit microcontroller," IEEE APEC Conf. Rec., pp. 963 - 969, 23-27 Feb. 1997.



page 17

Digital Control IC Implementation

Anti-aliasingfilter Sample and hold

Control/DPWMgenerator

A/DconverterVout Sense

ADC

page 18

Anti-Aliasing Filter

Anti-Aliasing Filter: Required by Sampling TheoremUnity DC Gain and Minimum Phase Lag before Main Loop Cutoff requires:

High Sampling Frequency High order filter (2nd order or higher)

-0dB at 100kHz

-40dB at 1/2F samplew/2 pole filter

F sample = 10MHz

frequency

Gai

n (d

B)

0

-40

-80

-1201.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09



page 19

Digital Control IC Implementation

Source: B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, "High-frequency digital controller IC for dc/dc converters," Proc. IEEE Appl. Power Electron. Conf., vol. 1, pp. 374380, 2002.

+

L

C

c(t)

Switching power converter

vo

+

fs = 1MHz

Vg

Vsense

HybridDPWM

Compensator(look-up table)

Delay-lineA/D

d e

VrefDigital Control IC

OUT SENSE

Externalmemory

Simple, small-area, low-power, all-digital standard-cell ASIC

Programmable compensator

1 MHZ switching frequency

page 20

A Prototype of Digital PWM Control Chip

1 MHz digital PWM controller IC0.5 CMOS technologyArea: 0.96 mm284 pins, only 4 essential: SENSE, OUT, VDD, GNDStandard digital design flow:

HDL (Verilog) based designSynthesis to standard-cell gatesAutomated place & route

Source: B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, "High-frequency digital controller IC for dc/dc converters," Proc. IEEE Appl. Power Electron. Conf., vol. 1, pp. 374380, 2002.



page 21

Chip Architecture

Vq

VoVref

(Vo)max

e+4+3+2+10

1234

Vref

Vsense

SENSE

A/D converter

Look-up table programming interface

Programmable compensatorSystem clock

Digital pulse-width modulator

OUT

DPWM

External memory

Table A

Table B

Table C

Ts

TsTs

e[n]

e[n1]

e[n2]

d[n]

d[n+1]+

c(t) TsdTs ss Tf /1=

page 22

ADC Requirements

Vq

VoVref

(Vo)max

e+4+3+2+1

01234

Only a few digital error output needed

Static voltage regulation Vq Vo

Dynamic voltage regulation small conversion range



page 23

Types of A/D Converter

DELAY-LINE CONVERTER

FEEDBACK-TYPE CONVERTER

DUAL-SLOPE CONVERTER

PARALLEL (FLASH) CONVERTER

CHARGE-REDISTRIBUTION CONVERTER

page 24

Delay-line A/D

Analog input is the supply voltage VD for a chain of logic gates

Digital output q(in thermometer code)

Digital output e

SENSE

sample

test

R

D Q

VDD

t1

R

D Q

VDD

t2

R

D Q

VDD

t3

D Q

t8

R

VDDdelaycell

Analog input Vsense

R

VDD

q1 q2 q3 q8

Encoder

Digital output e

Delay td versus VDD

1200

1000

800

600

400

200

00 1 2 3 4 5

VDD

t d(ps

)



page 25

Delay-line A/D Operation

Stateconversion

Endconversion

q = {11111100}e = 2

sample

test

t1t2

t3t4

t5t6

t7t8

td

s

11111100

page 26

Features of Deal-Line A/D Converter

Small chip area, inherent averaging of analog inputDelay blocks constructed with standard cellsMatched strobe delay added to provide self-calibrated reference point

Experimental characteristics over temperature



page 27

Delay-line A/D Experimental Results

nconsumptiocurrent A 10sampling MHz 1

6.3 ,53tionimplementa digital-All

=

==

s

q

fmVmVVVq

Vsense

Error e+4

+3

+2

+1

0

1

2

3

4

Zero-error bin

Vref 0.2 V VrefVref 0.1 V Vref + 0.1 V Vref + 0.2 V

page 28

Digital PID Controller

+

rn end t( )

y t( )K zi ( )11

Kp

+

+

++

K zd ( )11

unZOH G sp ( )

ynT

u n K e n K T e iKT

e n e nP Ii

nD( ) ( ) ( ) [ ( ) ( )]= + +

=

11

u n K e n K T e i KT

e n e nP ID

si

n( ) ( ) ( ) [ ( ) ( )] = + +

=

1 1 1 21

1

)]2()1(2)([)( )]1()([)1()( ++++= neneneTK

neTKneneKnunus

DsIP

The velocity form or incremental form of this digital PID control algorithm can be derived as following:

[Position form]



page 29

Digital PI Controller with Anti-Windup

mu

0

1)(tw

ue u

e

+

mu

1

1

1

zz

TK

D

I

PK

+

0 0

)(te

1t 0t

mu

u

t 0 1t 0t

mu

u

t0t

t

page 30

Look-up Table Based Programmable Compensator

PID compensator: d[n+1] = d[n] + a e[n] + b e[n-1] + c e[n-1]

Table A Table B Table C

Table A

Table B

Table C

Ts

TsTs

e[n1]

e[n2]

d[n]

d[n+1]+

Duty-cycleto

DPWM

Programmable compensator

External memory

ErrorfromA/D

e[n]

8-bit



page 31

PID Regulator based on Look-up Tables

Source: A. Prodic and D. Maksimovic, "Design of a digital PID regulator based on look-up tables for control of high-frequency DC-DC converters," IEEE Workshop on Computers in Power Electronics, pp. 18-22, June 2002.

ToPWM

Look up tableb e(n-1)

Look up tablec e(n-2)

+d[n]

d[n-1]

+Look up table

a e(n) e[n]

e[n-1]

e[n-2]

FromA/D

+

page 32

High-Resolution Hybrid DPWM

Combines a delay line (ring oscillator) with a counter to reduce the maximum clock speed

Conventional DPWM:

Hybird DPWM:

Prototype:

sn

clk ff = 2

sn

clks fff = 2

MHz 8MHz 1bits 8

==

=

clk

s

ffn

+VDD

Q0 Q1 Q2 Q3

0 1 2 3

RD Q

RD Q

RD Q

RD Q

d[3:2]

d[1:0]

inputd[3:0]

nd

nc

n

nc

Rsect

Set

R

S

Qc(t)

OUT

Systemclock2-bit

counter+1 out[1:0]

cnt[1:0]

MUX 1:2 dnnc-bit

Comparator 1(a ?=b)

nc-bitComparator 2

(a ?=b)

a[1:0]b[1:0]

a[1:0]b[1:0]

out(a=b)

out(a=b)

cnt[1:0]

nc



page 33

DPWM Experimental Results

0 32 64 96 128 160 192 224 255

100

90

80

70

60

50

40

30

20

10

0

Output duty ratio [%]

DPWM input (decimal)

page 34

A Digitally Controlled Buck Converter

L = 1 H, C = 22 F

4 V < Vg < 6 V

Vo = 2.7 V +/- 25 mV

0 < Io < 1.5 A

fs = 1 MHz

+

L

C

c(t)

Switching power converter

vo

+

fs = 1MHz

Vg

Vsense

HybridDPWM

Compensator(look-up table)

Delay-lineA/D

d e

VrefDigital controller IC

OUT SENSE

Externalmemory



page 35

Experimental Results

Load Transient Responses

page 36

Predictive Digital Current Mode Control

Objective: compute d[n] so that i[n] = ic (dead-beat control)Three possible control objectives: peak current, valley current or average current

+ vin

+

g(t)

i(t)L

A/D

vo

+

A/D

Ts

DPWMPredictive

DigitalCurrent-mode

controlleric

i[n-1]

d[n]

d[n-1]

Power-stagevoltage(s)



page 37

Types of current-mode control and their stability regions

Source: Bob Erickson, Advancing Digital Control of Switched-Mode Converters, 2004.

The same control law holds for the inherently stable control/PWM combinationsThis form of control law is appropriate for digital realization

Vvini

VTLndnd inc

s

2)]1[(]1[2][ =

StableStableD0.5StableTrailing triangle

D0.5StableTrailing

AveragePeakValley

page 38

Digital Deadbeat Current Control Scheme

A/D A/D A/D

+

+

Switching power converter vo(t)+

vin load

DPWM

Analog/digitalinterface

vo(t)vin(t) ig(t) d(t)

Computation unit

vin[n] ig[n] d[n] vo[n]

Deadbeat controller

iref[n] vo[n]Vref[n]

ev[n]Voltage loop regulator

ADMC401

])1[][(]1[][

+=

necnebKnuanu

vv

vvvv



page 39

Digital Current-Mode Control for DC-DC Converters

+ vg

+

C

is(t) L

ref sensesa

mpl

e

iL[n]

Current A/D

vo

+

Triangle-mod.DPWM

PredictiveDigital

Current-modecontroller

DigitalVoltage-loop reg.

andControl state mach.

A/D

Ts

Reference generatorVoltage and parameter programming

ic[n]

d[n]

d[n+1]

e[n]

CLK

Vref

page 40

Current A/D Implementation

Sensing voltage across RonConversion time: TcResolution: LSB = IqConversion range: 0-Imax

+ vg

+

C

iL(t)

L

c(t)

ref sense

sample

iL[n]

Delay-lineCurrent A/D

vo

+

sample

c(t)

nTs

Tc



page 41

Current A/D Sampling and Resolution

ON or OFF time samplingLocal signal averaging over Tc Improved noise immunity Tc can be longerResolution:

Example:Tc = 200 nstd = 0.2 nsVg = 5 VViq = 5 mV

gc

diqqon VT

tVIR =sample

c(t)

nTs

Tc

On-time sampling

OFF-time sampling

sample

c(t)

nTs

Tc

page 42

Experimental Results of the Synchronous Current Sampling



page 43

Summary: Digital Current-Mode Control

Investigations of all-digital current-mode multi-phase controller architectureStandard-cell based implementation of all key building blocksHDL-based design scales with digital technologyOpen possibilities for:

More advanced control algorithmsProgrammable features and parametersTight system integration with P loadMore advanced power management techniques including adaptive voltage scalingMore sophisticated approaches to accurate current sensing in multi-phase architecturesMasterless multi-phase architectures

page 44

3. Digital PWM IC: Future Outlook





page 45

Digital PWM IC: Future Outlook

TI positive about digital PWM IC outlookTI, which rolled out its new Fusion Digital Power solutions at the Texas-held Applied Power Electronics Conference 2005, expects to start volume producing within half a year and believes global digital PWM IC demand will reach US$335M through 2007. [DigiTimes March 8, 2005]

page 46

Available Digital PWM Control ICs

IXDP610: IXYS digital pulse width modulator, 8-bit, 390 kHz with programmable dead-time counterISL6590: Intersil digital multi-phase PWM controller for core-voltage regulation with internal 8-bit digital PID controller. ISL6580: Intersil digital PWM generator with internal 6-bit A/D converter. UCD8220: TI Digitally Controlled Push-Pull PWM Controllers



page 47

IXDP 610 [IXYS] Bus Compatible Digital PWM Controller

FeaturesMicrocomputer bus compatibleTwo complementary outputs for direct control of a switching power bridgeDynamically programmable pulse width ranges from 0 to 100 %Two modes of operation: 7-bit or 8-bit resolutionSwitching frequency range up to 390 kHzProgrammable Dead-time Counter prevents switching overlapCycle-by-Cycle disable input to protect against over-current, overtemperature, etc.Outputs may be disabled under software controlSpecial locking bit prevents damage to the stage in the event of a software failure18-pin slim DIP package

D0D1D2D3D4D5D6D7GND

123456789

181716151413121110

CSWRRST

ODISSEL

CLKVccOUT1OUT2

IXYSIXDP610PI

Year: 2001

page 48

IXDP 610 [IXYS] Functional Block Diagram

Pulsewidthlatch

Pulsewidth

counter

comparatorDeadtimelogic

Outputdisable

logic

Frequencydivider

Controllatch

Latchselectlogic

OUT1

Deadtime

counter

OUT2

DTLE

stop

DIV

lock

DT0-DT2

7/8

D0-D7

LE

CLK

SEL

8

8

WRCS

RST

ODIS

8



page 49

Application of IXDP610 to Full Bridge DC Servo Motor Drive

PWM Cycle Time and Dead-Time

out1

out2

tDT tDT

tPWtcycl

TTLclock

8051 IXDP610

XTAL2XTAL1 P0.D (D0)

P0.7 (D7)through

P1.7

P2.7(A15)P2.0(A8)

CLKD0ThroughD7

OUT1

OUT2

topowerbridge

frompowerbridge

11.059 MHz

RSTWRCS

)WR( P3.6

SEL ODIS

+V

CLK

SEL

DATA OUT1

OUT2

OverCurrentref

IXDP610

Mic

ropr

oces

sor

orm

icro

cont

rolle

r

RST

WR

CS

ODIS

page 50

UCD8620: Digitally Controlled Push-Pull PWM Controllers

FeaturesFor Digitally Assisted Power Supplies Using The UCD8220 and UCD8620 are members of the Microcontrollers and DSPsVoltage Mode Control or Peak Current Mode Control with Cycle-by-Cycle Current LimitingProgrammable Internal Slope CompensationProgrammable On-the-Fly Current Sense Threshold System using UCD8K devices close the PWM feedback loop in the traditional analog domain but the UCD8K controllers include circuitry to interpret a time-domain digital pulse train from a digital supervisor.



page 51

Digital Pulse Train Timing Diagram and UCD8K Operation

page 52

UCD 8620 Push-Pull Application CircuitUCD8620: Digitally Controlled Push-Pull PWM Controllers

36V-75Vinput

CS

FB

MSP430F1232Controller

orEquivalent

2

3

4

5

6

7

8

15

14

13

12

11

10

9

16UCD8620

CLK

3V3

ISET

AGND

CTRL

CLF

ILIM

VIN

N/C

VDD

PVDD

OUT1

OUT2

CS

PGND

output

CS

3V3

Biaswinding

FBE/A

Communication(Programming & status reporting)

MSP430F1232: 16-bit Ultra-Low-Power Microcontroller, 8kB Flash, 256B RAM, 10 bit ADC, 1 USART

Biaswinding

Rth



page 53

UCD 8620 Half-Bridge Application Circuit

36V-75Vinput

CS

FB

MSP430F1232or

EquivalentController

2

7

4

5

3

8

6

12

11

9

14

13

10

16UCD8620PWP

CLK

CLF

ISET

AGND

3V3

ILIM

CTRL

VIN

OUT1

OUT2

CS

VDD

PGND

PVDD

output

CS

3V3

FB

E/A

Communication(Programming & status reporting)

MSP430F1232: 16-bit Ultra-Low-Power Microcontroller, 8kB Flash, 256B RAM, 10 bit ADC, 1 USART

Rth

Vcin_mid

CSXFMR

Biaswinding

Gate driveTransformer(3-winding)

Vcin_mid

page 54

PWM IC Manufacturers

National Semiconductors: http://www.national.com/Unitrode/Texas Instruments http://www.unitrode.com/Motorola/On Semiconductor http://www.onsemi.com/Power Integrations http://www.powerint.com/Maxim http://www.maxim.com/



page 55

4. Digital Control Loop Design



page 56

Digital Control Loop Design

Control Loop: From Analog to DigitalDirect and Indirect Design MethodsSampling Frequency SelectionBilinear Transformation and Prewarping



page 57

Direct and Indirect Design Flows in Control Systems

Analogdesign and analysis

(Bode, root locus, )

Analysis

DSPimplementation

Digitaldesign and analysis

(Bode, root locus, )

DSPimplementation

Indirect Direct

Analogdomain

Digitaldomain

Transformation

page 58

Digital Controller Design Procedure

Analog Design, Digital Implementation

Digital Design, Digital Implementation

G s G s G zP c c( ) ( ) ( )

G s G z G zP P c( ) ( ) ( )

zero-order-holder

Bilinear transform with prewarping

(usually used in Classical Control)

(Usually used in Modern Control) In either case, we need to transform a continuous transfer function G(s) to a discrete transfer function G(z).



page 59

Analog Design, Digital Implementation

+

ADC DigitalController PLANT

CLOCK

r t( ) e t( ) u k( ) u t( ) y t( )e k( )DAC + ZOH

+

AnalogController PLANT

r t( ) e t( ) u t( ) y t( )

(a) An Analog Control System

(b) A Digital Control System

page 60

Digital Design, Digital Implementation

+

ADCDigital

Controller PLANT

CLOCK

DISCRETIZED PLANT

)(kr u k( ) u t( ) y t( )e k( )DAC + ZOH

)(ky



page 61

Control System Using an ADC Followed by a ZOH

H z( )1

DAC+

ZOHPLANT

H(s)ADC

page 62

Operation of a Zero Order Hold (ZOH)

ZERO ORDERHOLD

Ts

1 (t)

Ts

1( )t Ts

+



page 63

Operation of ADC, DAC, and ZOH

ADC

Ts

Sampling period

DAC ZOH+

ZOH

page 64

Convert a Continuous System to a Discrete System

T i

input

t

t

output

t

u(t)

)(' zHu(t)

DAC)(' tx'ix

)(' tx

x(t)

iu

iu



page 65

Sampling: Time Domain

Many signals originate as continuous-time signals, e.g. conventional music or voice.By sampling a continuous-time signal at isolated, equally-spaced points in time, we obtain a sequence of numbers

k {, -2, -1, 0, 1, 2,}Ts is the sampling period.

[ ] ( )sTksks =

( ) ( ) ( )

=

=k (t)

s

ks

ssampled

sT

TktTksts43421321

trainimpulse][

s(t)

t

Ts

Sampled analog waveform

page 66

Sampling: Frequency Domain

Sampling replicates spectrum of continuous-time signal at integer multiples of sampling frequencyFourier series of impulse train where s = 2 fs

( ) ( ) ) (2cos2 ) (cos2 1 1 )( L+++==

=

ttT

Tktt sssk

sTs

+++== ) (2cos)(2 ) (cos)(2 )( 1 )( )()(

2cosby Modulationcosby Modulation

L44 344 2144 344 21

t)(

s

t)(

ss

T

ss

sttfttftf

Tttftg

F()

G()

s 2s2s s2fmax-2fmax

maxmaxmax 2222 if only and if gap fffff ss ><



page 67

Shannon Sampling Theorem: Nyquist Frequency

A continuous-time signal x(t) with frequencies no higher than fmax can be reconstructed from its samples x[k] = x(kTs)if the samples are taken at a rate fs which is greater than 2 fmaxNyquist Rate = 2 fmax (constraint on the sampling rate)Nyquist Frequency = fs/2 (constraint on the frequency band)What happens if fs = 2 fmax?Consider a sinusoid sin(2 fmax t)

Use a sampling period of Ts = 1/fs = 1/2fmaxSketch: sinusoid with zeros at t = 0, 1/2fmax, 1/fmax,

page 68

Assumptions of Sampling Theorem

Continuous-time signal has no frequency content above the fmax

Sampling time is exactly the same between any two samples

Sequence of numbers obtained by sampling is represented in exact precision

Conversion of the sequence of numbers to continuous-time is ideal



page 69

Discretization of a Sinusoidal Signal

f fe = 8 0

f fe = 2 0

f fe = 2 0

page 70

Spectrum of the Sampled Signal

Case 1 : f f smax

0

f max f s 2 f s 3 f s

Continuous-timespectrum

Spectrum of thesampled signal

0

f max f s 2 f s 3 f sf s

Continuous-timespectrum

Overlapping (aliasing)of the spectrum (distortions!)



page 71

Frequency Response of a Zero-Order-Holder (ZOH)

( )sesG

sT

ho

= 1

The transfer function of a Zero-Order-Holder (ZOH) is

Its frequency response is

( )2

2sin

1 2T

T

TejejG Tj

Tj

ho

=

=

Magnitude response is

Phase response is

( )

=

2sin TcTjGho

( )2TjGho

=

G jhO ( )

2 s

s2

0

0

-

- 2

- 3

- 4

- 5

s

2s 3s

4s3s2s

s 4s

Ideal low-pass filtercharacteristics

( )jGho

page 72

Bilinear Transform

Given that u se s

G sc( )( )

( )=

G z G sc cs

Tzz

( ) ( )=

+ 2 1 1

1 1

It does not preserve the frequency response.

Tj

Tj

ee

Tj

+=

112

=2

2TTtan

D(j)(the continuous filter)

D(e jT )

(the discrete filter)

T

T



page 73

Prewarping Effect Due to Bilinear Transform

( )2/tan Tk

( )digital

(a

nalo

gue)

page 74

Anti-Aliasing Filter

02

02

022+ +s s

02

02

022+ +s s

In order to avoid the aliasing of the spectrum, the analog signals must be filtered prior to sampling to ensure that:

f f sm ax

soc-06：digital control of dc-dc...

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