5. dc-dc converters: topologies, modeling, and...

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5. DC-DC Converters: Topologies, Modeling, and Control

Power Electronic Systems & Chips Lab., NCTU, Taiwan

Power Electronic Systems & Chips Lab.

~

2/220

Basic Structure of a Switching Power Supply

PWM

OSC

COMP

REF

60 Hz

lineinput PFC converter

and filter

PWM Controller

Highfrequencyinverter

20-200 KHz DC

output

output rectifierand filter

LoadSource

120 Hz

Feedback Sensing and

IsolatorPFC

Controller

Input EMI filter

Output EMI filter

3/220

Why Topologies is Important in SPS Design?

Power ratings (voltage and current) are primary concerns in determination of SPS topologies Converters are classified as nonisolated and isolated converters DC-DC converters are basic of other converters Resonant and soft-switching converters are derivatives of their corresponding PWM

converters

AC/DC Battery Charger DC/DCDC/DC

DC

AC85

26

5V

PFC Controller PWM Controller

DC/DCController

SMPS AC/DC

BatteryCharger

DC/DCController

IC

DC/DC Converter

Power Conversion, Control, and Management

4/220

ac inputsupply

dc output

voltage

Transformers in SPS +

v1(t)

i1(t)+

v2(t)

i2(t)n1:n2

+

i3(t)

v3(t)

n3

Isolation Turns Ratio Provide Wide Range Output Multiple Outputs Transformer

Input rectificationand filtering

duty cyclecontrol

controlcircuitry

HighFrequency

switch

PowerTransformer

Output rectificationand filtering

Vref

mosfet orbipolar

TPWM

OSC

Signal Coupling

5/220

Objectives of Transformer

Isolation of input and output ground connections, to meet safety requirements

Extend the voltage conversion range Reduction of transformer size by incorporating high

frequency isolation transformer inside converter Minimization of current and voltage stresses when a large

step-up or step-down conversion ratio is needed use transformer turns ratio

Obtain multiple output voltages via multiple transformer secondary windings and multiple converter secondary circuits

Transformer isolation is required for all circuits operating at a dc input voltage of 60 V DC or more.

6/220

Transformers for Asymmetrical and Symmetrical Converters

Asymmetrical Converter Symmetrical Converter

2Bs

B

H

Bssymmetricalconverters

asymmetricalconverters

symmetricalconverters

forwardconverter

flybackconverter

AvailableFlux swing

A

BCDN2

N1

v1

i1

v2

i2

Ll2Ll1

Lm

A

B

C

D

7/220

Buck Derived Isolated DC-DC Converters with Synchronous Switch

Push-Pull Converter

Forward Converter Half-Bridge Converter

Full-Bridge Converter

S

L

C RSn:1

Vg

n:n

S

S1

S2n:1

S2

S1

Vg

S1

S2n:1

S2

S1

Vg

S1

S2

S1

S2

n:1

S1

S2

Vg

LC R

LC R

LC R

8/220

Buck-Boost Derived Isolated DC-DC Converter

Flyback Converter

n:1

S

Vg Lp Ls

S

R

9/220

Most Commonly Used Isolated Converters for Low-Power Applications

Flyback Converter

LOAD

Forward Converter

LOAD

An isolated dc-dc converter module (MS Kennedy Corporation)

10/220

Basic Topologies of PWM DC-DC Converters

Buck

Boost

Buck-Boost L C

D

vovi

L

C

D

vovi

vi vo

L

CD

One Inductor, One Capacitor

C,uk

L1

C2D

L2C1

L1

C2

D

L2

C1

SEPIC

Zeta L1 C2D

L2C1

SEPIC: Single-Ended Primary Inductor Converter

Two Inductors, Two Capacitors

vi

vi

vi

vo

vo

vo

11/220

Basic DC-DC Converters in CCM

Buck Converter

Boost Converter

Buck-Boost Converter

V

Buck converter

+

V

Boost converter

+

V

Buck-boost converter

0 0.2 0.4 0.6 0.8 10

0.20.40.60.8

1

M(D

)

D

0 0.2 0.4 0.6 0.8 10

M(D

)

D

0 0.2 0.4 0.6 0.8 1

-5

M(D

)

D

-4-3-2-10

+

V

Cuk converter

+

V

Sepic

0 0.2 0.4 0.6 0.8 1

-5

M(D

)

D

-4-3-2-10

0 0.2 0.4 0.6 0.8 10

M(D

)

D

12345

12345

Transform to Isolated Converters

Buck-Boost Converter

L C

D

vovi

L1

C2

D

L2

C1

vi vo

SEPIC Converter

L1

C2D

L2C1

vi vo

Cuk Converter

LOAD

Flyback Converter

Isolated SEPIC Converter

LOAD

L1 L2

V1 V2

V0

i1 i2

C1 C2

VinLOAD

Isolated Cuk Converter

13/220

Power Supply Topologies (sluw001a)

14/220

Power Supply Topologies (sluw001a)

15/220

Selection of Isolated SPS Topologies in Watts

Topologies

1 10 100 1000 10000Output power, watts

Com

plex

ity

Flyback

Resonant resetForward

Current fedPush-pull

Single transistorforward

Tow transistorforward

Half bridge

Dual interleavedForward converter

Full bridge

Phase shiftedFull bridge

Server applications

16/220

Modeling of Switching Converters



~

17/220


Why Modeling ? Classification of Modeling Techniques Modeling of Switching Power Converters State-Space Averaging Technique Transfer Functions Small-Signal Equivalent Circuit Model

18/220

Objective of Modeling

Objective of Modeling

Analysis

Simulation

DesignEfficiency

Output Impedance

Static Characteristics

19/220

Difficulties with Modeling of SPS

Nonsmooth Systems (time and state discontinuity)Nonlinearity due to operating point Concepts of existence, uniqueness, stability not clearly defined for systems with discontinuous right half-plan zero Inherent Nonlinear Dynamic Behavior! Concept of chaotic dynamics relatively new to power electronics

20/220

Working Profile of a Switching Converter

Power-on Power-off

ov

oi

Wat

ts

% C

PU

tim

e

Dell power edge 2400 (web/SQL server)

21/220

Operating Region State-Variable Plane

DCM

D = 1.0

0.1

0.3

0.5

0.7

0.9

CCM

80% 100%60%40% 110%90%10% 20%

Vo/Vi = 1.0

0.25

0.5

0.75

0

1.0

22/220

Operating Region Operating Point Operating Mode?

IN

OUT

VV

)(max,LB

o

II

0 0.5 1.0 1.5 2.0

0

0.25

0.50

0.75

1.0

DCM

D = 1.0

0.1

0.3

0.5

0.7

0.9

CCMCRM

VIN = constant

(min)

(max)

IN

OUT

VV

(max)

(min)

IN

OUT

VV

(max)OUTI(min)OUTI

23/220

Modeling of Switching Power Converters

Modeling of Voltage-Mode DC-DC Converters- Power Stage Modeling State-space average model (Middlebrook and C'uk 1977) Discrete time-domain model (Lee 1979) Equivalent circuit model (Chetty 1981) Unified topological model (Pietkiewicz and Tollik, 1987) PWM switch model (Voperian 1988) Injected-absorbed-current model (Kisovski 1991)

- Error Processor Modeling (Chetty 1982)- Pulsewidth Modulator Modeling Describing function model (Lee 1983) Equivalent circuit model (Bello 1981)

- Larger Signal Modeling (Vicua 1992) Modeling of Current-Mode DC-DC Converters

- Equivalent Circuit Model (Chetty 1981)- y-parameter Model (Middlebrook 1989)

24/220

Modeling Techniques

State Space Averaging Method[1] R. D. Middlebrook and S. Cuk, A general unified approach to modeling switching-converter

stages, IEEE PESC Conf. Rec., pp. 18-34, 1976.[2] S. Cuk and R. D. Middlebrook, A general unified approach to modeling switching DC-to-DC

converters in discontinuous conduction mode, IEEE PESC Conf. Rec., pp. 36-57, 1977.

Modeling of Switching Converters in DCM Operation[1] D. Maksimovic and S. Cuk, A unified analysis of PWM converters in discontinuous modes, IEEE

Trans. Power Electron., vol. 6, pp. 476490, May 1991. [2] J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, Averaged modeling of PWM

converters operating in discontinuous conduction mode, IEEE Trans. Power Electron., vol. 16, pp. 482-492, July 2001.

25/220

Modeling Techniques ..

PWM Switch Method[1] V. Vorperian, Simplified Analysis of PWM Converters Using Model of PWM Switch Part I:

Continuous Conduction Mode, IEEE Trans. on Aero. and Elec. Sys., vol. 26, no. 3, pp. 490-496, May 1990.

[2] V. Vorperian, Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: Discontinuous Conduction Mode, IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 497-505, May 1990.

Fast Analytical Techniques for Electrical and Electronic Circuits,V. Vorperian, Cambridge Press, 2004.

26/220

Modeling Techniques ..

Discrete Time-Domain Method[1] F. C. Lee, R. P. Iwens, Y. Yu, and J. E. Triner, Generalized computer-aided discrete time-domain

modeling and analysis of DC-DC converters, IEEE Trans. IECI, vol. 26, pp. 58-69, May 1979.

Equivalent Circuit Method[1] P.R.K. Chetty, Switch-Mode Power Supply Design, TAB BOOKS, Inc., 1986.

Modeling of Current-Programmed Converter[1] R. D. Middlebrook, Modeling current programmed Buck and Boost converters, IEEE Trans. on

Power Electronics, vol. 4, pp. 36-52, January 1989.

Unified Topological Method[1] Pietkiewicz, A. and D. Tollik, Unified topological modeling method of switching dc-dc converters

in duty-ratio programmed mode, IEEE Trans. on Power Electron., vol. 2, no. 3, pp. 218-226, July 1987.

Injected-Absorbed-Current Method[1] Kislovski, A. S., R. Redl, and N. O. Sokal, Dynamic Analysis of Switching-Mode DC/DC

Converters, Van Nostrand Reinhold, 1991.

27/220

Recommended Books: Modeling and Simulation

Dynamic Analysis of Switching-Mode DC/DC Converters,Andre'S. Kislovski, Richard Redl, and Nathan O. Sokal,Van Nostrand Reinhold, New York, 1991.

Complex Behavior of Switching Power Converters, Chi Kong Tse, CRC Press, 2004.

Switch-Mode Power Supply Simulation: Designing with SPICE 3Steven M. Sandler, McGraw-Hill Professional; 1 edition, Nov. 11, 2005.

Switch-Mode Power Supplies - SPICE Simulations and Practical Designs, Christophe Basso, McGraw-Hill, Feb. 1, 2008.

Modeling of DC-DC Converters

voltagereference

Pulse-widthmodulator

cv)(t sGc

refv

+ v

H

t

tsTsdT

tv

t

Complex Behavior of Switching Power Converters, Chi Kong Tse, CRC Press, 2004.

Dynamic Analysis of Switching-Mode DC/DC Converters, Andre'S. Kislovski, Richard Redl and Nathan O. Sokal, Van Nostrand Reinhold, New York, USA, 1991

SMPS Simulation with SPICE 3, Steven M. Sandler, McGraw-Hill Professional, Dec. 1, 1996.

Computer-Aided Analysis and Design of Switch-Mode Power Supplies, Yim-Shu Lee, Marcel Dekker, Inc., Feb. 23, 1993.

Switch-Mode Power Supplies -SPICE Simulations and Practical Designs, Christophe Basso, McGraw-Hill, Feb. 1, 2008. Fast Analytical Techniques for Electrical and Electronic Circuits,

V. Vorperian, Cambridge Press, 2004.

29/220

Modeling and Control of DC-DC Converters

Output voltage feedback only!

PWMModulator

LoopCompensator

vo

digital signal processor analog signal processor

vR

d

load

LR di~

Buck Converter Boost Converter

Buck/Boost Converter C,uk Converter

vi vo

L

CD

L

C

D

vovi

L C

D

vovi

L1

C2D

C1

vi vo

Switching power converters

oi

Define the Operating Point!

Define the Load Disturbance

vgosZ

sv~

sV

Define the Line

Disturbance

Define the Source Output Impedance!

Small-Signal Modeling of a Buck Converter

IN

OUT

VV

)(max,LB

o

II

0 0.5 1.0 1.5 2.0

0

0.25

0.50

0.75

1.0

DCM

D = 1.0

0.1

0.3

0.5

0.7

0.9

CCMCRM

Averaged Switch Modeling of Boundary Conduction Mode DC-to-DC ConvertersJ, Chen, R. Erickson, and D. Maksimovic, IECON 2001.

VIN = constant

V. Vorperian, "Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: Discontinuous Conduction Mode," IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 497-505, May 1990.

V. Vorperian, "Simplified Analysis of PWM Converters Using Model of PWM Switch Part I: Continuous Conduction Mode," IEEE Trans. on Aero. and Elec. Sys., vol. 26, no. 3, pp. 490-496, May 1990.

31/220

Modeling of Switching Converters in DCM Operation

IN

OUT

VV

)(max,LB

o

II

0 0.5 1.0 1.5 2.0

0

0.25

0.50

0.75

1.0

DCM

D = 1.0

0.1

0.3

0.5

0.7

0.9

CCMCRM

VIN = constant

V. Vorperian, "Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: Discontinuous Conduction Mode," IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 497-505, May 1990.

J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, Averaged modeling of PWM converters operating in discontinuous conduction mode, IEEE Trans. Power Electron., vol. 16, pp. 482-492, July 2001.

D. Maksimovic and S. Cuk, A unified analysis of PWM converters in discontinuous modes, IEEE Trans. Power Electron., vol. 6, pp. 476490, May 1991.

Systematic View of DC-DC ConvertersEfficiency

Output Impedance

Selection of Switching Frequency amd PWM Strategies

Frequency Responses

Time Responses

Current Injection Testing

33/220

PWM DC-DC Power Conversion and Regulation

CLOCK RAMP

Zi

Zf

vref

vo

vx

D

vi

T

TOND T

TON

vpvx

34/220

Signal Composition of a PWM DC-DC Converters

comparator

+

D

d

Vc

v c v c

V g

v g v g

igI g

ig

clock ramp

analogamplifier

reference

load

Vv v

modulator-power-stagesubsystem

Ii i

35/220

Frequency Spectrum

f 2f 3f fs - f fs

outputspectrum

bandpassfilter

frequency

fs + f 2fs 3fs

36/220

AC and DC Quantities in a PWM Switching DC-DC Converter

I ii i vd ioioIo

vovoVo

RLC

L

Z f

vref

v c

V vI i

CLOCK RAMP

vd

Vc

vc vc

io vo

Z i

37/220

Small-Signal Modeling of a Switching Power Converter

iIi iIi

RLC

L

error processor

Zi

Z f

vref

vc

v V vi I i

duty cyclemodulator

power stage

d D d

open

oOo iIi v V vo O o

AveragedPower Stage

vi

oid

vo

vo

The concerned transfer fucntions under small perturbations can be measured under an open loop condition.

38/220

Definition of

v to( )

t

V I VO O I, ,

ioo viv ,,i to( )

v ti( )

small signal perturbation

t

TtD on

D

d(t)

d t( )

t

IOO VIV ,, Ttd x

power switch gating waveform

xt

Tont

d

39/220

BuckBoost

Buck/Boost

Small-Signal Modeling of Voltage-Mode DC-DC Converters

Power Stage

PulseModulator

ErrorProcessor

vr

vo

vc

io

d

vi

40/220

Modeling of Single-Loop DC-DC Converters

vo

vc

io

d

vi

; ;

vv

vi

vd

o

i

o

o

o

KPWM A(s)

( , , )v f v i do i o

vi

io

d vc

vo

Zp

Gd

-A(s)

Gv

KPWM

41/220

Small Signal Transfer Functions

G s vvv

o

i d io

( ) ,

0 0

: Open-loop input-to-output

G vdd

o

v ii o

,0 0

cvdk

PWM

: Open-loop output impedance

: Control to output transfer function

: PWM modulator gain

Z vip

o

o d vi

, 0 0

A s vv

c

o

( )

KVp

PWM 1 : Compensator gain: PWM dc gain

42/220

Modeling of PWM DC-DC Converters

A dc-to-dc switching regulator incorporating a three-port duty ratioprogrammed modulator-power-stage subsystem whose transfer functions aredefined in terms of ratios of small-signal ac quantities (hats) superimposedupon large-signal dc quantities (capitals).

The spectrum of the output signal contains the switching frequency, thecontrol frequency, their respective harmonics, and sidebands.

The modeling objective is to find, as function of frequency, the loop gain andthe closed properties of the regulator.

The essential prerequisite is to find the transfer function of the three-portsubsystem of the modulator-power-stage.

43/220

Concerned Transfer Functions

Control-to-output transfer function Line-to-output transfer function (audio susceptibility) Reference-to-output transfer function Input impedance Output impedance

A voltage sourcing power supply should have a low (zero) outputimpedance, while a current sourcing power supply should have a high(infinite) output impedance.

44/220

Closed-Loop Transfer Functions

Gv,CL (Closed-loop Audio Susceptibility)

v G v G do v i d

d AK vo PWMvv

GG K A

GT

o

i

v

d

v

1 1PWM

Zp,CL (Closed-loop Output Impedance)

v Z i G do p o d

d AK vo PWMvi

ZT

o

o

p1

Loop Gain : PWMT A s K Gd ( )

vo

vc

iod

vi

; ;

vv

vi

vd

o

i

o

o

o

KPWM A(s)

( , , )v f v i do i o

vi

io

d vc

vo

Zp

Gd

-A(s)

Gv

KPWM

45/220

State-Space Averaging Technique



~

46/220

State-Space Averaging Techniques

State Space Averaging Modeling Static Analysis Small-Signal Model at CCM Small-Signal Model at DCM Frequency Response Analysis

47/220

Concept of Time Averaging (Low Frequency Response Behavior)

I ii i v d ioioIo

v ov oV o

RLC

L

Z i

Z f

v ref

v c

V vI i

CLOCK RAMP

v d

V c

vc v c

io

v o

48/220

Linear Approximation of State Space Trajectories

x( )0

x( )dTs

x ( )Ts

x A x B u

x A x B u 1 1

dT s( )Ton

( )1 d Ts( )Toff

t

x( )t

x A x B u 2 2

49/220

State-Space Averaging Method (CCM)

uExCyuBxAx

uExCyuBxAx

22

22

11

11

During

During

OFF

ON

T

T

When the circuit time constant is far greater than the switching period, the above equations can be averaged as:

x d1

averaging by using state duty ratio weighting

x d2+

Switch-ON Period Switch-OFF Period

x A x B uy C x E u

2 2

2 2

x A x B uy C x E u

1 1

1 1

50/220

State-Space Averaging Method

( ) ( )( ) ( )

x A A x B B uy C C x E E u

1 1 2 2 1 1 2 2

1 1 2 2 1 1 2 2

d d d dd d d d

x Ax Buy Cx Du

A A AB B BC C CE E E

where =

1 1 2 2

1 1 2 2

1 1 2 2

1 1 2 2

d dd dd dd d

51/220

State Averaging by Active Duty Ratios

uExCyuBxAx

uExCyuBxAx

22

22

11

11

During

During

OFF

ON

T

T

When the circuit time constant is far greater than the switching period, the above equations can be averaged as:

d1

state averaging by using duty ratio weighting

d2


x A x B uy C x E u

2 2

2 2

x A x B uy C x E u

1 1

1 1

( ) ( )( ) ( )


1 1 2 2 1 1 2 2

1 1 2 2 1 1 2 2

d d d dd d d d

x Ax Buy Cx Du


where =

1 1 2 2

1 1 2 2

1 1 2 2

1 1 2 2

d dd dd dd d

52/220

Small-Signal Perturbation at a DC Operating Point

Substitute x X x y Y y u U u

; ; ; ; d D d d D d1 1 2 2

ddt

D d D d D d D d( ) ( ) ( ) ( ) ( ) ( ) ( )X x A A X x B B U u 1 1 2 2 1 1 2 2

termnonlinear ignore

2121

2121

22112211

0 termsdc

22112211

0 termsdc

)()(

)()(

)()(

)()(

uBBxAA

UBBXAA

uBBxAA

UBBXAAxX

dd

d

DDDD

DDDDdtd

dtd

i

Note:The nonlinear dynamic system is linearized around a selected operating point!

53/220

DC Model and AC Model

DC Model

X A BU1

Y ( CA B E)U1

where

ddt

d

d

x Ax Bu F

y Cx Eu G

AC ModelA A AB B BC C CE E EF A A X B B UG C C X E E U

1 1 2 2

1 1 2 2

1 1 2 2

1 1 2 2

1 2 1 2

1 2 1 2

D DD DD DD D

( ) ( )( ) ( )

54/220

Transfer Function Matrix

)()()(

)()(

)()()()(

)()(

2

1

2221

1211 sdsGsG

sisv

sGsGsGsG

sisv

d

d

d

i

uu

uu

i

o

)()()()()()()()()( 11

sdssssdssss

du HuHFAIBuAIx

y C A B E u C A F GG u G

( ) [ ( ) ] ( ) [ ( ) ] ( )( ) ( ) ( ) ( )

s sI s sI d ss s s d su d

1 1

G C A B Eu s sI( ) ( ) 1

G C A F Gd s sI( ) ( ) 1

H I A BH I A F

u

d

s ss s d s

( ) ( )( ) ( ) ( )

1

1

55/220

Open Loop Transfer Functions

control-to-output (open-loop transfer function): v sd s

G s s so d d( )( )

( ) ( ) ( ) 1 11

1G C I A F G

line-to-output (audio susceptibility):

output impedance:

v sv s

G s s soi

u u( )( )

( ) ( ) ( ) 11 111

11G C I A B E

v si s

G s s sod

u u( )( )

( ) ( ) ( ) 12 121

12G C I A B E

56/220

Example: Buck Converter

Step 1. Draw the linear equivalent circuit for each switching state of the converter.

L

CD

Q iL io

vc

icrc

rL

R vo id

iRu1 vi u2

iiy2

y1

x1

x2

Q closed, D open

L

C

iL io

vc

icrc

rL

vi R vo

id

iRii

D closed, Q open

L

C

iL io

vc

icrc

rL

R vo

id

iRii

57/220

Select State Variables

Select the inductor current iL and capacitor voltage vL state variables.

c

L

vi

xx

2

1x

i

o

iv

yy

2

1y

Select the input dc voltage and output disturbance current as input variables.

Select the output voltage and input current as output variables.

d

i

iv

uu

2

1u

58/220

Derive Circuit Equations: State Equations

Step 2. Write the circuit equations for each equivalent circuit in a state-variable format.

L

C

iL io

vc

icrc

rL

vi R vo

id

iRiiQ-ON and D-OFF State:

v L didt

i r r C dvdt

vi L L L C c C

r Cdvdt

v i i i R

i Cdvdt

i R

i R RCdvdt

i R

Cc

C L C d

Lc

d

Lc

d

( )

( )

( )R r Cdvdt

i R v i RC c L C d

dvdt

RR r C

iR r C

v RR r C

icC

LC

CC

d

( ) ( ) ( )1

59/220

State-Space Average Modeling: State Equations

dC

CiC

CLL

C

C

CdC

CC

C

CL

C

CLLi

L

irR

RrvvrR

RirrR

Rr

virR

RrvrR

rirR

RrrivdtdiL

)()()(

dC

CiC

CLL

C

CL irR

RrL

vL

vrR

RL

irrR

RrLdt

di

1111

Replace in with R

R ri

R rv R

R ri

CL

CC

Cd( ) ( ) ( )

1C dv

dtc

CdC

CC

LC

CLLL

i virRRv

rRi

rRRrri

dtdiLv

)()(

1)(

We can obtain:

60/220


i ii L

dC

CC

CL

C

C

ddC

CC

LC

L

dCL

dCLo

irR

RrvrR

RirR

Rr

RiiCrR

RvCrR

iCrR

RRCRi

RiRiRiRiiiv

)()()(

)()(1

)(

)(

v RrR r

i RR r

v RrR r

io CC

LC

CC

Cd

( ) ( ) ( )

d

iC

C

C

LCC

C

i

o

d

i

C

C

C

C

L

CC

CL

C

C

C

L

iv

rRRr

vi

rRR

rRRr

iv

iv

rRR

C

rRRr

LLvi

rRCrRR

C

rRR

Lr

rRRr

Lvi

00

0

01

10

11

111

11

Q-OFF and D-ONState Equation

61/220


Q-OFF and D-ON State:

0 Ldidt

i r r Cdvdt

vL L L C c C

RidtdvRCRi

RidtdvCi

RiiivdtdvCr

dc

L

dc

L

dCLCc

C

)(

)(

L

C

iL io

vc

icrc

rL

R vo

id

iRii

RivRidtdvCrR dCLcC )(

dC

CC

LC

c iCrR

RvCrR

iCrR

Rdtdv

)()(1

)(

62/220


dC

CiC

CLL

C

C

CdC

CC

C

CL

C

CLL

L

irR

RrvrR

RirrR

Rr

virR

RrvrR

rirR

RrridtdiL

)()()(

dC

CiC

CLL

C

CL irR

RrL

vrR

RL

irrR

RrLdt

di

111

( )R r Cdvdt

i R v i RC c L C d

dvdt

RR r C

iR r C

v RR r C

icC

LC

CC

d

( ) ( ) ( )1

Replace in with RR r

iR r

v RR r

iC

LC

CC

d( ) ( ) ( )

1C dv

dtc

CdC

CC

LC

CLLL vi

rRRv

rRi

rRRrri

dtdiL

)()(

1)(

0We can obtain:

63/220


ii 0

dC

CC

CL

C

C

ddC

CC

LC

L

dCL

dCLo

irR

RrvrR

RirR

Rr

RiiCrR

RvCrR

iCrR

RRCRi

RiRiRiRiiiv

)()()(

)()(1

)(

)(

v RrR r

i RR r

v RrR r

io CC

LC

CC

Cd

( ) ( ) ( )

d

iC

C

C

LCC

C

i

o

d

i

C

C

C

C

L

CC

CL

C

C

C

L

iv

rRRr

vi

rRR

rRRr

iv

iv

rRR

C

rRRr

Lvi

rRCrRR

C

rRR

Lr

rRRr

Lvi

00

0

00

10

10

111

11

Q-ON and D-OFFState Equation

64/220


d

iC

C

C

LCC

C

i

o

d

i

C

C

C

C

L

CC

CL

C

C

C

L

iv

rRRr

vi

rRR

rRRr

iv

iv

rRR

C

rRRr

LLvi

rRCrRR

C

rRR

Lr

rRRr

Lvi

00

0

01

10

11

111

11

Q Conducted:

D Conducted:

d

iC

C

C

LCC

C

i

o

d

i

C

C

C

C

L

CC

CL

C

C

C

L

iv

rRRr

vi

rRR

rRRr

iv

iv

rRR

C

rRRr

Lvi

rRCrRR

C

rRR

Lr

rRRr

Lvi

00

0

00

10

10

111

11

65/220


00

0 ,01

10

11

,111

11

11

11

C

C

CC

C

C

C

C

CC

CL

C

C

rRRr

rRR

rRRr

rRR

C

rRRr

LL

rRCrRR

C

rRR

Lr

rRRr

L

EC

BA

00

0 ,00

10

10 ,

111

11

22

22

C

C

CC

C

C

C

C

CC

CL

C

C

rRRr

rRR

rRRr

rRR

C

rRRr

L

rRCrRR

C

rRR

Lr

rRRr

L

EC

BA

Q Conducted:

D Conducted:

66/220

State-Space Average Modeling: Averaging

Step 3. Average each state by using duty ratio as a weighting factor and then combine thetwo sets of equations into a single set.

x A x B uy C x E u

1 1

1 1

x A x B uy C x E u

2 2

2 2

Q : D :x d1


x d2+

( ) ( )( ) ( )


1 1 2 2 1 1 2 2

1 1 2 2 1 1 2 2

d d d dd d d d

x Ax Buy Cx Eu


where =

1 1 2 2

1 1 2 2

1 1 2 2

1 1 2 2

d dd dd dd d

67/220

State-Space Average Modeling: Perturbation

Step 4. Perturb the averaged equation set to produce DC and small signal terms and eliminatenonlinear product terms.

Substitute

into the averaged equations (in Steps 3)

x X x y Y y u U u

; ; ; ; d D d d D d1 1 2 2

( ) ( )( ) ( )


1 1 2 2 1 1 2 2

1 1 2 2 1 1 2 2

d d d dd d d d

uBuBUBUB

uBuBUBUB

xAxAXAXA

xAxAXAXA

uUBB

xXAAxX

)))(()((

)))(()(()(

222222

111111

222222

111111

2211

2211

dDdD

dDdD

dDdD

dDdD

dDdD

dDdDdtd

68/220

State-Space Average Modeling: Perturbation

ddt

D D D D

D D D D

d

d d

( ) ( ) ( )

) ( )

) ( )

) ( )

X x A A X B B U

A A x B B u

A A X B B U

A A x B B u

1 1 2 2 1 1 2 2

1 1 2 2 1 1 2 2

1 2 1 2

1 2 1 2

(

(

(

Y y C C X x

E E U uC C X E E U

C C x C C X E E U

E E u C C x E E u

( ( ) ( ))( )

( ( ) ( ))( )( ) ( )

( ) ( ) ( )

( ) ( ) ( )

1 1 2 2

1 1 2 2

1 1 2 2 1 1 2 2

1 1 2 2 1 2 1 2

1 1 2 2 1 2 1 2

D d D d

D d D dD D D D

D D d

D D d d

Perturbation of the State Equations

x1

x1Operating Point New Coordinates

1x

2x

69/220

State-Space Average Modeling: DC Analysis

DC Analysis:

Set all variational terms to zero, we can obtain

X A BU1

Y ( CA B E)U1

0 1 1 2 2 1 1 2 2

( ) ( )A A X B B UAX BU

D D D D

Y C C X E E UCX EU

( ) ( )1 1 2 2 1 1 2 2D D D D

Therefore

70/220

State-Space Average Modeling: DC Model

AX BU 0Eliminate the DC term ddt

X 0 and Y CX EU

LS

CC

LCo

CC

LC

iCC

LCL

DII

VrR

RIrRV

VrR

IrR

R

DVVrR

RIrRr

CD

)//(

10

)//(0

..

We obtain the dc model equation:

Comments:1. DC model gives DC information (steady-state behavior). 2. DC model can be used for loss estimation.

71/220

State-Space Average Modeling: AC Model

ddt

d

d

x A x B u F

y C x E u G

Neglect the nonlinear product term d d x u and

where

A A AB B BC C CE E EF A A X B B UG C C X E E U

1 1 2 2

1 1 2 2

1 1 2 2

1 1 2 2

1 2 1 2

1 2 1 2

D DD DD DD D

( ) ( )( ) ( )

dIiDi

vrR

RirRv

vrRL

irR

RCdt

vd

dLVv

LDv

rRR

Li

LrRr

dtid

CA

LLs

CC

LCo

CC

LC

C

iiC

CL

CLL

)//(

111

1//

..

We obtain the ac model (small-signal) equation:

Comments:1. AC model gives small signal information.2. AC model parameter value depends on dc operating point.

72/220

Time-to-Frequency Transform

In the following, the hat above the variables will be neglected for simplicity. The small signal(or ac term) of a variable is denoted using lower case letter. Thus, the dynamic equation of aPWM dc-dc converter can be represented as:

Step 5. Transform ac state-space model into frequency domain (Laplace transform, s-domain).

ddt

d

d

x Ax Bu F

y Cx Eu G

ddt

d

d

x Ax Bu F

y Cx Eu G

73/220

Time-to-Frequency Transform

Take Laplace transform:

s s s s d ss s s d s

x Ax Bu Fy Cx Eu G

( ) ( ) ( ) ( )( ) ( ) ( ) ( )

x I A Bu I A FH u H

( ) ( ) ( ) ( ) ( )( ) ( ) ( ) ( )

s s s s d ss s s d su d

1 1

y C I A B E u C I A F GG u G

( ) [ ( ) ] ( ) [ ( ) ] ( )( ) ( ) ( ) ( )

s s s s d ss s s d su d

1 1

G C I A B Eu s s( ) ( ) 1

G C I A F Gd s s( ) ( ) 1

H I A BH I A F

u

d

s ss s d s

( ) ( )( ) ( ) ( )

1

1

)()()()(

)()(2221

12111

sGsGsGsG

ssuu

uuu EBAICG

74/220

State-Space Average Modeling: Transfer Functions

dsGsG

iv

sGsGsGsG

iv

d

d

d

i

uu

uu

i

o

)()(

)()()()(

2

1

2221

1211

Interpretation of the transfer function matrix

Input-to-output voltage gain(audio susceptibility)

Output impedance

Input AdmittanceLoad-to-line current gain

Control-to-output voltage gain

Control-to-input current gain

75/220

State-Space Average Modeling: Transfer Functions

vo

vc

io

d

vi

; ;

vv

vi

vd

o

i

o

o

o

K PWM A(s)

iidi

ii

vi i

o

i

i

i

;

;

Loop compensator

Disturbances Results

Control action

76/220

State-Space Averaging: Time-to-Frequency Transform

LC

C

LLC

C

i

o

LC

C

LLC

Ci

o

rrRrRLCs

rRLCrRCrs

CsrDsvsv

rrRrRLCs

rRLCrRCrs

CsrVsdsv

2

2

]//[1

1)()(

]//[1

1)()(

Z s v si s

G so od dv

u

i

( ) ( )( )

( ) 00

12

77/220

State-Space Averaging: Time-to-Frequency Transform

( )( )

v sd s

V sr Cs

oi

C

o

1 2

LCsCrrRLs

CsrVsdsv

LC

Ci

o

2)(1

1)()(

CrrRLQ

LC

sQ

ss

CLo

o

oo

)(

11

1

22

Note: In most conditions, because R >>(rL + rC), the above equations can be approximated as

LCsCrrRLs

CsrVsdsv

LC

Ci

o

2)(1

1)()(

LCsCrrRLs

CsrDsvsv

LC

C

i

o

2)(1

1)()(

78/220

State-Space Average Modeling

The small signal control-to-output , and line-to-output are transferfunctions of two poles and one zero

( ) ( )

v sd s

o ( ) ( )v sv s

o

i

K s zs p s p

( )( )( )

1

1 2

with its parameters depending upon component values and operating point. p1, p2 can be complex poles or real poles. But p1, p2 and z1 all lie on LHP.

Note: The equivalent series resistance of the capacitor will introduce a LHP zero.

79/220

State-Space Averaging: Output Impedance

Output Impedance: Z s v si s

so od du

( ) ( )( )

( )

00

1c I A B du

( ) ( )

( )v si s

R

sQ

s

so

d o

1

1 1 1

2

2

s sQ

s

LCQ L

Rr r C

LCrr

Q Lr

r C

oo

oo

L C

L

C

CL

2 2

1 11

1 1 1

1 1 1

,( )

;

80/220

Modeling of Load Disturbances

L

CD

Q iL io

vc

icrc

rL

vi R vo

id

iR

81/220

Dynamic Responses for Step Load Changes

Intel: VRM (Voltage Regulator Module) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines, Nov. 2006.

Adaptive voltagepositioning offset

VOFFSET (40mV)

Nominal setpoint voltageVSET (2.0V)

Dynamic voltagetolerance, VDYN-(100mV for 2s)

Initial voltage drop is mainly due to the product

of the load current step and ESR of the capacitors.

V = I ESR.(ESL effects are ignored)

Output voltageVOUT (50mV/Div)

Steady state voltage athigh current is approximatelyVSET VOFFSET IOUT RSENSE

Output current transientstep, I = 0 to 14A(5A/Div)

m5.2 GX;-MV Sanyo F15006 ;H5.2 SENSEOUT RCL

82/220

Buck Converter with Load Current DisturbanceBlock Diagram Representation

D

Q

vi

iL iC vo

io

1sL rL

rsCC

1

1R

id

iR

83/220

Control-to-Output Transfer FunctionsDC-DC Converters in CCM Operating Mode

Buck

( )( ) ( )

v sd s

V r CssQ

so

iC

o o

11 12

CrrRLQ

LC

CLo

o

)(

11

1

vi vo

L

CD

Boost

( )( )

( )( ( ))

( )'

'v sd s

VD

r Cs sL D Rs

Qs

o i C

o o

2

2

2

1 11 1

Cr

DCr

RDL

DQ

LCD

CLo

o

1

L

C

D

vovi

Buck/Boost

L C

D

vovi ( )( )

( )( ( ))

( )'

'v sd s

VD

r Cs sDL D Rs

Qs

o i C

o o

2

2

2

1 11 1

CDr

Dr

RDL

DQ

LCD

LCo

o

))(

()(

1

2 2

84/220

Transfer Functions of Buck Converters

Transfer Function Transfer Function

( ) ( )

v sd s

V r Css

Foi

C

o

D

1

21

( ) ( )v sv s

D r Css

Foi

C

o

U

1

211

( ) ( )

( )v si s

R

sQ

s

sFo

deq

o

U

1

1 1 1

2

212

( ) ( )

i sd s

Vr

r Css

FL iL

L

o

D

1

22

( ) ( )i sv s

DR

RCss

FLi o

U

1

221

( ) ( )i si s

r Css

FLd

C

o

U

1

222

s sQ

s R r

LCQ L

Rr r C

LCrr

Q Lr

r C

oo eq L

oo

L C

L

C

CL

2 2

1 11

1 1 1

1 1 1

,

,( )

;

85/220

Transfer Functions of Boost Converters


( ) ( ) ( )

( )( )

'v sd s

VD

s s

sFo i z a

o

D

2 21

1 1

( ) ( ) 'v sv s D s

Foi o

U 1 1

211

( ) ( )

( )v sv s

R

sQ

s

sFo

ieq

o

U

1

1 1 1

2

212

( ) ( ) ( )'

i sd s

VD R

RC

sFL I

o

D

2 1 2

3 22

( ) ( ) ( )'i sv s

VD R

RCs

FLi

i

o

U

2 1

3 221

( ) ( ) 'i si s D

r Css

FLd

C

o

U 1 1 222

s sQ

s Q D LD R

r CD

D r C

DLC

DLC

Rr

Q LD R

r C

r CD R

LR r

DDD

r

oo

o LC

o

eq

C

eqC

zC

a eqL

C

2 2

1 11

2

2

2

1

1 1

1

,

;( )

; ( )

'

' ''

'

'

'

'

' '

86/220

Transfer Functions of Buck/Boost Converters


( )( ) ( )

( )( )

'v sd s

VD

s s

sFo i z a

o

D

2 21

1 1

( ) ( )

( )'

v sv s

DD

r Css

Foi

C

o

U

1

211

( ) ( )

( )v si s

R

sQ

s

sFo

deq

o

U

1

1 1 1

2

212

( ) ( ) ( )'

i sd s

VD R

RCss

FL io

D 2 221

( ) ( ) ( )'i sv s

DD R

RCss

FLi o

U

2 2211 1

( ) ( ) 'i si s D

r Css

FLd

C

o

U 1 1 222

s sQ

s

DLC

Q D LD R

rD

rD

C

r CD RDL

R rD

DD

r

Rr

Q LD R

r C

oo

oo C L

zC

a eqL

C

oeq

C

eqC

2 2

2 2

2

2

1 11

2

1

1

1 1

, ;

' '

' ' '

'

' '

'

,

( )(

( ))

( )( )

;

87/220

Summary: Buck Converters at CCM


( ) ( )

v sd s

V r Css

Foi

C

o

D

1

21

( ) ( )v sv s

D r Css

Foi

C

o

U 1 211

( ) ( )

( )v si s

R

sQ

s

sFo

deq

o

U

1

1 1 1

2

212

( ) ( )

i sd s

Vr

r Css

FL iL

L

o

D

1

22

( ) ( )i sv s

DR

RCss

FLi o

U 1 221

( ) ( )i si s

r Css

FLd

C

o

U

1

222

L

CD

Q iL io

vc

icrc

rL

vi R vo

idiR

L

C

iL io

vc

icrc

rL

vi R vo

idiRii

L

C

iL io

vc

icrc

rL

R vo

idiR

ii

x d1


x d2


x A x B uy C x E u

2 2

2 2

x A x B uy C x E u

1 1

1 1

x Ax Buy Cx Du


where =

1 1 2 2

1 1 2 2

1 1 2 2

1 1 2 2

d dd dd dd d

D ONQ ON

88/220

PWM Switch Model



~

89/220

PWM Switch Model

Introduction PWM Switch and its Invariant Properties CCM Analysis

DC and Small-Signal Model of PWM SwitchPWM Switch Model of Buck ConvertersPWM Switch Model of Boost ConvertersPWM Switch Model of Buck/Boost ConvertersPWM Switch Model of Cuk ConvertersAnalysis of PWM ConvertersRight-half Plane Zero of the ConvertersPWM Switch Model Including Storage-Time Modulation

DCM AnalysisDC and Small Model of PWM SwitchAnalysis of PWM ConvertersZero of Control-to-Output Transfer Function in DCM

90/220

Pulse-Width Modulator

For natural sampling,

v c

vp

d ts ( )

vpD T

Tvv

ON

S

c

p

( ) ( )d s K v sm c

Kvm p

1 constant

91/220

PWM Switch Model

( )i ta

( )v tcp

cd

1-d

p

( )v tap

a)(~ tic

(common)

(passive)

(active)

Instantaneous value

PWM Switch Modeling[1] V. Vorperian, Simplified Analysis of PWM Converters Using Model of PWM Switch Part I: Continuous

Conduction Mode, IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 490-496, May 1990.[2] V. Vorperian, Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: Discontinuous

Conduction Mode, IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 497-505, May 1990.[3] E. Van Dijk, J. N. Spruijt, D. M. O'Sullivan, and J. B. Klaassens, PWM-switch modeling of DC-DC converters,

IEEE Transactions on Power Electronics,, vol. 10, no. 6, pp. 659 -665, Nov 1995.

92/220

Modeling of the Switch

( )i ta )(~ tic

( )v tap ( )v tcp

vcp

vap

i Dia c

v Dvcp ap

)(~ of valueaverage thedenotes :Note tii aa

During a PWM switching interval:

ss

sea TtDT

DTttiti

,00),(~

)(~

ss

sapcp TtDT

DTttvtv

,00),(~

)(~

93/220

Small-Signal Perturbation

ccccaa

ccaa

ca

idiDdIDIiI

iIdDiI

dii

))((

v dv

V v D d V v

V v DV V d Dv dv

cp ap

cp cp ap ap

cp cp ap ap ap ap

( )( )

v V vv V v

cp cp cp

ap ap ap

Make a small-signal perturbation at a DC operating point

i I ii I ia a a

c c c

d D d

i Dia c

v Dvcp ap

We can obtain

94/220

DC and AC Analysis

For dc analysis, eliminate all small signal perturbation terms, we can get itsequivalent dc model.

I DIV DV

a c

cp ap

For ac analysis, set all dc terms to zero and neglect second order nonlinear terms, we can get its equivalent small-signal ac model.

cca iDdIi

v V d Dvcp ap ap

95/220

PWM Switch Model

DC Model:

apcp

ca

DVVDII

a c

p

1 D

I a Ic

Vap Vcp

AC Model:

dVvDv

dIiDi

apapcp

cca

VD

dap

a c

p

1 DI dc

ai ciciD

96/220

DC Analysis of a Buck Converter

DC Analysis

rL

rCR

L

C

a

p

c

Li

o

rRRD

VV

p

a c

1Vi Vo

DR

rL

97/220

AC Analysis of a Buck Converter

Note:In the following, the hat above the small signal variables are neglected for simplicity.

Small-signal equivalent circuit model of the buck converter.

voRrC

C

rLL iL io

vc

ic

id

iR

I dc

dDVi

p

1iv

Dii

aia

cic

ii

Vi

iS

iDvoR

rC

C

rLL iL io

vc

ic

id

iR

98/220

AC Analysis: Control-to-Output Transfer Function

Short the unrelated voltage source and open the unrelated current source

voRrC

C

rLL iL io

vc

iR

VD

dap

p

a c

1 Dii ic

'

99/220

AC Analysis: Control-to-Output Transfer Function

v VD

d D

v v R r sCr sL R r sC

V d R sr Cs R r LC s r r C r RC L r RC R r

cpi

o cpC

L C

iC

C L C L C L

/ /( / )( ) / /( / )

( )( ) ( ) ( )

11

12

G s v sd s

V R sr Cs RLC s r r C L r RC r RC R rd

oi

C

L C L C L

( ) ( )( )

( )( ) ( )

1

2

if rL

101/220

AC Analysis: Line-to-Output Transfer Function

)()()()1(

)1()1)(()1(

)/1()/1)(()/1(

/1)/1()(

/1)/1(

)/1//()()/1//(

2LCLCLC

Ci

CCL

Ci

CCL

Ci

C

CL

C

C

iCL

Ccpo

icp

rRRCrLRCrCrrsLCrRsCsrRDv

CsrRCsrsRCsLrCsrRDv

sCrRsCrRsLrsCrRDv

sCrRsCrRsLr

sCrRsCrR

DvsCrRsLr

sCrRvv

Dvv

G s v sv s

D R sr Cs RLC s r r C L r RC r RC R rv

o

i

C

L C L C L

( ) ( )( )

( )( ) ( )

1

2

if rL

103/220

AC Analysis: Disturbance-to-Output Transfer Function

LLLCCC

LCLC

LCC

LCLC

LCC

LC

LCC

LC

LC

C

LC

C

LC

CLC

d

o

rsLRCsrCrsrLCrsRLCsRRCsrrsLCrsrLCrsR

sLrCsrsRCRRCsrrsLCrsrLCrsR

sLrCsrsRCCsrRsLrCsrR

sLrsCrRsCrRsLrsCrR

sLrsCrR

sCrR

sLrsCrR

sCrR

sLrsCrR

sCrRsLrsCrRiv

22

2

2

))(1())(1()1())(1(

))(/1()/1())(/1(

/1)/1(

)(/1

)/1(

)//(/1

)/1()//()/1//(

vi

R s r LC s L r r C rs R r LC s L r r RC r r C R r

o

d

C L C L

C C L C L L

2

2

( )( ) ( ) ( )

104/220


if rL

105/220


LCLrr

RCss

LCr

Csrs

sisvsZ

LC

LC

d

oo 11

1

)()()(

2

2

o C LQ RC

r rL

1

o LC2 1

LrrRL

Lrr

RCLCL

rrRC

QLC

oLCoLC

o

o )(

111

111

1 2

1LC

106/220


Q LR

r r Lo C L

1 1 ( )

22

2 11)(

oo

LCop

Qss

LCLrr

RCsssZ

s s sQ

oo

2 2

111

1

1)(

11

221

2

2

2

sQ

sR

srLLCs

rr

LCr

LCr

CsrssZ

oeq

LL

CL

LCoq

R req L

11

rr LC

L

C

Q rLL

11

1

107/220


The exact output impedance is derived as:

LCRr

Rrrrr

LRCs

Rrs

LCr

Lrr

Csrs

Rr

RCrrCrr

RLsLC

Rrs

rCrrLsLCrsrRCrrRCrrLsLCrRs

rCrrLsLCrsRiv

LCLLC

C

LCLC

LLCLC

C

LCLC

LLCLCC

LCLC

d

o

1)1()(11)1(

)1(

)1()()1(

)(

)()()()(

2

2

2

2

2

2

108/220


111

1)(1)(

11

221

2

22

sQ

sR

sCrrLLCs

rr

LCr

LCr

Lrr

CsrssZ

oeq

CLL

CLLCLCoq

R req L

11

rr LC

L

C

Q Lr

r CL

C

11

1 1

109/220

Output Impedance of the Buck Converter

LCRr

Rrrrr

LRCs

Rrs

LCr

Lrr

Csrs

sisvsZ

LCLLC

C

LCLC

d

oo 1)1()(11)1(

)1(

)()()(

2

2

Z s v si s

R

sQ

s

soo

deq

o

( ) ( )( )

( )

11 1 1

2

2

Output Impedance of the Buck Converter:

s sQ

s R r

LCQ L

Rr r C

LCrr

Q Lr

r C

oo eq L

oo

L C

L

C

CL

2 2

1 11

1 1 1

1 1 1

,

,( )

;

110/220

Difficulties with Modeling and Control of SPS



~

111/220

6. Difficulties with Modeling and Control of SPS

Nonsmooth Systems (time and state discontinuity)Concepts of existence, uniqueness, stability not clearly defined for systems with discontinuous right hand sideConcept of chaotic dynamics relatively new To power electronics

112/220

Complex Behavior of Switching Power ConvertersChi Kong Tse, Complex Behavior of Switching Power Converters, CRC Press, 2004.

(c) Simulation results

(d) Experimental results

E = 22-33 V, L = 20 mH, C = 47 F, R = 22 , Vref = 11 V, A = 8.4, T = 400 s, VL = 3.8 V, VU = 8.2 V.

(a) Voltage-mode controlled buck converter.

(b) Operation waveforms.

u

VL

VU Vrampvcon

t

t3T2T1T0

113/220

Bifurcation of Voltage Mode Buck Converter in CCM

RLC

Z i

Z f

vref

v c

V vI i

CLOCK RAMP

vd

Vc

vc vc

io vo

rampv

u

VL

VUVramp

vcon

t

t3T2T1T0

Li

114/220

Vcon & Vramp at Different Gains

L = 20 mH, C = 47 F, R = 22 , T = 400 s, VL = 3.8 V, VU = 8.2 V, Vs = 33 V, Vref = 11 V.

KP = 5.0

KP = 3.0

KP = 7.0

KP = 9.0

8 msec

RL

vrefv c

vd

io vo

rampv

Li

PK

C

115/220

Phase Portraits

KP = 6.8KP = 3.0

KP = 7.4 KP = 12.0

116/220

Inductor Current and Output Voltage at Kp = 12.0

KP = 12.0Inductor Current

Output Voltage

117/220

Simulation Results with Varying Source Voltage

Source Voltage

Output Voltage

Inductor Curent

118/220

Experimental Setup for Measuring of a SPS

Active LoadDC Power Supply Buck Converter

Experimental Setup Experimental Buck Converter

119/220

Typical Waveforms

IL

VC

IL

VC

Coupling switching noise

5s

1ms

What happens?

120/220

Bifurcation Occurs in a Switching Power Supply

IL

IL

IL

IL

IL

IL

VC

VC

VC

VC

IL

VC

121/220

Intermittency, Parasitic and Common Mode Effects

IL

IL

VC

VC

Icom

122/220

Homework Assignments



~

123/220

Simulation of a Buck Converter

S. A. Shirsavar, "Teaching Practical Design of Switch-Mode Power Supplies," IEEE Trans. on Education, vol. 47, no. 4, pp. 467-473, Nov. 2004.

Vinvca

iL

LvL vo

io

C R

low-pass filteris

ic

Input voltage Vin = 12 VNominal output voltage Vout = 5 V

Switching Frequency fs = 76.5 kHzInductor L = 100 HCapacitor C = 2.4 FLoad resistor R => 25

id

124/220

Buck Converter

v VDL HrC FrRf KHz

i

L

C

s

10502000 14700 05550

%

.

.

ohm

ohm ohm

L

RvorC

C

rL

vi D

Q

iL

io

vc

iciSiD

Control-to-Output Transfer Function

( )( ) ( )

v sd s

V r CssQ

so

iC

o o

11 12

o o

L CLC

Q LR

r r C

1 1 1 ,( )

125/220

Control Loop Design



~

Voltage Mode Control of DC-DC Converters

PWMModulator

LoopCompensator

v o


vR

d


load

LR di~



vi vo

L

CD

L

C

D

vovi

L C

D

vovi

L1

C2D

C1

vi vo


oi

vgosZ

sv~

sV

127/220

Control Loop Design for DC-DC Converters

L. H. Dixon, Closing the Feedback Loop, Unitrode, 1988.

Feedback Control to Achieve: Good Voltage Regulation (Load Variation & Line Variation) High Stability (Load Variation & Line Variation)

vref

d

ve

v v f do i ( )

Fm

ConverterPower Stage

)(sA

Rvi

Single-Loop-Controlled Switching Regulator

128/220

Small Signal Modeling of Voltage Mode ControlSwitching Mode DC-DC Regulator

BuckBoost

Buck/Boost

Power Stage

PulseModulator

ErrorProcessor rv

~

ov~

cv~

oi~

d~

iv~

LoadDynamics

129/220


G s vvv

o

i d io

( ) ,

0 0


G vdd

o

v ii o

, 0 0

K dv c

PWM




Z vip

o

o d v i

, 0 0

A s vv

c

o

( )

KV p

PWM 1

: Compensator gain

: Power stage transfer function

: PWM dc gain

G Z Gv p d, ,

DC gain: DV Vc p

1

A(s) : Compensator to be designed

130/220

Small Signal Model of Voltage Mode Control

dv

iv

vv o

o

o

i

o ~~

;~~

;~~

KPWM A(s)

)~,~,~(~ divfv oio Zp

Gd

-A(s)

Gv

KPWM

)(1Z

sLZ

Z popcpo

)()()( sGKsAsL dPWM)(1

sL

GGG vovcvo

oi~

d~

iv~

oi~

d~

iv~ov~

cv~cv~

ov~

The design problem is to synthesize a loop compensator L(s) to satisfy given specifications of Gvc(s) and Zpc(s).

131/220


G s vvv

o

i d io

( ) ,

0 0


G vdd

o

v ii o

,0 0

cvdk

PWM




Z vip

o

o d vi

, 0 0

A s vv

c

o

( )

KVp

PWM 1 : Compensator gain: PWM dc gain

132/220

Control Concept for Switching Regulators

vo

vc

io

d

vi

; ;

vv

vi

vd

o

i

o

o

o

K PWM A(s)

iidi

ii

vi i

o

i

i

i

;

;

Loop compensator

Disturbances Results

Control action

133/220

Single-Loop Control Example

vovi

PWM Modulator

Zi

Zf

vref

DriverStage

Buck Converter

Power Stage

Error Amplifierand Compensation

VoltageDividerNetwork

vc

d

R

VP

134/220

Single-Loop-Controlled PWM Converter

Z i

Z f

v ref

Logic&

DRIVE

+

A

Se

vi

vo

B

FvFm

RL

Features of Voltage Mode Control: Error voltage compared to external ramp Se. Unique loop gain for control loop design Analog signal can be measured at B. Digital signal can be measured at A.

135/220


Control Architecture


~

136/220

The Purpose of Feedback Control

PWMModulator

LoopCompensator

vgvo

vR

load

RL di~

Buck Converter

Power Flow Control Efficiency & Stability & Power Quality Output Voltage Regulation Zero Output Impedance Input Voltage Disturbance Rejection Zero Audio Suspetibility Control with Estimated Feedback Signals

137/220

Control of Basic PWM DC-DC Converters

PWMModulator

LoopCompensator

vg

vo

vR

Efficiency

load

RL di~


Output Impedance

GateDrive

osZ

sv~

sV

Buck ConverterBuck-Boost ConverterBoost Converter

138/220

Multiple-Loop Control Scheme

PWMModulator

Voltage LoopCompensator

vo

vRCurrent LoopCompensator

CurrentSensing

CurrentLoop

VoltageLoop

load

RL di~Buck ConverterBuck-Boost ConverterBoost Converter

vgosZ

sv~

sV

Switching Power Converters

CarrierGenerator

139/220

Pioneer Voltage-Mode PWM Control IC SG1524

The First PWM IC: SG1524, Bob Mammano, 1976.

SG1524: -55C ~ 125CSG2524: -25C ~ 85CSG3524: 0C ~ 70C

Pioneer Current-Mode PWM Control IC uc3842

7/12

5/9

4/7

2/3

1/1

3/5

Vcc

VFB

ground

compCurrent

sense

OSC

34V

2.50V

UVLO

Vrefgoodlogic

TS2R

R 1VPWMlatch Power

ground

output

CurrentSense

comparator

Vref5.0V

50mAInternalbias

5VrefRS /

Erroramp

RT /CT

R

Vc

8/14

7/11

6/10

5/8

Block Diagram of UC3842/3/4/5

ccV

RS

Q

Latch

Clock

PWMcomparator

Erroramplifier

reference

Li

eV

sR

sV

RV

oV

RESET

LatchOutput(PWM)

Clock (SET)

Li

eV

sV

141/220

Voltage-Mode Control vs. Current-Mode Control

REF: Bob Bell, National Semiconductor, "Virtual-current mode: current-mode control without the noise," EDN, Feb. 16, 2006.

Voltage Mode Control Current Mode Control

VIN VINVOUT VOUTL1 L1

D1 D1

Q1 Q1

FET DRIVER

CLOCKSAWTOOTHGENERATOR

1.25VREFERENCE

Q RS

Q RS

CLOCK1.25V

REFERENCE

SWITCH DRIVER

SWITCH-CURRENTMEASURE

PWMCOMPARATOR

PWMCOMPARATOR

ERRORAMPLIFIER

ERRORAMP

142/220

Control Block Diagram of a Current-Mode Controller

143/220

Peak-Current-Mode-Control of a Buck Converter

144/220

Current-Mode Control vs. Voltage-Model Control

A. J. Forsyth and S. V. Mollov, "Modelling and control of DC-DC converters," IEEE Power Engineering Journal, vol. no. 5, pp. 229-236, Oct. 1998.

(a) Voltage-Mode Control (b) Current-Mode Control

145/220

Current-Mode vs. Voltage-Mode Control

Control-to-output bode plots for voltage and current mode converters. (The current mode converter has an extra 90 degrees of phase.)

146/220

Voltage Mode Control of DC-DC Converters

PWMModulator

LoopCompensator

vg vo


vR

d


load

LR di~



vi vo

L

CD

L

C

D

vovi

L C

D

vovi

L1

C2D

C1

vi vo


oi

147/220

Voltage Mode Control

REF: Voltage-mode control and compensation - Intricacies for buck regulators (Timothy Hegarty, EDN 2008)

Converter power stage

ModulatorType III compensator

PWMcomparator

Erroramp

COMP

SW

VIN

Vout

IoutRLRESRCO

LORDCR

RFB1FB

RC1CC1

CC2

RC2

RFB2

CC3

Vref

Driver&

deadtime

D

PWM rampVramp

148/220

Robert W. Erickson and Dragan Maksimovic, Fundamentals of Power Electronics, Kluwer Academic Publishers, 2nd Ed., February 2001.


Control Loop Design Basics


149/220

Control Loop Design Basics

1. Introduction2. Effect of Negative Feedback

Feedback reduces the transfer function from disturbances to the output Feedback causes the transfer function from the reference input to the

output to be insensitive to variations in the gains in the forward path ofthe loop

3. Construction of the important quantities 1/(1+T) and T/(1+T) and theclosed-loop transfer functions

4. Stability The phase margin test The relation between phase margin and closed-loop damping factor Transient response vs. damping factor

150/220

Control Loop Design Basics ..

5. Regulator design Feedback Lead (PD) compensator Lag (PI) compensator Combined (PID) compensator Design example

6. Measurement of loop gains The Voltage injection Current injection Measurement of unstable systems

7. Summary of key points

151/220


tvg tvo

tiload


Switching converter

transistor gate driver

Load

tvc t t

tsTsdT tvo

tvg

tiload td

divftv loadg ,,

disturbances

Control input

Switching converter

Output voltage of aswitching converterdepends on duty cycle d,input voltage vg, and loadcurrent iload

td

152/220

The DC Regulator Application

Objective: maintain constantoutput voltage vo(t) = V, in spiteof disturbances in vg(t) andiload(t).Typical variation in vg(t) : 100Hzor 120Hz ripple, produced byrectifier circuit.

Load current variations: a significant step-change in load current, suchas from 50% to 100% of rated value, may be applied.A typical output voltage regulation specification: 5V 0.1V.

Circuit elements are constructed to some specified tolerance. In highvolume manufacturing of converters, all output voltages must meetspecifications.

tvo tvg

tiload td

divftv loadgo ,,

disturbances

Control input

Switching converter

153/220

The DC Regulator Application

So we cannot expect to set the duty cycle to a single value, and obtain agiven constant output voltage under all conditions.

Negative feedback: build a circuit that automatically adjusts the duty cycleas necessary, to obtain the specified output voltage with high accuracy,regardless of disturbances or component tolerances.

154/220

Negative Feedback: A Switching Regulator System

gv v

tiload


Switching converter


Load

cv

Powerinput

H(s)sensorgain

error signal

compensator

sGc ev

refvreference

input

+

tvo

155/220

Negative Feedback

tvo tvg

tiload td

divftv loadgo ,,

disturbances

Control input

Switching converter


cv

error signal

sensorgain

tverefvreference

input

+ compensator

156/220


Effect of Negative Feedback


~

157/220

Effect of Negative Feedback

C tvg svo sdsj

eL

R

sdse

1 : M(D)

Small signal model: open-loop equivalent circuit mode of a buck converter

Output voltage can be expressed as

where

tiload

sisZsvsGsdsGtv loadoutgvgvdo

000

00

0

gloadload

g

vdload

oout

id

g

ovg

sisv

ovd si

svsZsvsvsG

sdsvsG

158/220

Voltage Regulator System Small-Signal Model

Use small-signal converter model

Perturb and linearize remainder of feedback loop

.

etctvvtv

tvvtv

eee

refrefref

C tvg svo sdsj

eL

R

sdse 1 : M(D)

tiload

error signal

sve svref

referenceinput

+

svc

H(s)

sGccompensator Pulse-width

modulator

sd

svsH o

sensorgain

MV1

159/220

H(s)

Regulator System Small-Signal Block Diagram

error signal

sve svref

referenceinput

svc sGc

compensator Pulse-widthmodulator

svsH o

Sensor gain

MV1 sd sGvd

sGvd svgac line variation

svo

tiloadload current variation

output voltagevariation

duty cyclevariation


sZout

Mvdc

outload

Mvdc

vdg

Mvdc

Mvdcrefo VGHG

ZiVGHG

GvVGHG

VGGvv/1

/1

/1

/

160/220

Solution of Block Diagram

Manipulate block diagram to solve for . Result is

Loop gain T(s) = products of the gains around the negative feedback loop.

which is of the form

svo

Mvdc

outload

Mvdc

vdg

Mvdc

Mvdcrefo VGHG

ZiVGHG

GvVGHG

VGGvv/1

/1

/1

/

" "/with 1

1

1

1

gainloopVsGsGsHsTT

ZiT

Gv

TT

Hvv

Mvdc

outload

vggrefo

161/220

Feedback Reduces Sensitivity to Load Disturbances

Original (open-loop) line-to-output transfer function:

With addition of negative feedback, the line-to-output transfer function becomes:

Feedback reduces the line-to-output transfer function by a factor of

If T(s) is large in magnitude, then the line-to-output transfer function becomessmall.

0 0

laodid

g

ovg sv

svsG

sTsZ

sisv out

vv

load

o

gref

1

00

sT11

162/220

Closed-loop Output Impedance

Original (open-loop) output impedance:

With addition of negative feedback, the output impedance becomes:

Feedback reduces the output impedance by a factor of

If T(s) is large in magnitude, then the output impedance is greatly reduced in magnitude.

0 0

gv

dload

oout si

svsZ

sTsZ

sisv out

vv

load

o

gref

1

00

sT11

163/220

Feedback Causes Reduction of Sensitivity

If the loop gain is large in magnitude, i.e., || T || >> 1, then (1+T) T and T/(1+T) T/T = 1. The transfer function then becomes

which is independent of the gains in the forward path of the loop.This result applies equally well to dc values:

0

101

00

1HT

THV

Vref

o

Closed-loop transfer function from to is : svrefv

sT

sTsHsv

sv

laod

giv

ref

o

1

1

00

sHsvsv

ref

o 1

Feedback causes the transfer function from the reference input to the output to be insensitive to variations in the gains in the forward path of the loop

164/220

Construction of 1/(1+T) and T/(1+T)

cf

At the crossover frequency fc, ||T || = 1

80dB

60dB

40dB

20dB

0dB

-20dB

-40dB1Hz 1KHz 10kHz100Hz 100kHz10Hz

f

-40dB/dec

-20dB/dec

-40dB/dec

zf

2pf

1pf

dB0T dBQ

2

2

11

0

11

1

ppp

z

s

s

Qs

s

TsT

crossoverfrequency

T

Example

165/220

Approximating 1/(1+T) and T/(1+T)

1for

1for 11 TT

TT

T

1for 1

1for 1

11

T

TsT

sT

166/220

Construction of T/(1+T)

cf

80dB

60dB

40dB

20dB

0dB

-20dB

-40dB1Hz 1KHz 10kHz100Hz 100kHz10Hz

f

-40dB/dec

-20dB/deczf

2pf

1pf T

crossoverfrequency

1for

1for 11 TT

TT

T

TT1

167/220

Derive Reference to Output Transfer Function

This is the desired behavior: the output follows the reference according to the idealgain 1/H(s) . The feedback loop works well at frequencies where the loop gain T(s)has large magnitude.At frequencies above the crossover frequency, || T ||

169/220

Interpretation: How the Loop Gain Rejects Disturbances?

1for 1

1for 1

11

T

TsT

sT

Bellow the crossover frequency: f < fc and || T || > 1Then 1/(1+T) 1/T, and disturbances are reduced in magnitude by 1/ || T ||

Above the crossover frequency: f < fc and || T || < 1Then 1/(1+T) 1, and the feedback loop has essentially no effect ondisturbances

170/220

Terminology: Open-loop vs. Closed-loop

Upon introduction of feedback, these transfer functions become (closed-looptransfer functions):

The loop gain:

Original transfer functions, before introduction of feedback (open-loop transferfunctions):

sZsGsG outvgvd

sTsZ

sTsG

sTsT

sHoutvg

1

1

11

sT

171/220

Stability

Even though the original open-loop system is stable, the closed-loop transfer functionscan be unstable and contain right half-plane poles. Even when the closed-loop system isstable, the transient response can exhibit undesirable ringing and overshoot, due to thehigh Q -factor of the closed-loop poles in the vicinity of the crossover frequency.When feedback destabilizes the system, the denominator (1+T(s)) terms in the closed-loop transfer functions contain roots in the right half-plane (i.e., with positive realparts). If T(s) is a rational fraction of the form N(s) / D(s), where N(s) and D(s) arepolynomials, then we can write

sDsN

sD

sDsNsT

sDsNsN

sDsN

sDsN

sTsT

1

11

1

11

Could evaluate stability by evaluatingN(s) + D(s), then factoring to evaluateroots. This is a lot of work, and is notvery illuminating.

172/220

Nyquist stability theorem: general result. A special case of the Nyquist stability theorem: the phase margin

test

Allows determination of closed-loop stability (i.e., whether 1/(1+T(s)) containsRHP poles) directly from the magnitude and phase of T(s).

A good design tool: yields insight into how T(s) should be shaped, to obtaingood performance in transfer functions containing 1/(1+T(s)) terms.

Determination of Stability Directly from T(s)

173/220

The Phase Margin Test

If there is exactly one crossover frequency, and if T(s) contains no RHP poles, then

A test on T(s), to determine whether 1/(1+T(s)) contains RHP poles. The crossoverfrequency fc is defined as the frequency where

dB012 cfjTThe phase margin m is determined from the phase of T(s) at fc, as follows:

cm fjT 2180

the quantities T(s) / (1+T(s)) and 1/(1+T(s)) contain no RHP poles wheneverthe phase margin jm is positive.

174/220

Example: a loop gain leading to a stable closed-loop system

68112180

1122

m

c

fjT

60dB

40dB

20dB

0dB

-20dB

-40dB

1Hz 1KHz 10kHz100Hz 100kHz10Hz

cfzf

1pf crossoverfrequency

T

T TT

m

0

-90

-180

-270

f

175/220

Example: a loop gain leading to an unstable closed-loop system

502301802302

m

c

fjT

60dB

40dB

20dB

0dB

-20dB

-40dB


cfzf

1pf crossoverfrequency

T

T TT

0m

0

-90

-180

-270

f

176/220

Relation Between Phase Margin and Closed-loop Damping Factor

A small positive phase margin leads to a stable closed-loop systemhaving complex poles near the crossover frequency with high Q. Thetransient response exhibits overshoot and ringing.

Increasing the phase margin reduces the Q. Obtaining real poles, withno overshoot and ringing, requires a large phase margin.

The relation between phase margin and closed-loop Q is quantified inthis section.

How much phase margin is required?

177/220

A Simple Second-order System

f

40dB

20dB

0dB

-20dB

-40dB

2f

0f

T

TTT

m

0

-90

-180

-270

-90-40dB/dec

-20dB/dec

10/2f

210 f

2f

ff0

220

fff

Consider the case where T(s) can be well-approximated in the vicinity of thecrossover frequency as

20

1

1

s

s

sT

178/220

Closed-Loop Response

if

Then

20

1

1

s

s

sT

20

2

0

1

111

11

s

s

sTsT

sT

or,

2

1

11

cc s

QssT

sT

where2

002 2

Qf

cccc

179/220

Low-Q case

202

00

Q :ionapproximat -low QQ

Q cc

c

f

40dB

20dB

0dB

-20dB

-40dB

2f

0f

T

-40dB/dec

-20dB/dec

ff0

220

fff

20 fffc

20 / ffQ T

T1

180/220

High-Q case

2

0

c

020 2

Q fQ c

f

40dB

20dB

0dB

-20dB

-40dB

2f

0f

T

-40dB/dec

-20dB/dec

ff0

220

fff

20 fffc

cffQ /0

TT1

60dB

181/220

Q vs. m

Solve for exact crossover frequency, evaluate phase margin, express as function of m. Result is:

4

41

2411

tan

sincos

QQ

Q

m

m

m

182/220

Q vs. m

-20dB

20dB

10dB

0dB

-10dB

-15dB

-5dB

15dB

5dB

Q

0 10 20 30 40 50 60 70 80 90

Q=1 0dB

Q=0.5 -6dB

m

52m

76m

183/220

Transient response vs. damping factor

Unit-step response of second-order system T(s)/(1+T(s))

22121

1

12

2

212

2

2/

4112

,

5.0 1

5.0 14tan2

14sin

1421

21

QQ

Qe

e

tv

QQtQ

QQ

Qetv

c

tt

c

Qtc

For Q>0.5, the peak value is

14/ 21peak Qetv

184/220

Transient Response vs. Damping Factor

2

0 5radianst c ,

1.5

1

0.5

010 15

tv Q=50Q=10

Q=4

Q=2

Q=1Q=0.75Q=0.5

Q=0.3

Q=0.2

Q=0.1Q=0.05Q=0.01

185/220

Typical specifications: Effect of load current variations on output voltage regulation

This is a limit on the maximum allowable output impedance Effect of input voltage variations on the output voltage regulation

This limits the maximum allowable line-to-output transfer function Transient response time

This requires a sufficiently high crossover frequency Overshoot and ringing

An adequate phase margin must be obtained

The regulator design problem: add compensator network Gc(s) tomodify T(s) such that all specifications are met.

5. Regulator Design

186/220

Lead (PD) Compensator

f

zf

0cG

cG

cG

+45/decade

10/zf

zf10

z

pc f

fG 0

pz fff max

Improves phase margin

p

zcc

s

s

GsG1

1

0

-45/decade

10/pf

0

pf

187/220

Lead Compensator: Maximum Phase Lead

ff

ff

ff

fG

fff

z

p

p

z

z

p

c

pz

sin1sin1

2tan 1max

max

0

15

30

45

60

75

90

1 10 100 1000

maximumphase lead

zp ff /

188/220

Lead (PD) Compensator

f

zf

0cG

cG

cG

+45/decade

10/zf

zf10

z

pc f

fG 0

pz fff max

-45/decade

10/pf

0

pf

To optimally obtain a compensator phase lead of at frequency fc, the pole andzero frequencies should be chosen as follows:

ff

ff

cp

cz

sin1sin1

sin1sin1

If it is desired that the magnitude of the compensator gain at fc be unity, then Gc0 should be chosen as

p

zc f

fG 0

189/220

Example: Lead Compensation

60dB

40dB

20dB

0dB

-20dB

-40dB

cfzf

pf

original gain

T

TT

T

m

0

-90

-180

-270

f

0

compensated gain

compensated phase asymptotes

original phase asymptotes

0f

0T

00 cGT

190/220

Lag (PI) Compensation

f

zf

cG

cG

cG

10/Lf

Lf10

Improves low-frequencyloop gain and regulation

s

GsG Lcc 1

+45/decade-90

-20dB/dec

0

191/220

Example: Lag Compensation

0

0

1s

TsT uu40dB

20dB

0dB

-20dB

-40dB

cf

010 fT

T

m

0

-90

-180

f

0f0uT

0uc TG


90

Original (uncompensated)loop gain is

Compensator:

s

GsG Lcc 1

Design strategy:chooseGc to obtain desiredcrossover frequencyL sufficiently low tomaintain adequate phasemargin

uT

uT

0f

Lf

Lf10

192/220

Example, Continued

Construction of 1/(1+T), lag compensator example:

40dB

20dB

0dB

-20dB

-40dB

cf

T

f

0f0uc TG


0f

Lf

Lf

0

1uc TG T1

1

193/220

Combined (PID) Compensator

40dB

20dB

0dB

-20dB

-40dB

f1Hz 1KHz 10kHz100Hz 100kHz10Hz

zfcmG

cG

cG

90/dec

10/Lf110 pf

45/dec

10/1pf-90

1pf

21

11

11

pp

Z

L

cmc

s

s

s

s

GsG

cG

cfLf

2pf

10/zf

10/2pfLf10 zf10

-90/dec

cG

0

90

-180

-90

194/220

5. An Illustrated Design Example

V28tvg tvo

loadi



cv

H(s)sensorgain

error signal

compensator

sGc ev

V5refv

referenceinput

+

F50 L

3R

F500C

V4mV

vH

100kHzsf

195/220

Quiescent Operating Point

Input voltageOutputQuiescent duty cycleReference voltageQuiescent value of control voltageGain H(s) 3/115/5/

14.25

536.028/153,5,15

28

VVHVDVV

VVD

RAIVVVV

ref

Mc

ref

load

g

196/220

Small-Signal Model

C tvg svodRV

L

R

1 : D

siload

error signal

sve 0 refv + svc

H(s)

sGccompensator

sd

svsH o

MV1

dDV

2

V4mV

31

H

sT

197/220

2

000

0

1

1

s

Qss

GsG dvd

Open-Loop Control-to-Output Transfer Function Gvd(s)

LCs

RLsD

VsGvd21

1

f

40dB

20dB

0dB

-20dB

-40dB

vdG

vdG

0

-90

-180

-270

0fStandard form:

Salient features:

dB5.195.9

kHz12

12

28

0

00

0

LCRQ

LCf

VFVGd

60dB

vdG

vdG

dBV29V280 dGdB5.199.50 G

kHz1.110 02/1 0 fQ

1Hz 1KHz 10kHz100Hz10Hz 100kHz

900Hz10 02/1 0 fQ

198/220

Open-loop line-to-output transfer function and output impedance

Same poles as control-to-output transfer function standard form:

2

000

0

1

1

s

Qss

GsG dvd

LCs

RLs

DsGvd21

1

Output impedance:

LCs

RLs

sLsLsC

RsZout21

1

199/220

System Block Diagram

sve 0 refv + svc

H(s)

sGcMV1 sd sGvd

sGvg svg

ac linevariation

sZout

+

+

svo

tiloadload current

variation

duty cyclevariation


sHsGV

sGsT vdM

c

1

V4mV

31

H

2

000

1

1

s

QsD

VV

sHsGsTM

c

200/220

dB4.733.2

1

1

0

2

000

0

Mu

uu

DVHVT

s

Qs

TsT

Uncompensated Loop Gain (with Gc=1)

f

40dB

20dB

0dB

-20dB

-40dB

uT

0

-90

-180

-270

0f

With Gc=1, the loop gain is

uT

dB4.723.20 uT dB5.199.50 Q

kHz1.110 02/1 fQ


900Hz10 02/1 fQ

uTuT

0kHz1

5 ,kHz8.1 mc f

201/220

Lead Compensator Design

Obtain a crossover frequency of 5kHz, with phase margin of 52 Tu has phase of approximately -180 at 5kHz, hence lead (PD)

compensator is needed to increase phase margin. Lead compensator should have phase of +52 at 5kHz Tu has magnitude of -20.6dB at 5kHz Lead compensator gain should have magnitude of +20.6dB at 5kHz Lead compensator pole and zero frequencies should be

kHz5.1452sin152sin1kHz5

kHz7.152sin152sin1kHz5

p

z

f

f

Compensator dc gain should be dB3.117.310

2

00

p

z

u

cc f

fTf

fG

202/220

Lead Compensator Bode Plot

f

zf0cG

cG

cG

10/zfzf10

z

pc f

fG 0

pz

c

ff

f

10/pf0

pf

40dB

20dB

0dB

-20dB

-40dB 0

-180


cG

-90

90

cG

203/220

2

000

00

11

1

s

Qs

s

s

CTsT

p

zcuLoop Gain with Lead Compensator

f

40dB

20dB

0dB

-40dB 0

-90

-180

-270

0f

T

dB7.186.80 TdB5.199.50 Q


0

T

-20dB

T

zfcf

pf

52m

170kHz

900kHz

1.4kHz

1.1kHz

17kHz

14kHz

5kHz

1.7kHz1kHz

204/220

1/(1+T) with Lead Compensator

need more low-frequency loop gainhence, add inverted zero (PID controller)

f

40dB

20dB

0dB

-40dB

0f

dB7.186.80 T dB5.199.50 Q


T

-20dB

zfcf

pfT1

1dB7.1812.0/1 0 T

0Q

205/220

Improved Compensator (PID)

p

L

Zcmc

s

s

s

GsG1

11

40dB

20dB

0dB

-20dB

-40dB

f1Hz 1KHz 10kHz100Hz10Hz

zfcmG

cG

cG

90/dec

10/Lf

45/dec

10/pf-90

pf

cG

cfLf

10/zf

Lf10 zf10 -45/dec

cG

0

90

-180

-90

add inverted zero toPD compensator,without changing dcgain or cornerfrequencies

choose fL to be fc/10,so that phase marginis unchanged

206/220

T(s) and 1/(1+T(s)), with P

5. dc-dc converters: topologies, modeling, and...

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