The operation of 0.35 lm partially depleted SOICMOS technology in extreme environments

Ying Li a,*, Guofu Niu a, John D. Cressler b, Jagdish Patel c, S.T. Liu d,Robert A. Reed e, Mohammad M. Mojarradi c, Benjamin J. Blalock f

a Alabama Microelectronics Science and Technology Center, Department of Electrical and Computer Engineering,

200 Broun Hall, Auburn University, Auburn, AL 36849, USAb School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA

c Jet Propulsion Laboratory, Pasadena, CA 91109, USAd Honeywell Solid State Electronics Center, Plymouth, MN 55441, USA

e NASA-GSFC, Code 562, Greenbelt, MD 20771, USAf Department of Electrical and Computer Engineering, University of Tennessee, Knoxville, TN 37966, USA

Received 12 November 2002; received in revised form 5 December 2002; accepted 9 December 2002

Abstract

We evaluate the usefulness of partially depleted SOI CMOS devices fabricated in a 0.35 lm technology on UNI-

BOND material for electronics applications requiring robust operation under extreme environment conditions con-

sisting of low and/or high temperature, and under substantial radiation exposure. The threshold voltage, effective

mobility, and the impact ionization parameters were determined across temperature for both the nFETs and the

pFETs. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate

transistors. These results suggest that this 0.35 lm partially depleted SOI CMOS technology is suitable for operation

across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated

temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

� 2003 Elsevier Science Ltd. All rights reserved.

Keywords: SOI; Partially depleted; CMOS; Low temperature electronics; High temperature electronics; Radiation; Impact ionization

1. Introduction

SOI CMOS technology is currently being considered

for a variety of aerospace/military/commercial elec-

tronics applications requiring robust operation under

‘‘extreme environment’’ conditions. Such extreme envi-

ronment conditions include both tolerance to high levels

of radiation exposure (typically greater than 500 krad

total dose hardness) such as would be found on space

missions (either orbital or planetary), as well as the ca-

pability of operating reliably across a very wide temper-

ature range (e.g., from )120 �C found in deep space, up to

300 �C for certain avionics or planetary applications).

This paper presents electrical characteristics on a 0.35

lm partially depleted SOI CMOS technology suitable

for operation in such extreme environments, and in-

cludes data from the same wafer lot for: temperatures

down to 86 K, temperatures up to 300 �C (573 K), and

exposure to 63 MeV protons for an equivalent total dose

of 1.3 Mrad(Si).

2. Experiment

The devices were fabricated using 0.35 lm partially

depleted SOI CMOS technology. The starting UNI-

BOND SOI material was obtained from SOITEC. The

* Corresponding author. Tel.: +1-334-844-1865; fax: +1-334-

844-1888.

E-mail address: yingli@eng.auburn.edu (Y. Li).

0038-1101/03/$ - see front matter � 2003 Elsevier Science Ltd. All rights reserved.

doi:10.1016/S0038-1101(02)00516-6

Solid-State Electronics 47 (2003) 1111–1115

www.elsevier.com/locate/sse

thicknesses of the gate oxide, the silicon film, and the

buried oxide were 8, 215 and 400 nm, respectively. The

devices had drawn gate lengths ranging from 0.35 to 5.0

lm, all with the same width of 5.0 lm. Total dose ra-

diation hardening of the front gates, back gates, and

field oxides was accomplished using various steps in the

CMOS process flow.

The doping in the silicon film averaged 3 � 1017 cm�3

and a single nþ doped polysilicon gate was used. The

nFET and pFET transistors had a 8 nm thick gate oxide,

and a CVD oxide refilled shallow trench. Both nFETs

and pFETs used lightly doped drain (LDD) structures

to improve hot electron reliability. The body tie was

formed using a connection at each end of the gate [1,2].

The devices were measured on-wafer from 86 to 573 K

using the combination of a specially designed Blanz

Model 102 cryogenic probe station capable of operating

from 80 to 300 K, and a high-temperature Signatone

probe station capable of operating from 300 to 800 K.

Pre- and post-radiation measurements were performed

at room temperature on devices wire-bonded into 28 pin

dual-inline packages. The packages were subsequently

exposed to 62.5 MeV protons at the Crocker Nuclear

Laboratory located at the University of California at

Davis. The dosimetry measurements used a 5-foil sec-

ondary emission monitor calibrated against a Faraday

cup. Ta scattering foils located several meters upstream

of the target establish a beam spatial uniformity of 15%

over a 2.0 cm radius circular area. Beam currents from

about 5 pA to 50 nA allowed testing with proton fluxes

from 106 to 1011 protons/cm2/s. The dosimetry system is

accurate to about 10%. At a proton fluence of 1 � 1012

p/cm2, the measured equivalent gamma dose was ap-

proximately 136 krad(Si). During irradiation, the front

gates of nFETs and pFETs were biased at worst-case

conditions of 3.0 and )3.0 V, with the source, drain,

body, and back-gate biased at 0 V to turn on the front

channel. The front-gate bias was removed after irradi-

ation and before testing. These devices were measured

after equivalent total gamma doses ranging from 10

krad(Si) to 1.3 Mrad(Si) at room temperature (note that

1 radðSiO2Þ ¼ 0:945 rad(Si)). All of electrical measure-

ments were made using an Agilent 4155 semiconductor

parameter analyzer.

3. Temperature effects

Fig. 1 shows the front-gate drain current ðIDÞ versus

gate voltage ðVGSÞ characteristics for a 5/0.35 ðW =L ¼5:0 lm=0:35 lmÞ nFET at temperatures ranging from

86 to 573 K. The drain/body junction leakage current is

below the system measurement limit at 86 K, and in-

creases to 2 � 10�9 A/lm at 573 K, and is attributed to

thermal generation of carriers. Similar leakage currents

were observed in the 5=0:35 pFET, as shown in Fig. 2.

Fig. 3 compares the front-gate threshold voltage versus

temperature for both the 5=0:35 nFET and the 5=0:35

Fig. 1. Subthreshold characteristics of a 5:0=0:35 nFET as a

function of temperature.

Fig. 2. Subthreshold characteristics of a 5:0=0:35 pFET as a

function of temperature.

Fig. 3. Front-gate threshold voltage as a function of tempera-

ture for both a 5=0:35 nFET and a 5=0:35 pFET.

1112 Y. Li et al. / Solid-State Electronics 47 (2003) 1111–1115

pFET, respectively. The threshold voltage was extracted

using the standard peak gm technique. A monotonic

decrease of the front-gate threshold voltage with in-

creasing temperature can be observed for both the

nFETs and the pFETs, as theoretically expected.

Observe in Fig. 1 that ID at high VGS increases at low

temperatures, despite the increase in Vth. This is a con-

sequence of the strong enhancement in carrier mobility

with cooling due to the (expected) reduction in phonon

scattering at low temperatures. The effective mobility

ðleffÞ was extracted as a function of temperature using a

recently proposed technique which properly accounts

for the bias dependence of RSD in LDD CMOS tech-

nologies [3]. Such a technique is particularly important

at low temperatures where carrier freeze-out can

strongly increase the source/drain resistance associated

with the LDD region. The results are shown in Fig. 4 for

same gate overdrive ðVGT ¼ VGS � Vth ¼ 1:0 VÞ. At 86 K,

the effective electron mobility ðleff ;eÞ reaches a value of

more than 1800 cm2/V s, much higher than the effective

hole mobility (leff ;h ¼ 380 cm2/V s) at 86 K. The mea-

sured dependence of leff on temperature can be fitted

with:

leff ;e ¼ 320:5T

300

� ��1:402

ð1Þ

leff ;h ¼ 105:9T

300

� ��1:020

ð2Þ

which is comparable to the proposed mobility model in

[4].

The saturated drain current, IDsat, also increases with

cooling, despite the increase in Vth. Note, however, that

the shorter channel devices experience a smaller relative

increase in saturated drain current ðIDsat;T=IDsat;573 KÞthan for the longer channel devices, as shown in Fig. 5.

The reasons for this are twofold: (1) velocity saturation

is more pronounced in the shorter channel devices, and

thus the saturation velocity is more important in deter-

mining the drain current than the effective mobility, and

(2) the temperature dependence of the saturation ve-

locity is inherently much weaker than that of the mo-

bility.

At high VDS, the body current IB is mainly composed

of impact ionization induced current near the drain end

of the channel, and can be described by:

IB ¼ �Ai

BiðVD � VDsatÞIS exp

�� lpBi

VD � VDsat

�; ð3Þ

where lp is the length of the pinch-off region [5]. This

pinch-off length lp is a technology-dependent parameter,

and is determined by the gate oxide thickness ðtoxÞ and

the junction depth ðXjÞ [5] according to:

lp ¼ 0:22t1=3ox X 1=2

j ; ð4Þ

Here, Ai and Bi are two parameters relating the electric

field to the impact ionization coefficient as ai:

ai ¼ Ai exp

�� Bi

E

�; ð5Þ

Using (3), Ai and Bi were extracted from the measured

IB=ISðVD � VDsatÞ versus 1=ðVD � VDsatÞ data, as shown in

Fig. 6. The slope of the line gives �Bi and the intercept

with the y-axis yields Ai=Bi. The resulting values of Ai

and Bi are shown in Fig. 7. Our results for this SOI

technology show an increase in both Bi and Ai with

cooling, which is contrary to previously reported models

[4]. The overall ai shows an increase with cooling for the

high values of electric field typically found in the pinch-

off region.Fig. 4. Effective channel mobility versus temperature for a 0.35

lm nFET and pFET.

Fig. 5. IDsat;T =IDsat;573 K as a function of temperature for nFETs

with different channel lengths.

Y. Li et al. / Solid-State Electronics 47 (2003) 1111–1115 1113

4. Radiation effects

The devices were packaged and incrementally exposed

to 63 MeV proton radiation under bias to an equivalent

total dose of 1.3 Mrad(Si) at room temperature [6]. Up

to 1.3 Mrad(Si), the front-gate device degradation is

very small for both the nFETs and the pFETs, as shown

in Fig. 8. The front-gate threshold voltage shifts are 18

and 12 mV for the 5=0:35 nFET and the 5=0:35 pFET,

respectively. No radiation-induced leakage currents

along the isolation edge were observed (less than 10 pA

at VGS ¼ 0 V) up to 1.3 Mrad(Si). This suggests that the

front-gate transistor in this partially depleted SOI

CMOS technology has sufficient radiation hardness for

most applications.

For most SOI CMOS technologies, however, the

back-gate transistor is typically the ‘‘weak link’’ with

respect to radiation hardness. Fig. 9 shows the back-gate

threshold voltage shift as a function of total dose for the

5=0:35 nFET and 5=0:35 pFET. The threshold voltage

of the back channel ðDVth2Þ is 32 V after 1.3 Mrad(Si)

radiation dose for 5=0:35 nFET, much larger than the

11 V shift for the pFET with the same size.

The radiation-induced back channel threshold shift

ðDVth2Þ can be fitted with the following equation:

DVth2ðDÞ ¼ �A 1

�� exp

�� DD0

��; ð6Þ

where D is the total dose in rad (1 rad ¼ 100 erg/g), Aand D0 are fitting parameters. In the low dose limit, the

above equation reduces to:

DVth2ðDÞ ¼ �ADD0

; ð7Þ

where D0 is a characteristic total dose. A is the maximum

value of DVth2 at high dose (>1 Mrad) and is related to a

radiation-induced net saturated positive charge density

Not according to:

A ¼ qNot

tox2

eox

; ð8Þ

where tox2 is the buried oxide thickness, eox is oxide di-

electric constant. In the low dose limit, DVth2 can be re-

lated to physical parameters using a simple model [7]:

Fig. 6. IB=ISðVD � VDsatÞ versus 1=ðVD � VDsatÞ as a function of

temperature for a 5=0:35 nFET.

Fig. 7. Bi and Ai versus temperature for a 5=0:35 nFET.

Fig. 8. Front-gate ID–VGS characteristics for both a 5=0:35

nFET and a pFET, both before and after radiation exposure.

Fig. 9. Back-gate Vth shift versus radiation dose for a 5=0:35

nFET and a pFET.

1114 Y. Li et al. / Solid-State Electronics 47 (2003) 1111–1115

DVth2ðDÞ ¼ �aqeox

qxt2ox2D; ð9Þ

where q=x ¼ 7:6 � 1012 pairs/rad, a is the hole capture

ratio, a number which is indicative of the hardness of the

buried oxide. From the above three equations, D0 can be

expressed by using Not and a as:

D0 ¼Notxatox2q

; ð10Þ

Therefore, we finally obtain:

DVth2ðDÞ ¼ � qNottox2

eox

1

�� exp

�� atox2

qDxNot

��: ð11Þ

Applying the model represented by Eq. (11) to zero

back-gate bias data implicitly assumes that the average

hole capture probability is not strongly dependent on

electric field, at least until all of the traps are filled by

holes. Previous work [2,8,9] has shown that measured

DVth2 can in fact be fitted well as a function of dose for

zero back-gate bias during irradiation using Eq. (11).

which supports that the parameter a in Eq. (11) is still a

meaningful parameter for zero back-gate bias irradia-

tion data presented here though a should ideally be de-

termined under high electric fields in buried oxide during

irradiation [10].

Fig. 10 shows a comparison of the experimental re-

sults of DVth2 and Eq. (11) for a 5=0:35 nFET. The model

clearly captures the behavior of the experimental data.

The DVth2 is saturated after the radiation dose is above 1

Mrad(Si) for this 0.35 lm nFET on UNIBOND, as

shown in Fig. 10. Using curve-fitting, values of Not ¼1:784 � 1012 cm�2 and a ¼ 0:024 can be determined. The

data from [2] are also shown in Fig. 10 for comparison,

using 1 radðSiO2Þ ¼ 0:945 rad(Si).

5. Summary

SOI CMOS technology was investigated for its po-

tential use in electronics applications requiring ro-

bust operation in extreme environments. The nFET and

pFET threshold voltage, effective mobility, and the im-

pact ionization parameters were determined from 573 to

86 K. The radiation response was characterized to 1.3

Mrad using threshold voltage shifts of both the front-

gate and back-gate transistors. Together these data

suggest that this 0.35 lm partially depleted SOI CMOS

technology on UNIBOND material is well suited for

many extreme environment applications.

Acknowledgements

The authors would like to thank P. Marshall, H. Kim,

L. Cohn, K. LaBel, H. Brandhorst, as well as the JPL

CISM program and Honeywell for their support of this

work.

References

[1] Liu ST, Balster S, Sinha S, Jenkins WC. Worst case total

dose radiation response of 0.35 lm SOI CMOSFETs.

IEEE Trans Nucl Sci 1999;46(6):1817–23.

[2] Liu ST, Jenkins WC, Hughes HL. Total dose radiation

hard 0.35 lm SOI CMOS technology. IEEE Trans Nucl Sci

1998;45(6):2442–9.

[3] Niu G, Cressler JD, Mathew SJ, Subbanna S. Total resis-

tance slope-based effective channel mobility extraction

method for deep submicrometer CMOS technology. IEEE

Trans Electron Dev 1999;46(9):1912–4.

[4] Selberherr S. MOS device modeling at 77 K. IEEE Trans

Electron Dev 1989;36(8):1464–74.

[5] Chan TY, Ko PK, Hu C. Simple method to characterize

substrate current in MOSFET�s. IEEE Electron Dev Lett

1984;5(12):505–7.

[6] Li Y, Niu G, Cressler JD, Patel J, Marshall PW, Kim HS,

et al. Proton radiation effects in 0.35 lm partially depleted

SOI MOSFETs fabriaction on UNIBOND. IEEE Trans

Nucl Sci 2002;49(6):2930–6.

[7] Leray JL. Assessment of SOI technologies for hardening.

Microelectron Eng 1988;8(3):187–200.

[8] Liu ST, Jenkins WC, Hughes HL, Auberton-Herve AJ.

Total dose radiation induced back channel threshold

voltage shifts and standby currents of CMOS devices

fabricated in UNIBOND materials. Silicon-On-Insulator

Technology and Devices, Electrochemical Society Proceed-

ings 1997;PV97-23:307–12.

[9] Liu ST, Hughes H, Jenkins WC, Allen L. ADVANTOX––

more radiation resistant than full dose SIMOX. Proc IEEE

Inter SOI Conf 1997, p. 148–9.

[10] Flament O, Paillet P, Leray JL. Effect of supplemental

dose in SIMOX on very high ionizing dose response.

Silicon-On-Insulator Technology and Devices, Electro-

chemical Society Proceedings 1994;PV94-11:381–9.

Fig. 10. Back-gate threshold voltage shift as a function of total

dose for a 5=0:35 nFET. The back-gate was biased at 0 V during

irradiation.

Y. Li et al. / Solid-State Electronics 47 (2003) 1111–1115 1115