IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 5, MAY 2012 673

Transparent IGZO-Based Logic GatesHaojun Luo, Patrick Wellenius, Leda Lunardi, and John F. Muth

Abstract—Optically transparent indium–gallium–zinc–oxide-based NAND and NOR gates and inverters were fabricated andcharacterized using transistors deposited at room temperaturewith 5-, 10-, and 20-μm gate lengths and beta ratio between 2.5and 40. The NAND and NOR gates’ operation frequencies weremeasured up to 5 kHz. The individual transistors were measuredto have saturation mobility of 14 cm2/V · s, subthreshold swing of190 mV/dec, and current ON/OFF ratios in excess of 108. Logic op-erations were satisfactorily demonstrated for bias voltage between1 and 20 V. These results indicate that viable digital logic can beapplied particularly where optical transparency or the use of novelflexible substrates is more important than the operating speeds.

Index Terms—Indium–gallium–zinc–oxide (IGZO), logic gate,NAND gate, NOR gate, thin-film transistors (TFTs), transparentcircuits.

I. INTRODUCTION

AMORPHOUS oxide-based semiconductor thin-film tran-sistors (TFTs) have stimulated considerable industrial

and academic research because of higher electron mobilityvalues when compared with silicon and organic counterparts,transparency, and potential applications on flexible substrates[1], [2]. Most of the research has been focused on displayapplications due to the large potential market [3], [4] oron the performance of discrete devices [5]–[7]. Few reportshave been published on inverters or ring oscillators usingoxide semiconductors [8]–[11]. Presley et al. reported thefirst amorphous oxide semiconductor (AOS)-based ring os-cillator with a peak oscillation frequency of 9.5 kHz [9].Recently, indium–gallium–zinc–oxide (IGZO)-based fullytransparent ring oscillators were reported with 2-MHz oper-ating frequency [10] and OR gates at 10 Hz [12]. All oxideCMOS-type inverters were reported by Nomura et al. andMartins et al. [13], [14]. However, to our knowledge, standardextensively used logic gates such as NAND and NOR gates havenot been reported on AOS-based transistors. While easy tobuild, they represent the fundamental blocks for most Booleanfunctions and therefore for all digital integrated circuits.

In this letter, we report transparent amorphous oxide digitallogic with all layers, including interconnects, composed of

Manuscript received November 30, 2011; revised January 20, 2012; acceptedJanuary 24, 2012. Date of publication March 12, 2012; date of current versionApril 20, 2012. The review of this letter was arranged by Editor A. Flewitt.

H. Luo, L. Lunardi, and J. F. Muth are with the Department of Electrical andComputer Engineering, North Carolina State University, Raleigh, NC 27695USA (e-mail: muth@ncsu.edu).

P. Wellenius is with the Phononic Devices Inc., Raleigh, NC 27606 USA.Color versions of one or more of the figures in this letter are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/LED.2012.2186784

Fig. 1. Optical micrographs of (a) NAND and (b) NOR gates.

oxides. All NAND and NOR gates and inverters, i.e., the basicbuilding blocks of digital logic, are demonstrated here, showinghigh gain and fast response compared to amorphous siliconor amorphous organic semiconductor devices of comparabledimensions. These results indicate that IGZO digital logic issuitable for particular applications where optical transparencyor substrate flexibility could be sought.

II. EXPERIMENTAL

The devices were fabricated using a staggered bottom-gate structure. An indium–tin–oxide (ITO) (130-nm, 30-Ω/�)coated glass was patterned by photolithography, followed byBCl3 reactive ion etching dry etch to form the bottom-gateelectrode. A 100-nm Al2O3 dielectric layer was then grownby atomic layer deposition at 200 ◦C. In order to reduce theleakage current, the Al2O3 film went through rapid thermalannealing at 600 ◦C for 60 s in N2 ambience. A 40-nm-thickamorphous IGZO channel layer was deposited by pulsed laserdeposition in oxygen pressure of 25 mtorr at room temperature.The composition of the IGZO layer is Ga2O3 : In2O3 : ZnO =1 : 1 : 10. ITO source/drain contacts and interconnects werethen deposited by pulsed laser deposition at room temperature.Optical micrographs of fabricated NAND and NOR gates areshown in Fig. 1(a) and (b), respectively.

Devices of different gate lengths (L = 5, 10, and 20 μm)were fabricated. Ratio β describes the relationship be-tween the geometry of drive transistors and load transistors,i.e., β = (Ldrive/Wdrive)/(Lload/Wload). In our experiment,values of β from 2.5 to 40 were investigated. The overlapsof gate and source/drain contacts have been varied from 2.5to 5 μm. All gate design was based on Hspice simulationresults.

Discrete devices and logic gates were characterized usingan HP 4155B semiconductor parameter analyzer with Agilent33220A arbitrary waveform generator. All tests were carriedout at room temperature.

0741-3106/$31.00 © 2012 IEEE

674 IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 5, MAY 2012

Fig. 2. (a) Schematic and voltage transfer curve of an inverter(Ldrive/Wdrive = 20 μm/400 μm, Lload/Wload = 20 μm/20 μm)at V = 1, 2, 5, 10, and 20 V, (b) Analysis of the transfer curve atVDD = 20 V.

III. RESULTS AND DISCUSSION

The transmission spectrum of the complete device stackshows 80% transparency throughout the visible region of thespectrum.

Individual transistors had the following parameters: atVDS = 5 V, a threshold voltage of 0.2 V, a subthreshold slopeless than 190 mV/dec, an ON/OFF current ratio larger than 108,and a saturation field-effect mobility value μsat of 14 cm2/V · swere measured. The OFF-state current is less than 1 pA,limited by gate leakage. The TFT transfer characteristics showenhancement mode operation allowing realization of simple cir-cuits without the necessity of level shifting. The low thresholdvoltage value, as well as the small value of subthreshold swing,allows the device to operate at 1.5 V, indicating potential low-power applications, and significant future progress in energyefficiency. Devices also operated from 1 to 20 V, compatiblewith different current integrated-circuit technologies.

An inverter is constructed by connecting a load transistor op-erating in saturation mode (VGG = VDD) to a drive transistor.Fig. 2(a) shows the voltage transfer curve of an inverter usinga load transistor with L = 20 μm and W = 20 μm and a drivetransistor with L = 20 μm and W = 400 μm. Switching fromthe high to the low state was observed for VDD = 1, 2, 5, 10,and 20 V. Full swing of the output from near 0 V to VDD − Vth

was also observed for all voltages. As shown in Fig. 2(b), atVDD = 20 V, the peak gain magnitude (gain = d VOUT/d VIN)of this inverter is as high as 18.4, which is considered high foran AOS enhancement load inverter [10], [11]. The noise mar-gins in high-state NMH (NMH = |VOH − VIH|) and low-stateNML (NML = |VIL − VOL|) were determined to be 18.2 and0.7 V, respectively. The transition width (VIH − VIL), whichindicates the undefined logic state region, is as small as 2.2 V.The voltage gain and noise margin in this letter are better thanthose of all oxide complementary CMOS-type inverters due todifferent materials and substrates [13], [14].

Here, it was observed that, for the same gate length, a largerbeta ratio results in a sharper transfer curve. This is because,when the gate width of the drive transistor is larger, a largercurrent is allowed to pass through the transistor when the gatevoltage is high. Therefore, the discharge process is faster. Forthe similar reason, the output OFF-state voltage was lower fora higher beta ratio. The larger device width results in a larger

Fig. 3. Schematic and voltage transfer curve of: (a) NAND gate(Ldrive/Wdrive = 20 μm/200 μm); and (b) NOR gate (Ldrive/Wdrive =10 μm/25 μm), VDD = 5 V.

input capacitance value. Thus, it will take a longer time for theload transistor to charge that input capacitance when the inputvoltage changes from high to low.

The NAND gate was realized by a series connection oftwo drive transistors and a load transistor, whereas the NOR

gate was constructed by two parallel drive transistors con-nected to a load transistor. A variety of devices with dif-ferent gate lengths (L = 5, 10, and 20 μm), beta ratio (β =2.5, 5, 10, 20, and 40), and different gate and source/drain over-laps (overlap = 5 and 2.5 μm) were fabricated.

The performance of the NAND and NOR gates under dcvoltage and dynamic waveform inputs were characterized. Thedc transfer curve for a β = 40 NAND gate is shown in Fig. 3(a)with the schematic of the NAND gate in the inset. The NAND

gate shows very sharp transfer characteristics for VDD from 1to 20 V. As shown in Fig. 3(a), when VDD = 5 V, if one inputVA was low (0 V), the output was in high state (4.9 V). If inputVA was high (VA = VDD), the NAND gate acted like an inverter.

Comparing the devices with same gate length and differentbeta ratio, the NAND gates with smaller values of β showshallower transfer characteristics, consistent with theory. Fora NAND gate (Ldrive/Wdrive = 10 μm/25 μm), the outputvoltage drops from 4.9 V to less than 1 V for the input VDD =5 V, whereas for the Ldrive/Wdrive = 10 μm/400 μm NAND

gate, the output voltage drops from 4.9 V to less than 0.1 V.The gate source/drain overlap has been designed to be 2.5

and 5 μm. As expected, the larger overlap (5 μm) deviceswith larger input capacitance consequently yielded shallowertransfer characteristics and slower response speed.

The voltage transfer curve for a β = 2.5 NOR gate is dis-played in Fig. 3(b) with the schematic of the NOR gate in theinset. If one of the inputs VA was kept high, the output voltagewas always low regardless of voltage applied to the other input.If input VA was low, the NOR gate acted like the inverter.Similar to the NAND gate, the NOR gate displayed sharp transfercharacteristics and satisfactory functionality from 1 to 20 V. ForVDD = 5 V, the output voltage dropped from 4.9 V to less than0.1 V when input VB is scanned from low to high.

In order to test the dynamic performance of the NAND andNOR gates, two input signals (VA = VB = 10 V) were directlyapplied to two input terminals. The supply voltage VDD was10 V. The output waveforms of typical NAND and NOR gatesoperating at 100 Hz, 1 kHz, and 5 kHz are shown in Fig. 4(a)

LUO et al.: TRANSPARENT IGZO-BASED LOGIC GATES 675

Fig. 4. Output waveforms with supply voltage of VDD = 10 V of(a) NAND gate (Ldrive/Wdrive = 10 μm/400 μm) and (b) NOR gate(Ldrive/Wdrive = 10 μm/100 μm), operating at 100 Hz, 1 kHz, and 5 kHz.

and (b), respectively. Note that, in this setup, no level shifter oroutput buffer was employed.

The parasitic capacitance originating from the Al2O3 dielec-tric was measured to be 85 nF/cm2. For the NAND gate, theoutput was low only when both inputs were high. In contrast,for the NOR gate, the output is high only when both of the inputsare at low voltage. As depicted in Fig. 4, for the frequencyof 100 Hz, the output waveform is sharp, without significantdifference between the rise and fall times. At the frequency of5 kHz, the rise and fall times of the NAND gate are 78 and 8 μs,respectively, whereas the rise and fall times of the NOR gateare 52 and 12 μs, respectively. The driver transistors of thisNOR gate are smaller (Ldrive/Wdrive = 10 μm/100 μm) thanthose of this NAND gate (Ldrive/Wdrive = 10 μm/400 μm)therefore yielding shorter rise times. The rise time is muchlarger than the fall time, implying that the limitation of thiscircuit for operating at a higher frequency is the charging time.Increasing the channel width of the load transistor or decreasingthe capacitance of the drive transistor could reduce the chargingtime. Decreasing gate source/drain overlap and reducing theresistance of interconnects could reduce the RC time constantand improve operating speeds. The speed of the NAND and NOR

gates was as high as 5 kHz, much faster than earlier reported OR

gate results [12].The logic gates in this letter were constructed with n-type-

only TFTs. The n-type circuits have fewer transistors count thancomplementary circuits, but they tend to dissipate higher staticpower.

The above results indicate that AOS-based logic gates areviable as the integrated-circuit technology for particular appli-cations and transparent systems on glass or plastics. Due to therelatively low operating frequency and high capacitance com-pared to other high-frequency integrated-circuit technologies,those applications may be constrained to areas specifically notrequiring fast response. However, the high electron mobilityobserved in amorphous IGZO films so far promises furtherincrease in the circuit speed. By scaling down the devicedimensions, optimizing the circuit design, reducing parasiticcapacitance and interconnect resistance could lead to highermaximum operating frequency. The low threshold voltage andsmall subthreshold swing permit stable logic operation at lowvoltages, indicating progress in energy efficiency. Furthermore,the logic gates were demonstrated to function over a range of

voltages indicating that they can be easily integrated with avariety of current integrated-circuit technologies.

IV. CONCLUSION

Transparent amorphous IGZO-based NAND and NOR gateshave been realized. Individual transistors with a threshold volt-age of 0.2 V, a subthreshold slope less than 190 mV/dec, acurrent ON/OFF ratio larger than 108, a gate leakage currentless than 1 pA, and a saturation field-effect mobility value μsat

of 14 cm2/V · s were fabricated. These logic gates demon-strated sharp transfer characteristics and satisfactory function-ality between 1 and 20 V with operating frequencies reaching5 kHz. The significance of these results indicates basic digitallogic building blocks with high gain and fast response anddemonstrates the viability for amorphous oxide digital logic fortransparent and flexible electronic systems.

REFERENCES

[1] J. F. Wager, “Transparent electronics,” Science, vol. 300, no. 5623,pp. 1245–1246, May 2003.

[2] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono,“Room-temperature fabrication of transparent flexible thin-film transistorsusing amorphous oxide semiconductors,” Nature, vol. 432, no. 7016,pp. 488–492, Nov. 2004.

[3] J. S. Park, T. W. Kim, D. Stryakhilev, J. S. Lee, S. G. An, Y. S. Pyo,D. B. Lee, Y. G. Mo, D. U. Jin, and H. K. Chung, “Flexible full colororganic light-emitting diode display on polyimide plastic substrate drivenby amorphous indium gallium zinc oxide thin film transistors,” Appl.Phys. Lett., vol. 95, no. 1, pp. 013503-1–013503-3, Jul. 2009.

[4] J. Jeong, “The status and perspectives of metal oxide thin-film transistorsfor active matrix flexible displays,” Semicond. Sci. Technol., vol. 26, no. 3,p. 034008, Mar. 2011.

[5] N. C. Su, S. J. Wang, C. C. Huang, Y. H. Chen, H. Y. Huang, C. K. Chiang,and A. Chin, “Low voltage-driven flexible InGaZnO thin-film transistorwith small subthreshold swing,” IEEE Electron Dev. Lett., vol. 31, no. 7,pp. 680–682, Jul. 2010.

[6] I. Song, S. Kim, H. Yin, C. J. Kim, J. Park, S. Kim, H. S. Choi, E. Lee, andY. Park, “Short channel characteristics of gallium indium zinc oxide thinfilm transistors for three-dimensional stacking memory,” IEEE ElectronDev. Lett., vol. 29, no. 6, pp. 549–552, Jun. 2008.

[7] E. Fortunato, L. Pereira, P. Barquinha, A. Botelho do Rego, G. Goncalves,A. Vila, J. Morante, and R. Martins, “High performance indium free oxidethin film transistor,” Appl. Phys. Lett., vol. 92, no. 22, pp. 222 103-1–222 103-3, Jun. 2008.

[8] J. M. Lee, I. T. Cho, J. H. Lee, and H. I. Kwon, “Full-swing InGaZnO thinfilm transistor inverter with depletion load,” Jpn. J. Appl. Phys., vol. 48,no. 10, pp. 100 202-1–100 202-3, Oct. 2009.

[9] R. E. Presley, D. Hong, H. Q. Chiang, C. M. Hung, R. L. Hoffman, andJ. F. Wager, “Transparent ring oscillator based on indium gallium oxidethin-film transistors,” Solid State Electron., vol. 50, no. 3, pp. 500–503,Mar. 2006.

[10] A. Suresh, P. Wellenius, V. Baliga, H. Luo, L. M. Lunardi, andJ. F. Muth, “Fast all-transparent integrated circuits based on indium gal-lium zinc oxide thin-film transistors,” IEEE Electron Dev. Lett., vol. 31,no. 4, pp. 317–319, Apr. 2010.

[11] D. Zhao, D. A. Mourey, and T. N. Jackson, “Fast flexible plastic substrateZnO circuits,” IEEE Electron Dev. Lett., vol. 31, no. 4, pp. 323–325,Apr. 2010.

[12] W. Lim, E. Douglas, J. Lee, J. Jang, V. Craciun, D. Norton, S. Pearton, F.Ren, S. Y. Son, J. H. Yuh, H. Shen, and W. Chang, “Transparent dual-gateInGaZnO thin film transistors: OR gate operation,” J. Vac. Sci. Technol.B, vol. 27, no. 5, pp. 2128–2131, Sep. 2009.

[13] K. Nomura, T. Kamiya, and H. Hosono, “Ambipolar oxide thin-film tran-sistor,” Adv. Mater., vol. 23, no. 30, pp. 3431–3434, Aug. 2011.

[14] R. Martins, A. Nathan, R. Barros, L. Pereira, P. Barquinha, N. Correia,R. Costa, A. Ahnood, I. Ferreira, and E. Fortunato, “Complementary metaloxide semiconductor technology with and on paper,” Adv. Mater., vol. 23,no. 39, pp. 4491–4496, Oct. 2011.