vhdl qua cac vi du.ppt
TRANSCRIPT
Dr. Le Dung Hanoi University of Science and Technology
THIẾT KẾ SỐ VỚI VHDL QUA CÁC VÍ DỤ
NỘI DUNG
Dr. Le Dung Hanoi University of Science and Technology
• GIỚI THIỆU CHUNG VỀ THIẾT KẾ SỐ VỚI VHDL
• TỔNG QUAN VỀ NGÔN NGỮ VHDL
• LIBRARY DECLARATION
• ENTITY DECLARATION
• ARCHITECTURES
• CONFIGURATION
Dr. Le Dung Hanoi University of Science and Technology
DANH SÁCH CÁC VÍ DỤ • VÍ DỤ 1 : Bộ cộng Half-Adder • VÍ DỤ 2: Bộ so sánh 3 bits • VÍ DỤ 3: FSMD - ISA bus interface design • VÍ DỤ 4: Bộ MUX21 (Thiết kế 1, 2 , 3) • VÍ DỤ 5: Testbench cho MUX21 • VÍ DỤ 6: My_Package và D Flip Flop • VÍ DỤ 7: Mạch so sánh 2 số 8 bits • VÍ DỤ 8: Time signal type • VÍ DỤ 9: Mảng AND 4 bits • VÍ DỤ 10: General MUX với generic constant • VÍ DỤ 11: XOR3_Gate kiến trúc DATAFLOW
• …….
GIỚI THIỆU CHUNG VỀ THIẾT KẾ SỐ VỚI VHDL
Dr. Le Dung Hanoi University of Science and Technology
• Các mức thiết kế trừu tượng (Levels of Abstraction)
• Chu trình thiết kế số trên ASIC & FPGA với VHDL
• Công cụ phần mềm thiết kế với VHDL
Dr. Le Dung Hanoi University of Science and Technology
CÁC MỨC THIẾT KẾT TRỪU TƯỢNG - Levels of Abstraction in IC design -
Physic
layout level
Behavioural level
Register Transfer level (RTL)
Gate level
F a
b y y = f(a,b)
Des
ign
Com
pila
tion
Pro
cess
Dr. Le Dung Hanoi University of Science and Technology
CHU TRÌNH THIẾT KẾ SỐ TRÊN ASIC & FPGA
Requirements
Simulate RTL Model
Gate-level Model
Synthesize
Simulate Test Bench
ASIC or FPGA Place & Route
Timing Model Simulate
Des
ign
Com
pila
tion
Pro
cess
Dr. Le Dung Hanoi University of Science and Technology
CHU TRÌNH THIẾT KẾ VỚI VHDL
Mô phỏng mã VHDL
Viết mã VHDL cho từng khối
(Block)
Viết mã VHDL cho bàn kiểm tra (Testbench)
Phân tích hệ thống và phân chia khối (Block)
Tổng hợp logic (netlists & gate structure)
Mô phỏng ở mức cổng (gate level)
Tổng hợp trên vi mạch (floor planning, place, route, timing, implement)
Behavioural level
RT level
Gate level
Physic
layout level
chiếm 70% thời gian thiết kế
Des
ign
Com
pila
tion
Pro
cess
Dr. Le Dung Hanoi University of Science and Technology
CÔNG CỤ PHẦN MỀM THIẾT KẾ VỚI VHDL • Aldec Active HDL • Mentor Graphics ModelSim • Synplicity Synplify Pro • ModelSim Xilinx • Xilinx XST • Xilinx ISE • Xilinx WebPACK • Altera Quartus II • ModelSim Altera • Altera Quartus II Web Edition • GMU ATHENa • DirectVHDL Green Mountain
EDA TOOLS
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ: PHẦN MỀM QUARTUS II 9.0
Dr. Le Dung Hanoi University of Science and Technology
CHU TRÌNH THIẾT KẾ TRÊN QUARTUS II 9.0
Dr. Le Dung Hanoi University of Science and Technology
GIAO DIỆN QUARTUS II 9.0
TỔNG QUAN VỀ NGÔN NGỮ VHDL
Dr. Le Dung Hanoi University of Science and Technology
• KEYWORDs, STATEMENTs, IDENTIFIERs
• ENTITY và một số khái niệm cơ bản
• CẤU TRÚC CƠ BẢN CỦA MỘT ENTITY + Library declarations + Entity + Architecture + Configuration
• TESTBENCH
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 1: BỘ CỘNG HALF-ADDER
Schematic block design
Reserved words
(keywords) Statement
Identifiers
VDHL Entity design
Statement
Statement ending
Comment
Dr. Le Dung Hanoi University of Science and Technology
CÁC TỪ KHÓA CỦA VHDL
Dr. Le Dung Hanoi University of Science and Technology
CÁC QUI ƯỚC CƠ BẢN CỦA VHDL
• Không phân biệt chữ hoa chữ thường (case insensitive)
• Chú thích (comment) được đặt sau 2 ký tự gạch ngang “--” và tính cho đến cuối dòng. Có thể bắt đầu từ bất kỳ vị trí nào.
• Một phát biểu (statement) có thể được triển khai trên nhiều dòng và luôn kết thúc bằng dấu chấm phẩy “;”.
• Dấu phẩy “,” dùng để ngăn cách giữa các phần tử trong 1 danh sách.
• Gán tín hiệu (signal assignment) bằng ký hiệu ngoặc nhọn và dấu bằng “<=“.
• Liên kết cổng (port association) với tín hiệu thì dùng “=>”.
• Định danh có thể gồm các chữ cái (A-Z,a-z), số (0-9) và dấu gạch chân (_), phải bắt đầu bằng chữ cái. Định danh là duy nhất trong Entity và Architecture.
Dr. Le Dung Hanoi University of Science and Technology
MỘT SỐ MỞ RỘNG TRONG VHDL93
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 2: BỘ SO SÁNH 3 BIT Top-level Entity
Top-level Entity
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 3: FSMD - ISA bus interface ----------------------------------------------------- -- ISA bus interface design (ISA.vhd) ----------------------------------------------------- -- 8-bit adder ----------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity adder is . . . . . . . . . . . . . . . . end adder; architecture behv of adder is . . . . . . . . . . . . . . . . end behv; -- Comparator --------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity comparator is . . . . . . . . . . . . . . . . . end comparator; architecture behv of comparator is . . . . . . . . . . . . . . . . . end behv; -- Data Register -------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity data_reg is . . . . . . . . . . . . . . . . . end data_reg; architecture behv of data_reg is . . . . . . . . . . . . . . . . . end behv;
-------------------------------------------------------- -- Data Path of ISA bus interface --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity datapath is . . . . . . . . . . . . . . . end datapath; architecture struct of datapath is component data_reg is . . . . . . . . .. . . end component;
component comparator is . . . . . . . . . . . end component;
component adder is . . . . . . . . . . . . end component; end struct; ---------------------------------------------------------- -- FSM controller for ISA bus interfacing ---------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity controller is . . . . . . . . . . . . . . . end controller; architecture fsm of controller is . . . . . . . . . . . . . . . end struct;
------------------------------------------------------- -- ISA bus interface ( FSM + Datapath ) -- VHDL structural modeling ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.all; entity ISA is . . . . . . . . . . . . . end ISA; architecture struct of ISA is
component controller is . . . . . . . . . . end component;
component datapath is . . . . . . . . . . . . end component;
begin
end struct;
U1: datapath port map ( . . . . . . . );
U0: controller port map (. . . . . . .. );
http://esd.cs.ucr.edu/labs/tutorial/ISA.vhd
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 3: FSMD - ISA bus interface
Dr. Le Dung Hanoi University of Science and Technology
ENTITY VÀ MỘT SỐ KHÁI NIỆM CƠ BẢN
DESIGN (VHDL)
TOP-LEVEL ENTITY
COMPONENT C1
COMPONENT C2
COMPONENT C3
ENTITY BL1
ENTITY BL2
COMPONENT C2
ENTITY BL3
COMPONENT C4 COMPONENT C4
LIBRARY.PACKAGE
. . . . . . . . .
Dr. Le Dung Hanoi University of Science and Technology
CẤU TRÚC ENTITY ĐƠN GIẢN
Entity declaration
Architecture of the entity
design entity: HALFADDER
Lưu trong tệp: halfadder.vhd (thường cùng tên với Entity và có đuôi là .vhd)
VÍ DỤ 1: Chỉ khai báo một Entity với một Architecture
Dr. Le Dung Hanoi University of Science and Technology
ENTITY & ARCHITECTURES
Design Entity - most basic building block of a design.
One entity can have 3 styles of architecture
entity declaration
architecture 1
architecture 2
architecture 3
design entity - File extension for a VHDL file is .vhd - Name of the file should be the same as the entity name.
Dataflow Behavioral Structural
Dr. Le Dung Hanoi University of Science and Technology
CẤU TRÚC CƠ BẢN CỦA ENTITY
library …;
use … ;
entity ETT is port ( ……….); end entity ETT ;
architecture STYLE of ETT is begin ….. end architecture STYLE;
configuration CONF of ETT is for STYLE ….. end for; end configuration CONF;
ENTI
TY
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MÃ VHDL CƠ BẢN CỦA ENTITY
Configuration
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VÍ DỤ 4: BỘ MUX21 Thiết kế 1 : 1 Entity + 1 Architecture
A
B
S
Y
Schematic
RTL Viewer Technology mapping viewer
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 4: BỘ MUX21 Thiết kế 2 : Top-level Entity + 2 Architectures và 1 số Entities tạo cổng.
A
S
B
Y U V
W
port map
Schematic
Khi biên dịch sẽ chọn kiến trúc nào cho MUX21 ?
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 4: BỘ MUX21 Thiết kế 2 : Entities tạo cổng INV, AND2i, OR2i cho Top-level Entity
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 4: BỘ MUX21 Thiết kế 2 Hierachy, RTL viewer , Techology Mapping viewer
RTL Viewer
(Nestlist)
Technology Mapping Viewer
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 4: BỘ MUX21 Thiết kế 3 : Top-level Entity + 2 Architectures + Configuration và 1 số Entities tạo cổng INV, AND2i, OR2i và thêm AND3i.
Top-level entry (thiết kế 2) thêm đoạn mã VHDL sau :
Dùng AND3i
Dùng AND2i
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 4: BỘ MUX21 Thiết kế 3 : thêm Entity AND3i để dùng cho configuration
Dr. Le Dung Hanoi University of Science and Technology
TESTBENCH
A VHDL ‘test bench’ can be considered to be the top level of a design
It instantiates the Design Under Test (DUT) applies stimuli to it checks whether the stimuli are correct or captures the outputs for visualisation in a waveform viewer
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 5: TESTBENCH cho BỘ MUX21
LIBRARY DECLARATION
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• Khái niệm library và package
• library: IEEE, STD, WORK
• Packages in IEEE
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KHÁI NIỆM LIBRARY Tập hợp (directory) các đơn vị thiết kế (design units) đã được biên dịch (compiled) để sau đó có thể tái sử dụng (re-use) trong thiết kế khác nhau mà mã nguồn VHDL sẽ được che dấu (hide).
library Lib_Name;
use Lib_name.Pak1.all
entity
architecture
Library Lib_name
Package Pak1 Package Pak2
Components
Functions
Procedures
Design Entity
Constants
Data types
Components
Functions
Procedures Compiled design units
Dr. Le Dung Hanoi University of Science and Technology
BA LOẠI LIBRARIES CHÍNH
• ieee
• std
• work
Specifies multi-level logic system, complex mathematical functions, logic functions, numeric types ….
Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.
Holds current designs after compilation
Ngầm định luôn thấy được nên không cần khai báo
Cần khái báo tại tất các các Entity khi sử dụng đến các đơn vị thiết kế bên trong thư viện này
Dr. Le Dung Hanoi University of Science and Technology
Một số PACKAGE trong LIBRARY ieee
library IEEE; use IEEE.Std_logic_1164.All;
Syntax:
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VÍ DỤ 6: My_Package và D Flip Flop Tạo package: My_package trên library: work
Kiểu trạng thái cho FF
Hàm phát hiện sườn xung dương
đoạn BODY
mô tả function
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 6: My_Package và D Flip Flop Entity: D_FF mô tả D Flip-flop có sử dụng work.My_package
Hàm đầu ra kiểu Moore :
reset Q = 0 ; set Q = 1
Chuyển đổi trạng thái theo D và CLK sườn dương
D=1 Set; D=0 Reset
ENTITY DECLARATION
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• Syntax
• Entity Port modes
• Standard Signal types
• Time and Delay Models
• User defined data type
• Generic constants
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Entity Declaration ?.
HALFADDER
CARRY
SUM
A
B
Đinh danh của thực thể
Giao diện vào (port in) Giao diện ra (ports out)
Mô tả định danh và giao diện vào/ra của một khối mạch (module) như 1 hộp đen (nghĩa là không mô tả chi tiết và hoạt đông bên trong)
Dr. Le Dung Hanoi University of Science and Technology
Entity Syntax entity Entity_name is
port (Port_name_1 : in Signal_type; Port_name_2 : inout Signal_type; Port_name_3 : out Signal_type );
end entity Entity_name; keywords: entity, is, end
port, in, out, inout, buffer
entity interfaces ports
in : inputs (read-only)
out: outputs (write-only)
inout: bidirectional data
buffer: outputs and readable
Port modes (direction)
Signal types
Dr. Le Dung Hanoi University of Science and Technology
Entity Port Modes Chỉ có thể gán cho signal hoặc variable
Chỉ có thể bị gán (muốn đọc thì phải định nghĩa tín hiệu trung gian vô hướng w_output
Ghi ra từ 1 nguồn và có thể đọc vào mà không cần biến trung gian.
1 ví dụ về out và buffer
in ports
Data bus
inout dùng kết nối với bus dữ liệu 2 chiều
Dr. Le Dung Hanoi University of Science and Technology
Standard (Predefined) Signal Types
package Standard is type Bit is (‘0’,’1’); type Bit_vector is (-- array of bits); type Boolean is (False, True); type Character is (--ASCII set) type Integer is range implementation_defined; type Real is range implementation_defined; type String is (--array of characters); type Time is range implementation_defined;
end package Standard;
(in std library)
integer range: (-2147483647 to 2147483647) (32 bits) real range : (-1.0E308 to 1.0E308) not synthesizable time range : (-2147483648 to 2147483647)
Dr. Le Dung Hanoi University of Science and Technology
Standard signal type: BIT
Mô tả cổng AND 3 đầu vào
BIT: nhận một trong hai giá trị là ‘0’ hoặc ‘1’ (viết trong nháy đơn)
Dr. Le Dung Hanoi University of Science and Technology
Standard signal type: BIT_VECTOR BIT_VECTOR: là một mảng 1 chiều gồm các phần tử kiểu BIT với phần tử có trọng số cao nhất luôn là phần tử đầu tiên (bên trái)
Ví dụ: nếu port d được định nghĩa :
d: out BIT_VECTOR (3 downto 0);
thì d là mảng gồm 4 phần tử d(3), d(2), d(1) và d(0) với d(3) là MSB
Trong architecture có thể gán như sau:
d(3) <= ‘1'; tương đương với gán d <= “1101";
d(2) <= '1';
d(1) <= '0';
d(0) <= '1';
Còn nếu định nghĩa d: out BIT_VECTOR (0 to 3); thì khác là d(0) sẽ là MSB. Ví dụ : d <= “0101”; d(0)<=0; d(1)<=1; d(2)<=0; d(3)<=1;
Dr. Le Dung Hanoi University of Science and Technology
Ví dụ 7: Mạch so sánh 2 số 8 bits BIT_VECTOR BIT
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Boolean, Integer, Real, String
-- Examples of integer declarations: type Year is range 0 to 99; type Memory_address is range 65535 downto 0;
-- Examples of real declarations: type Probability is range 0.0 to 1.0; type Input_level is range -5.0 to 5.0;
-- A String (a collection of characters) a value is specified between “ “ constant Error_message: string := “Error ! Do not press any botton ! ”;
Checked by simulator
-- Trong ví dụ 6
function Positive_edge (signal clk:std_logic) return boolean;
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Time signal type
type Time is range implementation_defined units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units;
(femto-seconds) Primary unit:
resolution limit for VHDL simulator
Secondary units
- ‘Time' is a special data type a physical unit. - It is used to delay the execution of statements for a certain amount of time, e.g. in testbenches or to model gate and propagation delays - Time in range (-2147483648 to 2147483647)
Dr. Le Dung Hanoi University of Science and Technology
Ví dụ 8: Time signal type architecture EXAMPLE of TIME_TYPE is signal CLK : bit := ’0’; constant PERIOD : time := 10 ns; begin -- sequential time delay process begin wait for 20 ns; . . . wait for PERIOD ; . . . wait for 5 * PERIOD ; . . . wait for PERIOD *5.5; end process; ……..
-- concurrent signal assignment -- with constant time CLK <= not CLK after PERIOD/2;
end EXAMPLE;
20ns 10ns 50ns 55ns
Process
… … …
CLK
10ns
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Delay Model 1: Inertial Delay (Trễ quán tính)
giảm sự lan truyền các xung nhọn qua mạch
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Delay Model 2: Transport Delay (Trễ truyền dẫn)
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Delay Model 3: Delta Delay (Trễ dùng trong tính toán mô phỏng các quá trình song song)
no Delta delay
Xem phần sau:
Concurrent statement and Simulation
Dr. Le Dung Hanoi University of Science and Technology
Signal type: STD_LOGIC (also called IEEE Std.1164 Multi-Valued Logic )
STD_LOGIC: là kiểu giá trị logic chuẩn được định nghĩa rộng hơn hai giá trị ‘0’ và ‘1’ của kiểu BIT. Gồm 9 giá trị được định nghĩa trong library là IEEE thuộc package : std_logic_1164 package
library IEEE; use IEEE.Std_logic_1164.All;
type std_logic is ( ‘U’, -- uninitialized e.g. after power-up ‘X’, -- strongly driven unknown e.g. after setup violation ‘0’, -- strongly driven logic zero ‘1’, -- strongly driven logic one ‘Z’, -- high impedance e.g. not driven at all ‘W’, -- weakly driven unknown ‘L’, -- weakly driven logic zero ‘H’, -- weakly driven logic one ‘-’); -- don’t care
Chủ yếu dùng cho mô phỏng. ‘0’,’1’ và ‘Z’ có thể tổng hợp được (synthesizable)
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Signal type: STD_LOGIC (also called IEEE Std.1164 Multi-Valued Logic)
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Signal type: STD_ULOGIC signal Z,A,B: std_ulogic;
Z <= A; Z <= B;
This code is invalid, because: all statements are concurrently valid and are not executed sequentially
when A=‘0’ and B=‘1’, we have a short circuit
A
B Z
A
B Z R
Resolver circuit
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Resolved signal type • For resolved signal types (std_logic & std_logic_vector), the resolver circuit is inferred by the synthesis tool
A
B Z R
Resolver circuit signal Z,A,B: std_logic;
Z <= A; Z <= B;
Resolved
logic level
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Signal type: STD_LOGIC_VECTOR ( 1D array of STD_LOGIC)
Ví dụ 9: Mảng AND 4 bits
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SIGNAL : Wire and BUS
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0);
wire
a
bus
b
1
8
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Ghép (Concatenation) các tín hiệu std_logic_vector
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111”
d <= ‘0’ & ”0001111”; -- d <= ”00001111”
e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- e <= ”00001111”
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Gán các tín hiệu std_logic_vector
signal Down: std_logic_vector (3 downto 0); signal Up: std_logic_vector (0 to 3);
Up <= Down;
Up(0)
Up(1)
Up(2)
Up(3)
Down(3)
Down(2)
Down(1)
Down(0)
OR
Up(0)
Up(1)
Up(2)
Up(3)
Down(0)
Down(1)
Down(2)
Down(3)
Correspondence by position!
Dr. Le Dung Hanoi University of Science and Technology
Gán 1 phần các tín hiệu std_logic_vector
signal Bus: std_logic_vector (7 downto 0); signal A: std_logic_vector (0 to 3);
Which of the following VHDL codes is correct?
Bus(0 to 3) <= A;
Bus <= A;
Bus(3 downto 0) <= A;
Bus(5 downto 4) <= A(0 to 1);
Bus(5 downto 4) <= A(0 to 1); Bus(4 downto 3) <= A(2 to 3);
Direction of Bus differs from declaration
Array sizes do not match
OK! Bus(3) is driven by A(0)
OK! Bus(5) is driven by A(0)
OK! Bus(4) is driven by A(1) and by A(2): resolved data
type… use with care!!
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Signed and Unsigned Data types (in IEEE.std_logic_arith)
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Dùng package ieee.std_logic_unsigned
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Một số ví dụ sử dụng các kiểu tín hiệu
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Một số ví dụ sử dụng đúng và sai kiểu
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User defined types
type Length is range 0 to 1E9 units um; mm = 1000 um; m = 1000 mm; km = 1000 m; mil = 254 um; inch = 1000 mil; foot = 12 inch; yard = 3 foot; end units;
Primary unit: resolution limit
Metric secondary units
Imperial secondary units
type 1D_array is array (0 to 15) of integer; type 2D_array is array (7 downto 0, 1 to 10) of real;
type Squ_Matrix is array (0 downto 15) of 1D_array;
-- User defined array types
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User defined enumerated types
-- user-defined a subset of std_logic type my_logic is (‘0’, ‘1’, ‘Z’)
subtype output_signal is Std_logic range ‘0’ to ‘Z’; (chú ý: Std_logic được liệt kê theo thứ tự sau : (‘U’, ‘X’ , ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’)
type FF_states is (reset, set) ; -- Xem Ví dụ 6
type FSM_states is (S1, S2, S3, S4, S5);
type color is (red, green, blue, white); encoding red = “00”
green =“01” blue = “10”
white = “11”
Dr. Le Dung Hanoi University of Science and Technology
Generic constants • Cho phép tạo tham số trong việc mô tả hoạt động. • Tham số đó dễ dàng thay đổi để đáp ứng cho các thiết kế khác nhau. • Tạo ra một chương trình mã linh động và dễ tái sử dụng. • Phải được khai báo trong Entity. • Có thể khai báo nhiều Generic constants. • Generic constants cần được xác định 1 giá trị cụ thể khi chạy chức
năng tổng hợp mạch. VÍ DỤ 10: General MUX với generic constant
ARCHITECTURE
Dr. Le Dung Hanoi University of Science and Technology
• Syntax
• • •
Dr. Le Dung Hanoi University of Science and Technology
ARCHITECTURE SYNTAX
architecture Architecture_Name of Entity_Name is [ declarations ] -- Optional
begin code -- concurrent statements
end architecture Architecture_Name;
HA HA
OR
Entit
y de
clar
atio
n
Entit
y de
clar
atio
n
Architecture
A
B
Cin
S
Cout
s1
c1
c2
Operator
Signals
Components
Processes
Dr. Le Dung Hanoi University of Science and Technology
Ba dạng cơ bản của Architecture
Components and interconnects
structural
Architecture Styles
dataflow
Concurrent statements
behavioral
• Registers • State machines • Test benches
Sequential statements
Dr. Le Dung Hanoi University of Science and Technology
DATAFLOW
• concurrent signal assignment (⇐) • conditional concurrent signal assignment (when-else) • selected concurrent signal assignment (with-select-when) • generate scheme for equations (for-generate)
Concurrent statements
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ 11: XOR3_Gate kiến trúc DATAFLOW
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY xor3_gate IS PORT( A : IN STD_LOGIC;
B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC );
end xor3_gate;
ARCHITECTURE dataflow OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC; BEGIN
U1_OUT <= A XOR B; Result <= U1_OUT XOR C;
END dataflow;
U1_OUT
Dr. Le Dung Hanoi University of Science and Technology
Mô tả Dataflow • Describes how data moves through the system and the various
processing steps. • Dataflow uses series of concurrent statements to realize logic. • Dataflow is most useful style when series of Boolean equations
can represent a logic used to implement simple combinational logic
• Dataflow code also called “concurrent” code • Concurrent statements are evaluated at the same time; thus, the
order of these statements doesn’t matter • This is not true for sequential/behavioral statements
This order… U1_out <= A XOR B; Result <= U1_out XOR C;
Is the same as this order… Result <= U1_out XOR C; U1_out <= A XOR B;
Dr. Le Dung Hanoi University of Science and Technology
Mô tả Structural ARCHITECTURE structural OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC;
COMPONENT xor2
PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC );
END COMPONENT;
BEGIN U1: xor2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: xor2 PORT MAP (I1 => U1_OUT, I2 => C, Y => Result);
END structural;
ABC
Result xor3_gate
I1 I2
Y I1 I2
Y
U1_OUT
PORT NAME
LOCAL WIRE NAME
Dr. Le Dung Hanoi University of Science and Technology
Mô tả Structural
ARCHITECTURE structural OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC;
BEGIN U1: entity work.xor2(dataflow)
PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: entity work.xor2(dataflow)
PORT MAP (I1 => U1_OUT, I2 => C, Y => Result);
END structural;
ABC
Result xor3_gate
I1 I2
Y I1 I2
Y
U1_OUT
PORT NAME
LOCAL WIRE NAME
ARCHITECTURE behavioral OF xor3 IS BEGIN xor3_behave: PROCESS (A, B, C) BEGIN
IF ((A XOR B XOR C) = '1') THEN Result <= '1'; ELSE Result <= '0'; END IF;
END PROCESS xor3_behave; END behavioral;
Dr. Le Dung Hanoi University of Science and Technology
Mô tả Behavioral
ABC
Result xor3_gate
Rising clock edge entity What is
port (D,Clk: in std_logic; Q: out std_logic);
end entity What;
architecture RTL of What is begin
process (D, Clk) is begin if (Clk=‘1’) then Q <= D; end if; end process;
end architecture RTL;
With a latch, not with a D-flip-flop!! When a Clk-event occurs and Clk is low, nothing happens When a Clk-event occurs and Clk is high, the D input is copied to the Q output
When a D-event occurs and Clk is high, the D input is copied to the Q output => hence a latch: when Clk is high, Q follows D
Since there is no ELSE part the previous Q value has to be remembered for the case where Clk=‘0’. The synthesis tool will hence infer a latch instead of just combinatorial logic!!!
Beware of unintended latches when ELSE parts are omitted
Dr. Le Dung Hanoi University of Science and Technology
Rising clock edge
How do we describe a rising clock edge?
Method 1: WAIT UNTIL
entity DFlipFlop is port (D,Clk: in std_logic; Q: out std_logic);
end entity DFlipFlop;
architecture RTL of DFlipFlop is begin
process is begin wait until Clk’event and Clk=‘1’; Q <= D; end process;
end architecture RTL;
This is not synthesisable
Dr. Le Dung Hanoi University of Science and Technology
Rising clock edge How do we describe a rising clock edge?
Method 2: Sensitivity list
entity DFlipFlop is port (D,Clk: in std_logic; Q: out std_logic);
end entity DFlipFlop;
architecture RTL of DFlipFlop is begin
process (D,Clk) is begin if (Clk’event and Clk=‘1’) then Q <= D; end if; end process;
end architecture RTL;
Preferred method!
Dr. Le Dung Hanoi University of Science and Technology
Rising clock edge How do we describe combinatorial circuits with registered outputs?
Method 1: WAIT UNTIL
entity RegisteredCircuit is port (A,B,C,D,Clk: in std_logic; Z: out std_logic);
end entity RegisteredCircuit;
architecture RTL of RegisteredCircuit is begin
process is begin wait until Clk’event and Clk=‘1’; -- combinatorial circuit Z <= (A and B) or (C and D); end process;
end architecture RTL;
A
B
C D
Z
‘Wait until’ has to be first line of process, followed by the description of the combinatorial circuit
Dr. Le Dung Hanoi University of Science and Technology
Rising clock edge How do we describe combinatorial circuits with registered outputs?
Method 2: Sensitivity list
entity RegisteredCircuit is port (A,B,C,D,Clk: in std_logic; Z: out std_logic);
end entity RegisteredCircuit;
architecture RTL of RegisteredCircuit is begin
process (A,B,C,D,Clk) is begin if (Clk’event and Clk=‘1’) then -- combinatorial circuit Z <= (A and B) or (C and D); end if; end process;
end architecture RTL;
A
B
C D
Z
‘if Clk’event’ has to be first line of process, with the description of the combinatorial circuit in the THEN part and with no ELSE part
Dr. Le Dung Hanoi University of Science and Technology
Rising clock edge How do we describe flip-flops with asynchronous reset?
entity DFlipFlop is port (D,Clk, Reset: in std_logic; Q: out std_logic);
end entity DFlipFlop;
architecture RTL of DFlipFlop is begin
process (D, Clk, Reset) is begin if (Reset = ‘1’) then Q <= ‘0’; elseif (Clk’event and Clk=‘1’) then Q <= D; end if; end process;
end architecture RTL;
Dr. Le Dung Hanoi University of Science and Technology
Rising clock edge How do we describe flip-flops with synchronous reset?
entity DFlipFlop is port (D,Clk, Reset: in std_logic; Q: out std_logic);
end entity DFlipFlop;
architecture RTL of DFlipFlop is begin
process (D, Clk, Reset) is begin if (Clk’event and Clk=‘1’) then if (Reset=‘1’) then Q <= 0; else Q <= D; end if; end if; end process;
end architecture RTL;
Dr. Le Dung Hanoi University of Science and Technology
Dr. Le Dung Hanoi University of Science and Technology
Mô hình Moore FSM
Present State Register
Next State function
Output function
Inputs
Present State
Next State
Outputs
clock reset
concurrent statements
process(clock, reset)
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ : Moore FSM
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
0 0
0
1
1 1
reset
VÍ DỤ : Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset) BEGIN
IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN
Moore_state <= S1; ELSE Moore_state <= S0; END IF;
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ : Moore FSM in VHDL (2) WHEN S1 =>
IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF;
WHEN S2 => IF input = ‘0’ THEN
Moore_state <= S0; ELSE
Moore_state <= S1; END IF;
END CASE; END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
Dr. Le Dung Hanoi University of Science and Technology
Dr. Le Dung Hanoi University of Science and Technology
Mô hình Mealy FSM
Next State function
Output function
Inputs
Present State Next State
Outputs
Present State Register
clock reset
process(clock, reset)
concurrent statements
VÍ DỤ : Mealy FSM
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1 reset
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ : Mealy FSM in VHDL (1) TYPE state IS (S0, S1); SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset) BEGIN
IF(reset = ‘1’) THEN Mealy_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Mealy_state IS
WHEN S0 => IF input = ‘1’ THEN
Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ : Mealy FSM in VHDL (2)
WHEN S1 => IF input = ‘0’ THEN
Mealy_state <= S0; ELSE Mealy_state <= S1; END IF;
END CASE; END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
Dr. Le Dung Hanoi University of Science and Technology
VÍ DU: Moore FSM – State diagram
C z 1 = ⁄
resetn
B z 0 = ⁄ A z 0 = ⁄ w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
Dr. Le Dung Hanoi University of Science and Technology
Present Next state Output state w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
VÍ DỤ: Moore FSM – State table
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ: Moore FSM – Building Block
Present State Register
Next State function
Output function
Input: w
Present State: y
Next State
Output: z
clock resetn
process(clock, reset)
concurrent statements
Dr. Le Dung Hanoi University of Science and Technology
USE ieee.std_logic_1164.all ;
ENTITY simple IS PORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ; END simple ;
ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ;
BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN
VÍ DỤ: Moore FSM in VHDL (1)
Dr. Le Dung Hanoi University of Science and Technology
CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ;
VÍ DỤ: Moore FSM in VHDL (2)
Dr. Le Dung Hanoi University of Science and Technology
END IF ; END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
A
w 0 = z 0 = ⁄
w 1 = z 1 = ⁄ B w 0 = z 0 = ⁄
resetn w 1 = z 0 = ⁄
VÍ DỤ: Mealy FSM - State diagram
Dr. Le Dung Hanoi University of Science and Technology
Present Next state Output z state w = 0 w = 1 w = 0 w = 1
A A B 0 0 B A B 0 1
VÍ DỤ: Mealy FSM – State table
Dr. Le Dung Hanoi University of Science and Technology
process(clock, reset)
Next State function
Output function
Input: w
Present State: y Next State
Output: z
Present State Register
clock resetn
concurrent statements
VÍ DỤ: Mealy FSM – Building Block
Dr. Le Dung Hanoi University of Science and Technology
LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ; END Mealy ;
ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ;
BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN
VÍ DỤ: Mealy FSM in VHDL code (1)
Dr. Le Dung Hanoi University of Science and Technology
VÍ DỤ: Mealy FSM in VHDL code (2)
CASE y IS WHEN A => IF w = '0' THEN
y <= A ; ELSE
y <= B ; END IF ; WHEN B => IF w = '0' THEN
y <= A ; ELSE
y <= B ; END IF ; END CASE ;
Dr. Le Dung Hanoi University of Science and Technology
END IF ; END PROCESS ;
WITH y SELECT z <= w WHEN B,
z <= ‘0’ WHEN others;
END Behavior ;
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái
Wait 00
Up1 01
Up2 10
Up3 11
Down3 11
Down2 10
Down1 01
Start=0
Start=1 Up=0
Start=1 Up=1
Up Start
Next state logic
Out put logic
State Reg
Reset Output
NextState
CurrentState
Dr. Le Dung Hanoi University of Science and Technology
Wait 00
Up1 01
Up2 10
Up3 11
Down3 11
Down2 10
Down1 01
Start=0
Start=1 Up=0
Start=1 Up=1
entity FSM is port ( Start, Up, Reset, Clk: in std_logic; Output: out std_logic_vector(0 to 1));
end entity FSM;
architecture Behav of FSM is type FSM_States = (Wait,Up1,Up2, Up3,Down1,Down2,Down3); signal CurrentState, NextState : FSM_States;
begin OutputLogic: process(CurrentState) is … end process OutputLogic;
NextStateLogic: process(CurrentState,Start,Up) is … end process NextStateLogic;
StateRegister: process(NextState,Clk,Reset) is … end process StateRegister;
end architecture Behav;
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái
Dr. Le Dung Hanoi University of Science and Technology
OutputLogic: process(CurrentState) is begin
case CurrentState is when Wait => Output <= “00”; when Up1|Down1 => Output <= “01”; when Up2|Down2 => Output <= “10”; when Up3|Down3 => Output <= “11”; end case;
end process OutputLogic;
Wait 00
Up1 01
Up2 10
Up3 11
Down3 11
Down2 10
Down1 01
Start=0
Start=1 Up=0
Start=1 Up=1
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái
Dr. Le Dung Hanoi University of Science and Technology
NextStateLogic: process(CurrentState,Start,Up) is begin
case CurrentState is when Wait => if (Start=‘0’) then NextState <= Wait; elseif (Up=‘1’) then NextState <= Up1; else NextState <= Down3; end if; when Up1 => NextState <= Up2; when Up2 => NextState <= Up3; when Up3|Down1 => NextState <= Wait; when Down3 => NextState <= Down2; when Down2 => NextState <= Down1; end case;
end process NextStateLogic;
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái
Wait 00
Up1 01
Up2 10
Up3 11
Down3 11
Down2 10
Down1 01
Start=0
Start=1 Up=0
Start=1 Up=1
Dr. Le Dung Hanoi University of Science and Technology
StateRegister: process(NextState,Clk,Reset) is begin
if Reset=‘1’ then CurrentState <= Wait; elseif (Clk’event and Clk=‘1’) then CurrentState <= NextState; end if;
end process StateRegister;
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái
Wait 00
Up1 01
Up2 10
Up3 11
Down3 11
Down2 10
Down1 01
Start=0
Start=1 Up=0
Start=1 Up=1
Dr. Le Dung Hanoi University of Science and Technology
Dr. Le Dung Hanoi University of Science and Technology