vlsi record 6th sem nit trichy
TRANSCRIPT
NATIONAL INSTITUTE OF TECHNOLOGY
TIRUCHIRAPALLI- 620015
LABORATORY RECORD
Certified Bonafide Record of work done by
………………………………………………………………………………………………………….
Class ………………………………............ Roll No …….....……………………………....
University Examination ……………………………………………………………...…
Registration No ...............……………………. Year ……...............………………..
Staff Incharge Head of the department
Internal Examiner External Examiner
INDEX
Expt. No. Date Experiment
Page No. Marks
1 12-01-
2012 Half Adder, Full Adder, Half Subtractor, Full Subtractor 3
2 18-01-
2012 Multiplexer and Demultiplexer 27
3 02-02-
2012 Working with RAM 38
4 09-02-
2012 Comparators, Parity Generator and ALU 41
5 21-02-
2012 Counters and shift registers 55
6 06-03-
2012 Carry Look Ahead Adder, Braun-Array Multiplier, FIR Filter 60
EXPERIMENT 1
Half Adder, Full Adder, Half Subtractor, Full Subtractor
Aim:
To design and implement
a.Half adder b.Half subtractor
c.Full adder d.Full subtractor
Tool Required: Altera Quartus II
Code:
Half adder (functional)
Code:
module half_adders (s,c,a,b);
output s,c;
input a,b;
xor(s,a,b);
and(c,a,b);
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Half adder
Structural:
module half(s,c,a,b);
output s,c;
input a,b;
wire s,c,a,b;
assign s=a^b;
assign c=a&b;
endmodule
Compilation Report:
Simulation Report:
RTL Viewer::
Half adder(data flow)
Code:
module ha1(s,c,x,y);
input x,y;
output s,c;
assign {c,s}=x+y;
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Full adder
Code:
module fulladd (sum,cout,in1,in2,cin);
output sum,cout;
input in1,in2,cin;
wire sum,cout,in1,in2,cin;
wire i1,i2,i3;
half ha1(i1,i2,in1,in2);
half ha2(sum,i3,i1,cin);
assign cout=i2||i3;
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Full subtractor
Code:
module full_sub(d,bo,a,b,b1);
output d,bo;
input a,b,b1;
assign d=a^b^b1;
assign bo=((~a)&(b|b1))|(b&b1);
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Half subractor(funtional)
Code:
module half_subs (d,b0, a, b);
output d, b0;
input a,b;
wire abar;
not(abar,a);
xor (d, a, b);
and(b0,abar,b);
endmodule
Compilaion Report:
Simulation Report:
RTL Viewer:
Half adder(behavioural)
module ha1(s,c,x,y);
input x,y;
output reg s,c;
always
begin
{c,s}=x+y;
end
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Full subtractor(behavioural)
Code:
module hs2(d,b,x,y);
input x,y;
output reg d,b;
always @(x or y)
begin
{b,d}=x-y;
end
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Half subtractor(data flow)
Code:
module hs1(d,b,x,y);
input x,y;
output d,b;
assign {b,d}=x-y;
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Full adder(behavioural)
Code:
module fa3(s,c,x,y,z);
input x,y,z;
output reg s,c;
always
begin
{c,s}=x+y+z;
end
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Full subractor (behavioural)
Code:
module f3(d,b,x,y,z);
input x,y,z;
output reg d,b;
always
begin
{b,d}=x-y-z;
end
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Full subtractor(using half subtractor)
Code:
module fs1(d,b,x,y,z);
input x,y,z;
output d,b;
wire do,bo,b1;
hs1 h1(do,bo,x,y);
hs1 h2(d,b1,do,z);
or o1(b,bo,b1);
endmodule
Compilation Report:
Simulation Report:
RTL Viewer:
Result:
Half adder, full adder, half subtractor, full subtractor was implemented using Verilog HDL.
Experiment 2
Multiplexer and De-multiplexer
Aim:
To design and implement the following:
1. 4:1 mux
2. 16:1 mux
3. 1:4 demux
4. 1:16 demux
Tools Required:
Quartus II 9.2
1. 4:1 mux
Code:
module mux41(s,i,y);
output y;
input [1:0]s;
input [3:0]i;
reg y;
always @(s or i)
case(s)
2'b00:y=i[0];
2'b01:y=i[1];
2'b10:y=i[2];
2'b11:y=i[3];
default: y=0;
endcase
endmodule
Compilation Report:
Simulation:
RTL View:
2. 16:1 mux
Code:
module mux16(s,i,y);
output y;
input s,i;
wire [0:3]j;
wire [0:3]s;
wire [0:15]i;
mux41(s[2:3],i[0:3],j[0]);
mux41(s[2:3],i[4:7],j[1]);
mux41(s[2:3],i[8:11],j[2]);
mux41(s[2:3],i[12:15],j[3]);
mux41(s[0:1],j[0:3],y);
endmodule
Compilation Report:
Simulation:
RTL View:
3. 1:4 demux
Code:
module demux1x4(s0,s1,i,o0,o1,o2,o3);
output o0,o1,o2,o3;
input s0,s1,i;
wire o0, o1, o2, o3;
wire sn0,sn1;
not (sn0,s0);
not(sn1, s1);
and (o0, i, sn1, sn0);
and (o1, i, sn1, s0);
and (o2, i, s1, sn0);
and (o3, i, s1, s0);
endmodule
Compilation Report:
Simulation:
RTL View:
4. 1:16 demux
Code:
module demux1_1x16(s,i,o);
output o;
input s,i;
wire [0:15]o;
wire [0:3]s;
wire [0:3]j;
demux1x4(s[2],s[3],i,j[0],j[1],j[2],j[3]);
demux1x4(s[0],s[1], j[0], o[0], o[1], o[2], o[3]);
demux1x4(s[0],s[1], j[1], o[4], o[5], o[6], o[7]);
demux1x4(s[0],s[1], j[2], o[8], o[9], o[10], o[11]);
demux1x4(s[0],s[1], j[3], o[12], o[13], o[14], o[15]);
endmodule
Compilation Report:
Simulation:
RTL View:
Problem Statement:
5:1 Mux using 2:1 Mux
module mux51(y,s,i);
input [4:0]i;
input [2:0]s;
output y;
wire [2:0]t;
mux21 m1(t[0],s[0],i[1],i[0]);
mux21 m2(t[1],s[0],i[3],i[2]);
mux21 m3(t[2],s[1],t[0],t[1]);
mux21 m4(y,s[2],i[4],t[2]);
endmodule
module mux21(y,i0,i1,s);
input s,i0,i1;
output y;
wire a,b,c;
not (a,s);
and (c,a,i0);
and (b,s,i1);
or (y,b,c);
endmodule
Compilation Report:
Simulation :
RTL View:
result :
The Verilog HDL code was written, simulated and verified for the following:
1. 4:1 mux
2. 16:1 mux
3. 1:4 demux
4. 1:16 demux
A 5:1 MUX was realized using four 2:1 MUX in Verilog HDL and verified.
Experiment No 3
WORKING WITH RAM
AIM:
To generate a 3-port RAM using the Megacore utility available in ALtera Quartus II and to build an
accumulator using the RAM which stores the sum of two locations in the RAM in a third location
TOOLS REQUIRED:
Altera Quartus II
CODE :
module fa ( a,b,c_out,s);
input [7:0]a;
input [7:0]b;
output [7:0]s;
output c_out;
assign {c_out,s}=a+b;
endmodule
SCHEMATIC REPRESENTATION:
COMPILATION REPORT:
SIMULATION REPORT:
Result: A 3-port RAM using MEGA Core utility is generated on Altera Quartus II and an accumulator
using RAM storing sum of 2 no. in 3rd location is built and verified using waveform.
Experiment 4
Comparators, Parity Generator and ALU
Aim:
To design and implement the following:
5. Comparator
6. ALU
7. Parity Generator
Tools Required:
Xilinx ISE Software
5. Comparator
Code:
module comparator(a, b, out);
input [3:0] a;
input [3:0] b;
output reg [2:0] out;
always @(*)
begin
if (a>b)
out=3'b100;
else if (a<b)
out=3'b001;
else
out=3'b010;
end
endmodule
Synthesis Report:
---- Source Parameters
Input File Name : "comparator.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "comparator"
Output Format : NGC
Target Device : Automotive 9500XL
---- Source Options
Top Module Name : comparator
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : comparator.lso
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=====================================================================
====
* HDL Compilation *
=====================================================================
====
WARNING:HDLCompilers:176 - Include directory \Documents and
Settings\owner\Desktop\xilinx1\acpcs\ does not exist
Compiling verilog file "C:/Documents and
Settings/owner/Desktop/xilinx1/acpcs/comparator.v" in library work
Module <comparator> compiled
No errors in compilation
Analysis of file <"comparator.prj"> succeeded.
=====================================================================
====
* Design Hierarchy Analysis *
=====================================================================
====
Analyzing hierarchy for module <comparator> in library <work>.
=====================================================================
====
* HDL Synthesis *
=====================================================================
====
Performing bidirectional port resolution...
Synthesizing Unit <comparator>.
Related source file is "C:/Documents and
Settings/owner/Desktop/xilinx1/acpcs/comparator.v".
Found 4-bit comparator greater for signal <out$cmp_gt0000> created at line 27.
Found 4-bit comparator less for signal <out$cmp_lt0000> created at line 29.
Summary:
inferred 2 Comparator(s).
Unit <comparator> synthesized.
=====================================================================
====
HDL Synthesis Report
Macro Statistics
# Comparators : 2
4-bit comparator greater : 1
4-bit comparator less : 1
=====================================================================
====
* Advanced HDL Synthesis *
Advanced HDL Synthesis Report
Found no macro
=====================================================================
====
* Low Level Synthesis *
=====================================================================
====
Optimizing unit <comparator> ...
=====================================================================
====
* Partition Report *
=====================================================================
====
Partition Implementation Status
=====================================================================
* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : comparator.ngr
Top Level Output File Name : comparator
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
RTL View:
Simulation Report:
6. ALU
Code:
module alu(a, b, select, alu_out);
input [3:0] a;
input [3:0] b;
input [2:0] select;
output reg [7:0] alu_out;
always @(select[0] or select[1 ] or select[2])
case ({select[0], select[1 ], select[2]})
3'b000:alu_out=a+b;
3'b001:alu_out=a-b;
3'b010:alu_out=a*b;
3'b011:alu_out=a&b; //bit wise and
3'b100:alu_out=a|b; //bit wise or
3'b101:alu_out=a^b; //xor
3'b110:alu_out=a<<1; //left shift
3'b111:alu_out=b>>1; //right shift
endcase
endmodule
Synthesis Report:
---- Source Parameters
Input File Name : "alu.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "alu"
Output Format : NGC
Target Device : Automotive 9500XL
---- Source Options
Top Module Name : alu
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : alu.lso
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
RTL View:
Simulation Report:
7. Parity Generator
Code:
module parity_gen(a, par);
input [7:0] a;
output reg par;
//odd parity
always @(*)
par=(~(^a));
endmodule
Synthesis Report:
---- Source Parameters
Input File Name : "parity_gen.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "parity_gen"
Output Format : NGC
Target Device : Automotive 9500XL
---- Source Options
Top Module Name : parity_gen
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : parity_gen.lso
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=====================================================================
====
=====================================================================
====
* HDL Compilation *
=====================================================================
====
WARNING:HDLCompilers:176 - Include directory \Documents and
Settings\owner\Desktop\xilinx1\acpcs\ does not exist
Compiling verilog file "C:/Documents and
Settings/owner/Desktop/xilinx1/acpcs/parity_gen.v" in library work
Module <parity_gen> compiled
No errors in compilation
Analysis of file <"parity_gen.prj"> succeeded.
* Design Hierarchy Analysis *
=====================================================================
====
Analyzing hierarchy for module <parity_gen> in library <work>.
* HDL Analysis *
=====================================================================
====
Analyzing top module <parity_gen>.
Module <parity_gen> is correct for synthesis.
* HDL Synthesis *
=====================================================================
====
Performing bidirectional port resolution...
Synthesizing Unit <parity_gen>.
Related source file is "C:/Documents and
Settings/owner/Desktop/xilinx1/acpcs/parity_gen.v".
Found 1-bit xor8 for signal <par$xor0000> created at line 26.
Unit <parity_gen> synthesized.
=====================================================================
====
HDL Synthesis Report
Macro Statistics
# Xors : 1
1-bit xor8 : 1
* Advanced HDL Synthesis *
=====================================================================
====
=====================================================================
====
Advanced HDL Synthesis Report
Macro Statistics
# Xors : 1
1-bit xor8 : 1
* Low Level Synthesis *
=====================================================================
====
Optimizing unit <parity_gen> ...
=====================================================================
====
* Partition Report *
=====================================================================
====
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=====================================================================
====
* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : parity_gen.ngr
Top Level Output File Name : parity_gen
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
RTL View:
Simulation Report:
8. Extra Problem Statement
module extra(s1, s2, b, o, m, a);
input [3:0] s1;
input [3:0] s2;
input [7:0] b;
output reg [15:0] o;
output [2:0] m;
input [7:0] a;
comparator c(s1,s2,m);
alu a1(a,b,m,o);
endmodule
Synthesis Report:
---- Source Parameters
Input File Name : "extra.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "extra"
Output Format : NGC
Target Device : Automotive 9500XL
---- Source Options
Top Module Name : extra
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : extra.lso
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
Simulation Report:
Result:
1. Verilog HDL Code was written and simulated for the following:
a) Comparator b) Parity Generator c) ALU in Xilinx ISE.
2. Verilog Code was written and simulated for the given problem
and verified in Xilinx ISE.
Experiment 5
Counters and shift registers
Aim:
To simulate and synthesize Verilog HDL programming using Xilinx for the following:
1. Decade counter
2. Ripple counter
3. SISO
4. PIPO
Tools Required:
Xilinx-ISE
1. Decade counter
Code:
module decadecounter(clk,Q);
input clk;
output reg [3:0] Q=0;
always @(posedge clk)
begin
Q=Q+1;
if(Q==10)Q=0;
end
endmodule
Simulation Report:
2. Ripple counter:
Code:
module rc(clk,o,up);
input clk,up;
output reg [3:0] o=0;
always @(posedge clk)
begin
if(up==1)
begin
o=o+1;
end
else
begin
o=o-1;
end
end
endmodule
Simulation report:
3. SISO
Code:
module siso(i,clk,o);
input clk,i;
output reg o;
reg[3:0] p;
always@(posedge clk)
begin
o=p[3];
p[3]=p[2];
p[2]=p[1];
p[1]=p[0];
end
endmodule
Simulation report:
4.PIPO:
Code:
module pipo(i,clk,o);
input i,clk;
output reg o;
always@(posedge clk)
o=i;
endmodule
Simulation report:
Result:
The following were designed and implemented :
1. Decade counter
2. Ripple counter
3. SISO
4. PIPO
EXPERIMENT NO. 6
Carry Look Ahead Adder, Braun-Array Multiplier, FIR Filter
AIM: To simulate and synthesize Verilog HDL program for the following
1. CARRY LOOK AHEAD ADDER 2. BRAUN- ARRAY MULTIPLIER 3. FIR FILTER
TOOLS REQUIRED: Xilinx- ISE 9.2
CODE:
CARRY LOOK AHEAD ADDER
module carry_ahead (a,b, ci, s,co);
input [3:0] a;
input [3:0] b;
input ci;
output [3:0] s;
output co;
wire [9:0] x;
wire [3:0] p;
wire [3:0]g;
wire [2:0] y;
hf ha1( a[0], b[0], p[0], g[0]);
hf ha2( a[1], b[1], p[1], g[1]);
hf ha3( a[2], b[2], p[2], g[2]);
hf ha4( a[3], b[3], p[3], g[3]);
xor ( s[0], ci, p[0]);
and (x[0], ci, p[0]);
or( y[0], x[0], g[0]);
xor( s[1], y[0], p[1]);
and (x[1], p[1], p[0],ci);
and ( x[2], p[1], g[0]);
or ( y[1], x[1], x[2], g[1]);
xor( s[2], y[1], p[2]);
and (x[3], p[0], p[1], p[2], ci);
and ( x[4], p[1], p[2], g[0]);
and (x[5], p[2], g[1]);
or (y[2], x[3], x[4], x[5], g[2]);
xor (s[3], y[2], p[3]);
and (x[6], p[0], p[1],p[2], p[3], ci);
and ( x[7], p[1], p[2], p[3], g[0]);
and (x[8], p[2], p[3], g[1]);
and (x[9], p[3], g[2]);
or (co, x[6], x[7], x[8], x[9], g[3]);
endmodule
module hf( a, b, s, c);
input a,b;
output c, s;
xor( s, a,b);
and (c, a,b);
endmodule
SIMULATION
BRAUN ARRAY MULTIPLIER
CODE:
module braun_mul( a, b, p);
input [3:0] a;
input [3:0] b;
output [7:0] p;
wire [10:0] c;
wire [14:0] d;
wire s, s1, s2, s3, s4, s5;
and( p[0], a[0], b[0]);
and ( d[0], a[1], b[0]);
and (d[1], a[0], b[1]);
and( d[2], a[2], b[0]);
and (d[3],a[1], b[1]);
and (d[4],a[0], b[2]);
and (d[5],a[3], b[0]);
and (d[6],a[2], b[1]);
and (d[7],a[1], b[2]);
and (d[8],a[0], b[3]);
and (d[9],a[3], b[1]);
and (d[10],a[2], b[2]);
and (d[11],a[1], b[3]);
and (d[12],a[3], b[2]);
and (d[13],a[2], b[3]);
and (d[14],a[3], b[3]);
fa f1( p[1], c[0], d[0], d[1], 0);
fa f2( s, c[1], d[2], d[3], 0);
fa f3(p[2], c[2], s, d[4], c[0]);
fa f4( s1, c[3], d[5], d[6], 0);
fa f5( s2, c[4], s1, d[7], c[7]);
fa f6 (p[3], c[5], s2, d[8], c[2]);
fa f7( s3, c[6], d[9], d[10], c[3]);
fa f8( s4, c[7], s3, d[11], c[4]);
fa f9( p[4], c[8], s4, 0, c[5]);
fa f10(s5, c[9], d[12], d[13], c[6]);
fa f11 (p[5], c[10], s5, c[8], c[7]);
fa f12 (p[6], p[7], d[14], c[7], c[10]);
endmodule
module fa(sum, co, a,b ,ci);
input a, b, ci;
output sum, co;
wire c1, c2, c3;
xor( sum, a,b, ci);
and (c1, a,b);
and (c2, ci, b);
and (c3, a, ci);
or(co, c1, c2, c3);
endmodule
SIMULATION
FIR FILTER
CODE:
module filter(x, a, b, c, y, clk);
input [3:0]x;
input [3:0]a;
input [3:0]b;
input [3:0]c;
input clk;
output reg [8:0] y;
reg [3:0] xn=0;
reg [3:0] xn_1=0;
wire [7:0] p1;
wire [7:0] p2;
wire [7:0] p3;
wire [7:0] s1;
wire [7:0] s2;wire [8:0] out;
wire [8:0] oo;
braun_mul b1 ( x, a, p1);
braun_mul b2 (xn, b, p2);
braun_mul b3( xn_1, c, p3);
assign out= p1+p2;
assign oo= p3+out;
always@ ( posedge clk)
begin
xn_1<= xn;
xn<= x;
y<= oo;
end
endmodule
SIMULATION
RESULT:
The following were synthesized and simulated using Verilog HDL
CARRY LOOK AHEAD ADDER
BRAUN- ARRAY MULTIPLIER
FIR FILTER