von neumann architecture - thammasat · pdf fileavr microcontrollers architecture some...

AVR Microcontrollers Architecture

AV

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ller

s A

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Th

ere

are

two

fu

nd

amen

tal

arch

itec

ture

s to

acc

ess

mem

ory

1.

Vo

n N

eum

ann

Arc

hit

ectu

re

2.

Har

var

d A

rch

itec

ture

2

Von N

eum

ann A

rchi

tectu

re

3

Th

ere

are

two

fu

nd

amen

tal

arch

itec

ture

s to

acc

ess

mem

ory

.

Joh

n V

on

Neu

man

n's

: O

ne

shar

ed m

emo

ry f

or

inst

ruct

ion

s (p

rog

ram

) an

d

dat

a w

ith

on

e d

ata

bu

s an

d o

ne

add

ress

bu

s b

etw

een

pro

cess

or

and

mem

ory

. In

stru

ctio

ns

and

dat

a h

ave

to b

e fe

tch

ed i

n s

equ

enti

al o

rder

(kn

ow

n a

s th

e V

on

Neu

man

Bo

ttle

nec

k),

lim

itin

g t

he

op

erat

ion

ban

dw

idth

.

Its

des

ign

is

sim

ple

r th

an t

hat

of

the

Har

var

d a

rch

itec

ture

. It

is

mo

stly

use

d

to i

nte

rfac

e to

ex

tern

al m

emo

ry.

Harv

ard A

rchi

tectu

re

Th

e te

rm o

rig

inat

ed f

rom

th

e H

arv

ard

Mar

k 1

rel

ay-b

ased

co

mp

ute

r, w

hic

h s

tore

d

4

Th

e te

rm o

rig

inat

ed f

rom

th

e H

arv

ard

Mar

k 1

rel

ay-b

ased

co

mp

ute

r, w

hic

h s

tore

d

inst

ruct

ion

s o

n p

un

ched

tap

e an

d d

ata

in r

elay

lat

ches

.

Har

var

d A

rch

itec

ture

: T

he

Har

var

d a

rch

itec

ture

use

s p

hysi

call

y s

epar

ate

mem

ori

es f

or

thei

r

inst

ruct

ion

s an

d d

ata,

req

uir

ing

ded

icat

ed b

use

s fo

r ea

ch o

f th

em.

Inst

ruct

ion

s an

d o

per

and

s

can

th

eref

ore

be

fetc

hed

sim

ult

aneo

usl

y.

Dif

fere

nt

pro

gra

m a

nd

dat

a b

us

wid

ths

are

po

ssib

le,

allo

win

g p

rog

ram

an

d d

ata

mem

ory

to

be

bet

ter

op

tim

ized

to

th

e ar

chit

ectu

ral

req

uir

em

ents

. E

.g.:

If

the

inst

ruct

ion

fo

rmat

req

uir

es

14

bit

s th

en p

rog

ram

bu

s an

d m

em

ory

can

be

mad

e 1

4-b

it w

ide,

wh

ile

the

dat

a b

us

and

dat

a m

em

ory

rem

ain

8-b

it w

ide.


Som

e Adv

ance

d Micr

ocon

trolle

rs

8-b

it m

icro

co

ntr

oll

er

–A

tme

l A

VR

(A

Tm

eg

a8

)

16

-bit

mic

roc

on

tro

lle

r –

Inte

l M

CS

-96

32

-bit

mic

roc

on

tro

lle

r –

AR

M m

icro

co

ntr

oll

er

PIC

Mic

roc

on

tro

lle

r –


5

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ARM

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18

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21

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22

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f 8051.

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ab

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Stat

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Bit

7–

I: G

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al

Inte

rru

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En

ab

le

Th

e G

lob

al I

nte

rru

pt

En

able

bit

mu

st b

e se

t fo

r th

e in

terr

up

ts t

o b

e en

able

d. T

he

ind

ivid

ual

inte

rru

pt

enab

le c

on

tro

l is

th

en p

erfo

rmed

in

sep

arat

e co

ntr

ol

reg

iste

rs.

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he

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bal

In

terr

up

t

En

able

Reg

iste

r is

cle

ared

, n

on

e o

f th

e in

terr

up

ts a

re e

nab

led

in

dep

end

ent

of

the

ind

ivid

ual

inte

rru

pt

enab

le s

etti

ng

s. T

he

I-b

it i

s cl

eare

d b

y h

ard

war

e af

ter

an i

nte

rru

pt

has

occ

urr

ed,

and

is

set

by t

he

RE

TI

inst

ruct

ion

to

en

able

su

bse

qu

ent

inte

rru

pts

. T

he

I-b

it c

an a

lso

be

set

and

cle

ared

by

the

app

lica

tio

n w

ith

th

e S

EI

and

CL

I in

stru

ctio

ns,

as

des

crib

ed i

n t

he

Inst

ruct

ion

Set

Ref

eren

ce.

• B

it6

–T

: B

it C

op

y S

tora

ge


26

• B

it6

–T

: B

it C

op

y S

tora

ge

Th

e B

it C

op

y i

nst

ruct

ion

s B

LD

(B

it L

oaD

) an

d B

ST

(B

it S

To

re)

use

th

e T

-bit

as

sou

rce

or

des

tin

atio

n f

or

the

op

erat

ed b

it. A

bit

fro

m a

reg

iste

r in

th

e R

egis

ter

Fil

e ca

n b

e co

pie

d i

nto

T b

y

the

BS

T i

nst

ruct

ion

, an

d a

bit

in

T c

an b

e co

pie

d i

nto

a b

it i

n a

reg

iste

r in

th

e R

egis

ter

Fil

e b

y t

he

BL

D i

nst

ruct

ion

.

• B

it5

–H

: H

alf

Ca

rry

Fla

g

Th

e H

alf

Car

ry F

lag

H i

nd

icat

es a

Hal

f C

arry

in

so

me

arit

hm

etic

op

erat

ion

s. H

alf

Car

ry i

s u

sefu

lin

BC

D a

rith

meti

c.

See

th

e “In

stru

ctio

n S

et D

escr

ipti

on

” fo

r d

etai

led

in

form

atio

n.

Stat

us R

egist

er

• B

it 4

–S

: S

ign

Bit

, S

= N

⊕V

Th

e S

-bit

is

alw

ays

an e

xcl

usi

ve

or

bet

wee

n t

he

Neg

ativ

e F

lag

N a

nd

th

e T

wo

’s C

om

ple

men

t

Ov

erfl

ow

Fla

g V

. S

ee t

he

“In

stru

ctio

n S

et D

escr

ipti

on

” fo

r d

etai

led

in

form

ati

on

.

• B

it 3

–V

: T

wo

’s C

om

ple

men

t O

ver

flo

w F

lag

Th

e T

wo

’s C

om

ple

men

t O

ver

flo

w F

lag

V s

up

po

rts

two

’s c

om

ple

men

t ar

ith

met

ics.

See

th

e

“In

stru

ctio

n S

et D

escr

ipti

on

” fo

r d

etai

led

in

form

atio

n.

• B

it 2

–N

: N

egat

ive

Fla

g

27

• B

it 2

–N

: N

egat

ive

Fla

g

Th

e N

egat

ive

Fla

g N

in

dic

ates

a n

egat

ive

resu

lt i

n a

n a

rith

meti

c o

r lo

gic

op

erat

ion

. S

ee t

he

“In

stru

ctio

n S

et D

escr

ipti

on

” fo

r d

etai

led

in

form

atio

n.

• B

it 1

–Z

: Z

ero

Fla

g

Th

e Z

ero

Fla

g Z

in

dic

ates

a z

ero

res

ult

in

an

ari

thm

etic

or

log

ic o

per

atio

n.

See

th

e “In

stru

ctio

n

Set

Des

crip

tio

n”

for

det

aile

d i

nfo

rmat

ion

.

• B

it 0

–C

: C

arry

Fla

g

Th

e C

arry

Fla

g C

in

dic

ates

a C

arry

in

an

ari

thm

etic

or

log

ic o

per

atio

n.

See

th

e “In

stru

ctio

n S

et

Des

crip

tio

n”

for

det

aile

d i

nfo

rmat

ion

.


STAC

KAN

DST

ACK

POIN

TER

�S

tack

ma

y b

e l

oca

ted

an

yw

he

re

wit

hin

up

pe

r 1

02

4

by

tes o

f S

RA

M. L

ow

er 9

6 b

yte

s (

re

gis

ter a

re

a)

mu

st

no

t b

e o

ccu

pie

d b

y s

tack

.

�1

6-b

it s

tack

po

inte

r c

on

tain

s t

wo

8-b

it r

eg

iste

rs,

SP

H a

nd

SP

L.

�P

US

H c

om

ma

nd

de

cre

ase

s t

he

sta

ck

po

inte

r a

nd


28

�P

US

H c

om

ma

nd

de

cre

ase

s t

he

sta

ck

po

inte

r a

nd

PO

P c

om

ma

nd

in

cre

ase

s i

t.

�In

ge

ne

ra

l, t

he

sta

ck

po

inte

r t

o b

e i

nit

iali

ze

d b

y t

he

hig

he

st

ad

dre

ss o

f S

RA

M.


SPH

and S

PL d

Stac

k Poin

ter H

igh an

d Low

Reg

ister AVR Microcontrollers Architecture

29


Stac

k Poin

ter In

struc

tions


30


POW

ERM

ANAG

EMEN

T AND

SLEE

PM

ODES

�A

Tm

eg

a8

off

ers f

ive

sle

ep

mo

de

s f

or

eff

icie

nt

po

we

r m

an

ag

em

en

t. T

he

y a

re

:

�Id

le m

od

e

�A

DC

no

ise

re

du

cti

on

mo

de

�P

ow

er-d

ow

n m

od

e

Po

we

r-s

av

e m

od

e, a

nd


31

�P

ow

er-s

av

e m

od

e, a

nd

�S

tan

db

y m

od

e.

�S

LE

EP

in

str

ucti

on

ev

ok

es t

he

sle

ep

mo

de

.


SYST

EMRE

SET

�Fo

ur so

urce

s of r

eset

for A

Tmeg

a8 ar

e:

�Po

wer-o

n res

et

�Ex

terna

l res

et

�W

atch

dog r

eset,

and


32

Wat

chdo

g res

et, an

d

�Br

own-

out r

eset.

�Al

l I/O

regis

ters a

re in

itiali

zed a

nd ex

ecut

ion st

arts

from

the

rese

t vec

tor.

�M

CUCS

R re

gister

hold

s the

info

rmat

ion ab

out t

he so

urce

of

rese

t.


WAT

CHDO

GTI

MER

�Op

erated

by a

separa

te int

ernal

oscil

lator

of 1 M

Hz fr

eque

ncy.

�M

ay be

enab

led or

disab

led th

rough

its re

gister

WDT

CR.

�Ge

nerat

es sy

stem

reset

at ter

mina

l cou

nt.�

Usefu

l to av

oid xh

angin

gy sy

stem.


33

Usefu

l to av

oid xh

angin

gy sy

stem.

�To

be lo

aded

perio

dicall

y to a

void

syste

m res

et.


Syste

m C

lock a

nd C

lock O

ption

sAVR Microcontrollers Architecture

34


Syste

m C

lock a

nd C

lock O

ption

s

Cloc

k sou

rce ca

n be s

electe

d via

I/O re

gister


35

•Cl

ock s

ource

can b

e sele

cted v

ia I/O

regis

ter•

Chan

ging c

lock s

ource

requ

ires t

ime t

o stab

ilize f

reque

ncy

•Ad

justin

g cloc

k freq

uenc

y mak

es tra

de-of

f betw

een p

rocess

ingpo

wer a

nd po

wer c

onsu

mptio

n

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