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ategory: SOCcentral Feature Articles & Columns: Featur e Artic les: Tuesday, June 22, 2010

Using Dynamic and Static Power Rail Analysis to Maximize

Results with M inimum Effort  Featured

Contributor: Cadence Design Systems, Inc.

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une 26, 2006 -- Knowing where and how to apply power rail analysis can save a great deal of timen power planning and verification. Several key concepts can help, beginning with an understandingf appropriate uses for dynamic and static rail analysis. While both types of analysis deal with IRrop, they differ in important ways, and understanding the differences is vital to getting workingilicon.

his article provides a quick overview of these dynamic/static differences as well as offering a numberf other methodology tips for power verification. The goal is to make sure your power verification

methodology really does provide the verification you need, while eliminating unnecessary verificationwork.

he first rule of thumb is to remember that analysis is not the solution. Fixing the problem is theolution. By focusing on meaningful design fixes — rather than some arbitrary level of "clean"nalysis results — you get the solutions you need faster.

Dynamic or static analysis?

tatic power rail analysis evaluates the IR drop caused by high average currents flowing through aesign’ s resistive power rails and generates the familiar plot shown in Figure 1. This type of powerail analysis has traditionally been used as a signoff analysis at technology nodes above 130nm,

where sufficient natural decoupling capacitance from the power network and non-switching logicames most dynamic transients.

Dynamic analysis evaluates the IR drop caused when large amounts of circuitry switchimultaneously, causing peak current demand on the power rails. This current demand can be highlyocalized and brief — within a single clock cycle, and can result in an IR drop that causes additionaletup- or hold-time violations. Typically, high IR drop on clock networks causes hold-time violations,

while IR drop on signal nets causes setup-time violations.here is no fixed relationship between static and dynamic IR drop in a design. The peak current

waveforms used in dynamic analysis are determined by understanding when circuitry switches andhe switching circuitry’ s electrical characteristics. As a result, these dynamic waveforms are mostlyndependent of clock frequency.

n contrast, the average currents used in static analysis are calculated over a period of time, typicallyclock cycle, and so vary with clock frequency. In the example shown in Figure 2, the same cellperating at different clock frequencies has different values for average current, but the peak current

waveform remains constant.

Figure 1. An example plot of static IR drop show s large areas wherethe VDD pow er rail differs significantly from the nominal voltage.Such differences are truly significant w hen they prevent the designfrom meeting timing. 

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Dynamic and static in the flow

Dynamic analysis starts to become important for designs at 130nm and below. This type of analysiss, therefore, relatively new when compared to static analysis, which has been used for signoff forome time. For today’ s designs, both static and dynamic analysis should be utilized from initial

oorplanning (power planning) through to sign-off, as indicated in the design flow overview in Figure.

mportant points to consider when determining your methodology for power rail analysis include:

sing only a dynamic approach to understand your design’ s IR drop is not a wise designmethodology. If you use only dynamic analysis, you could fight a losing battle throwing de-caps athe big red spot on your IR drop display that is actually caused by poor power rail sizing. Staticnalysis enables you to detect the cause of the IR drop without confusion.

Most advanced standard cell libraries include a number of differently sized filler cells, and associatede-cap cells that have the same footprint. Once dynamic analysis has shown that additional de-caps

re required, the first approach for adding the additional capacitance is to swap filler cells for de-capells. If cell swapping does not give you enough de-cap cells, you may face major re-work on yourmplementation to add the required de-caps.

he challenge in trying to correct dynamic IR drop problems late in the design flow is that the de-capsequired to correct dynamic IR drop may require increased space on silicon, which may not bevailable if your routing utilization is high. Under these circumstances, it makes sense to performynamic analysis to optimize de-cap size and location as early as possible in your design flow toreserve” the required area up-front.

On the other hand, if your routing utilization is lower, you may have room to add de-caps later in theow. In fact, with loose utilization and using mainstream technology nodes, you might be able to getway without initial power planning to reserve the room for additional de-caps, since swapping filler

Figure 2. Static power is calculated by averaging current across atime period, which depends on frequency. Dynamic power isassociated with clock edges, so the dynamic current waveform doesnot change with frequency.

Figure 3. This simplified low-power flow indicatesthe main stages of design where static and dynamicrail analyses are valuable. 

l Use static analysis to generate robust power rails (widths, vias, etc.).

l Use dynamic analysis to optimize the insertion of de-coupling capacitance.

l Use static analysis to optimize power switch sizes to minimize IR drop.

l Use dynamic power-up analysis to optimize power switch sizes to control power-up ramp

time.

l Use both static and dynamic analysis early and late in the design flow.

l Establish IR drop limits based on understanding how IR drop can affect timing.

l Try to optimize for decoupling capacitors early in the flow, since late optimization for de-caps

can lead to major re-work.

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ells for de-cap cells may address all of your needs. As with many design tradeoffs, though, puttingff dynamic analysis until signoff increases project risk.

Good static analysis practices

arly in the design, use static analysis to ensure that your rails are wide enough. Static analysisequires less design data to be completed, so you can run this analysis after placement and prior toignal routing.

very design suffers from IR drop; the question is whether the IR drop causes the design to fail. It isnusual to see IR drop force the operating voltage so low that a block totally fails. It is much morekely that IR drop causes timing or SI noise issues. With these effects in mind, IR drop limits shoulde determined from a sound engineering approach based on understanding how IR drop can affectming and SI noise — and not just by simple guesswork. When IR drop causes timing problems,emember that you can either fix the timing or the IR drop.

o make sure that your analysis results are accurate in the first place, remember to account formanufacturing effects. Variations in power rail resistance play a direct role in determining the amountf IR drop along the rail, so bear in mind that the rails you draw get modified to suit the processechnology. Specifically, chemical/mechanical polishing (CMP) smoothes the top of the metal and

rodes (wears away) copper more than aluminum. Slotting, the methodology of inserting tall columnsf dielectric into wide areas of metal, helps prevent this erosion. To help mitigate the impact of rosion, most advanced process technologies have tightened up their requirements for slotting, nowequiring slots at smaller widths of metal.

Good dynamic analysis practices

One concern with running any kind of rail analysis in the design-planning stage is that good testectors are not yet available for the entire design. Vectors are often available at the block level,owever, and they provide a good place to start dynamic analysis.

When vectors are available, they usually aim at toggling nodes for functional verification, so usengineering judgment to assess how well these vectors simulate realistic power-consumptionehavior. To see values for power consumption that represent the design’ s actual workingonditions, you need vectors that mirror these working conditions. At the very least, the vectorseed to target simultaneous switching of high-power drivers rather than simply toggling all theodes. Typically, you need detailed knowledge of a design to understand what vectors to run.

Memory designs are the exception, where vector patterns used to check access time with read andwrite cycles work well.

or full-chip analysis or analysis of ASIC-style designs containing random logic, comprehensive suitesf vectors are unlikely to be available, so a vectorless dynamic analysis approach should beonsidered. This type of analysis uses the timing window information from static timing analysis (STA)o determine when gates switch, and complex algorithms predict what gates are likely to switchimultaneously.

f you use vectorless analysis, it is a good idea to correlate these results with vector-based analysisesults and with silicon (if available) to better understand if these results trend to optimism oressimism. For sign-off, analysis needs to be pessimistic, but too much pessimism results in over-esign, so a balance is required. Many designers also run up-front experiments to see what powerail configurations work best for their applications and target fabrication technologies.

Another issue that bears more attention is package loading, which can play a significant role in IRrop transients. Packages add resistance, capacitance and inductance to I/Os. Since this additional

oading can make IR drop worse, it should be included in dynamic rail analysis. Due to the complexityssociated with mapping chip-package pin names and generating pin models, look for analysis toolshat provide easy links to get information from package design tools.

As late as 2005, the vast majority of designs starts were at 130nm and above, so most designersad not yet encountered the most severe power-related challenges that begin to rule design flowst 90nm and below. The rail analysis issues and practices described in this article can help ease theransition to 90nm by focusing engineering attention where it is needed. With more advancedechnology nodes, the need for both dynamic and static power rail analysis becomes increasinglyritical, so it is worthwhile to begin developing sound methodologies using these techniques.

Power Basics

Power comprises three components:

l Dynamic or switching power to charge/discharge the signal load;

l The cells’ internal power;

l Leakage power.

Leakage power increases significantly at the 90-nm technology node and

begins to dominate total power between 65 and 45nm. Leakage power isstate dependent; the logic condition of a cell plays a role in determining therelated leakage.

Power rail analysis deals with dynamic power and the cells’ internal power.The main inputs to power rail analysis are extracted power rail parasitics,power information and voltage sources. The value for power can becalculated in several ways. Static power estimation uses activity informationand signal loading. Specifically, static power is calculated as:

P = 0.5·C·V²·F·A where

C = signal net loading;V = signal’ s voltage;F = frequency of change;A = activity rate

For example, consider a signal that has a load capacitance of 1.5pF,transitions from 0 to 1.2V at a base frequency of 100MHz, and has an activityfactor of 0.4 (only switches four out of 10 cycles). The static power

associated with this signal is:

P = 0.5·1.5e-1 2

·1.2·1.2·100e6

·0.4 Watts

Dynamic power estimation results in a power waveform per instance. Thesewaveforms are calculated from the static conditions plus a pre-characterizedswitching waveform for each cell and input slew rates. The calculations fordynamic power can be seeded with information from vectors, which directlydetermine which cells switch and when they switch. Dynamic power can alsobe calculated using a vectorless approach, in which complex algorithmsdetermine which cells switch based on timing window, logic and activityinformation.

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Copyright 2003-2010 Tech Pro Communications 1209 Colts Circle Lawrenceville, NJ 08648 Phone: 609-477-6308 john_miklosz@soccentral.com 

By Peter McCror ie. 

eter is the Product Marketing Director for Design for Manufacturing (DFM) at Cadence Designystems, Inc.

Go to the Cadence Design Systems, Inc. website to learn more. 

eywords: SOCcentral, Cadence Design Systems, power analysis, power optimization, EDA tools,

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