Altera Corporation 712008 5

7. Quartus II TimeQuest

Quartus II TimeQuestASICQuartus II TimeQuest GUI

Quartus II TimeQuest GUISynopsys Design ConstraintsSDCQuartus II

Quartus II TimeQuest Report Console Quartus IITimeQuest

Quartus II TimeQuest FPGAHardCopy ASIC

Quartus II TimeQuest 73Quartus II TimeQuest

77 727Quartus II TimeQuest

729 731SDC

QII53018-8.0.0

72 Altera Corporation2008 5

Quartus II Volume 3

733 753I/O 757 765 766 792 7100TimeQuest GUI 7113

TimeQuest SOPC Builder Quartus II Volume 4SOPC Builder

Quartus II TimeQuest

Quartus II TimeQuest FPGA

Quartus II TimeQuest

Quartus II TimeQuestQuartus II v7.2Quartus II TimeQuest Quartus II 2Quartus IITimeQuestQuartus II TimeQuest

Quartus II TimeQuest Assignments SettingsSettings CategoryTiming Analysis Settings Use TimeQuest Timing Analyzerduring compilation

Quartus II TimeQuest Tools CustomizeCustomizeToolbarsProcessingClose

http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp

Altera Corporation 732008 5

Quartus II TimeQuest

Quartus II TimeQuest

Quartus II TimeQuest Quartus II TimeQuest 71 Quartus II TimeQuest

71. Quartus II TimeQuest

Quartus II FPGA EDA

HDL

Create Quartus II Projectand Specify Design Files

Perform Initial Compilation

Specify Timing Requirements

Perform Compilation

Verify Timing

74 Altera Corporation2008 5

Quartus II Volume 3

Analysis andSynthesis

SDC

SDC Project Add/Remove Files in ProjectFiles SDC

FPGA

TimeQuest

Quartus II TimeQuest727 Quartus II TimeQuest

Altera Corporation 752008 5

Quartus II TimeQuest

Quartus II TimeQuest

Quartus II TimeQuest

Quartus II

Quartus II TimeQuest

Quartus II

Quartus II TimeQuest Quartus IITools TimeQuest Timing Analyzer Quartus II TimeQuestAnalysis and Synthesis

Quartus II TimeQuest

TimeQuest Quartus II

Quartus II TimeQuest

quartus_staw

Tasks OpenProject

76 Altera Corporation2008 5

Quartus II Volume 3

Quartus IITimeQuest 71

71.

-h | --help quartus_sta

-t |--script=

-s | --shell

--tcl_eval Tcl

--do_report_timing report_timing -npaths 1 -to_clock $clock

--force_dat

--lower_priority quartus_sta

--post_map

--qsf2sdc Quartus II.qsf Synopsys Design Constraints

--sdc= SDC

--fast_model

--report_script=

--speed=

--tq2hc Quartus II TimeQuest SDCHardCopy Design CenterHCDC PrimeTimeSDC

--tq2pt Quartus II TimeQuest SDC PrimeTime SDC

-f

-c | --rev=

Quartus II .qsf

--multicorner

Altera Corporation 772008 5

Quartus II TimeQuest

quartus_sta

Quartus II TimeQuest Quartus II TimeQuest

Quartus II TimeQuest 72 72

72. Quartus II TimeQuest

Create Timing Netlistcreate_timing_netlist

Create Timing Netlistcreate_timing_netlist

Constrain the Design

UpdateTiming Netlistupdate_timing_netlist

Verify Static TimingAnalysis Results

Open Projectproject_open

create_clockset_clock_uncertainty

set_clock_latency

create_generated_clockderive_pll_clocksset_input_delay

set_output_delay, ...

report_sdcreport_timingreport_clocks

report_min_pulse_widthreport_ucp

report_clocks_transfersreport_min_pulse_width

report_net_timing

78 Altera Corporation2008 5

Quartus II Volume 3

72Quartus II TimeQuest

Quartus II TimeQuest 73Quartus II TimeQuest 74

73.

72. Quartus II TimeQuest

Nodes

Keepers (1)

Cells LUTDSPTriMatrixIOE (2)

Pins Nets Ports Clocks

72 :(1) -from

(2) Stratix LUT LE

data1 and_inst

data2

clk

reg1

reg2

reg3

Altera Corporation 792008 5

74. Quartus II TimeQuest

74 reg1 reg2 and_inst

data1|combout reg1|regout and_inst|combout

data1~combout reg1 and_inst

data1, clk data_out

2

data1reg1

combout

combout

outclk

inclk0]

datain

clk

regout

regout

datac

dataddatain

data_outreg3

and_inst

data2 reg2

clk clk~clkctrl

Cell

Port

Pin

Pin

Port

Cells

Cell

710 Altera Corporation2008 5

Quartus II Volume 3

75

75.

Quartus II TimeQuest Quartus II TimeQuest clock-to-outtCO Q DtCO FPGA clock-to-out

Quartus II TimeQuest 76Quartus II TimeQuest tSUtSU FPGA

CLRN

D QClock Path Data Path

Asynchronous Clear Path

clk

rst

CLRN

D Q

Altera Corporation 7112008 5

76.

Quartus II TimeQuest

77 reg1 0 ns reg25 ns

77.

D QD Q

Data Arrival

Clock Arrival

D QD Q

clk

clk

reg1 reg2

0 ns 5 ns 15 ns10 ns

Latch Edge at Destination Register reg2

Launch Edge at Source Register reg1

712 Altera Corporation2008 5

Quartus II Volume 3

Quartus II TimeQuest

I/O Quartus IITimeQuest Quartus II TimeQuest

Quartus IITimeQuest Quartus II TimeQuest 782 A B10 ns3 ns A20 ns19 ns B

78.

Setup A Setup B

0 ns 8 ns 16 ns 24 ns 30 ns

Source Clock

Destination Clock

Altera Corporation 7132008 5

Quartus II TimeQuestQuartus II TimeQuest 1

(1)

Quartus IITimeQuest 2

(2)

Quartus IITimeQuest 3

(3)

Clock Setup Slack Data Required Time Data Arrival Time=

Data Arrival Time Launch Edge Clock Network Delay to Source Register ++=

tCO Register-to-Register Delay+

Data Required Clock Arrival Time tSU Setup Uncertainty=

Clock Arrival Time Latch Edge Clock Network Delay to Destination Register+=

Clock Setup Slack Time Data Required Time Data Arrival Time=

Data Arrival Time Launch Edge Clock Network Delay ++=

Input Maximum Delay of Pin Pin-to-Register Delay+

Data Required Time Latch Edge Clock Network Delay to Destination Register tSU+=

Clock Setup Slack Time Data Required Time Data Arrival Time=

Data Arrival Time Launch Edge Clock Network Delay to Source Register ++=

tCO Register-to-Pin Delay+

Data Required Time Latch Edge Clock Network Delay Output Maximum Delay of Pin+=

714 Altera Corporation2008 5

Quartus II Volume 3

Quartus II TimeQuestQuartus II TimeQuest Quartus II TimeQuest 22 79 A B 2 AB A1 B12 A B A2 B2

79.

Quartus II TimeQuest 79 A2

Setup A

0 ns 8 ns 16 ns 24 ns 30 ns

Source Clock

Destination Clock

Setup BHoldCheck A1 Hold

Check B2Hold

Check A2Hold

Check B1

Altera Corporation 7152008 5

Quartus II TimeQuest 4

(4)

Quartus IITimeQuest 5

(5)

Quartus IITimeQuest 6

(6)

Clock Hold Slack Data Arrival Time Data Required Time=

Data Arrival Time Launch Edge Clock Network Delay to Source Register tCO+ + +=

Register-to-Register Delay

Data Required Time Clock Arrival Time tH Hold Uncertainty+ +=

Clock Arrival Time Latch Edge Clock Network Delay to Destination Register+=

Clock Setup Slack Time Data Arrival Time Data Required Time=

Data Arrival Time Launch Edge Clock Network Delay + +=

Input Minimum Delay of Pin Pin-to-Register Delay+

Data Required Time Latch Edge Clock Network Delay to Destination Register tH+ +=

Clock Setup Slack Time Data Arrival Time Data Required Time=

Data Arrival Time Latch Edge Clock Network Delay to Source Register tCO+ + +=

Register-to-Pin Delay

Data Required Time Latch Edge Clock Network Delay Output Minimum Delay of Pin+=

716 Altera Corporation2008 5

Quartus II Volume 3

clear presetQuartus II TimeQuest 7

(7)

Quartus II TimeQuest 8

(8)

I/O Input Maximum Delay Quartus II TimeQuest

Quartus II TimeQuest Quartus II TimeQuest 9

Recovery Slack Time Data Required Time Data Arrival Time=

Data Arrival Time Launch Edge Clock Network Delay to Source Register+ +=

tCO Register-to-Register Delay+

Data Required Time Latch Edge Clock Network Delay to Destination Register tSU+=

Recovery Slack Time Data Required Time Data Arrival Time=

Data Arrival Time Launch Edge Clock Network Delay Maximum Input Delay+ + +=

Port-to-Register Delay

Data Required Time Latch Edge Clock Network Delay to Destination Register Delay tSU+=

Altera Corporation 7172008 5

(9)

Quartus II TimeQuest 10

(10)

Input Minimum Delay Quartus II TimeQuest

2 12 3 710 1

Removal Slack Time Data Arrival Time Data Required Time=

Data Arrival Time Launch Edge Clock Network Delay to Source Register+ +=

tCO of Source Register Register-to-Register Delay+

Data Required Time Latch Edge Clock Network Delay to Destination Register tH+ +=

Removal Slack Time Data Arrival Time Data Required Time=

Data Arrival Time Launch Edge Clock Network Delay Input Minimum Delay of Pin ++ +=

Minimum Pin-to-Register Delay

Data Required Time Latch Edge Clock Network Delay to Destination Register tH+ +=

718 Altera Corporation2008 5

Quartus II Volume 3

710.

711 src_clk 10 ns dst_clk 5 ns

711.

712 5 ns 0 ns

D Q

ENA

D Q

D Q

ENA

2 Cycles

D Q

ENA

D Q D Qdata_in

src_clk

reg reg

data_out

dst_clk

Altera Corporation 7192008 5

712.