IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27,NO 12,DECEMBER 1992 1927

A 288-kb Fully Parallel Content Addressable MemoryUsing a Stacked-Capacitor Cell Structure

Tadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai,Toshifumi Kobayashi, Member, IEEE, Michihiro Yamada, and Hideyuki Ozaki

AZNract-Thk paper describes a 288-kb (8K words X 36 b)fully parallel content addressable memory (CAM) LSI using acompact dynamic CAM cell with a stacked-capacitor structureand a novel hierarchical priority encoder. The stacked-capac-itor structure results in a very compact dynamic CAM cell (66pmz) which is operationally stable. The novel hierarchicalpriority encoder reduces the circuit area and power dissipa-tion. In addition, a new priority decision circuit is introduced.The chip size is 10.3 X 12.0 mmz using a 0.8-~m CMOS processtechnology. A typical search cycle time of 150 ns and a maxi-mum power dksipation of 1.1 W have been obtained using cir-cuit simulation. In fabricated CAM chips, we have verified theperformance of a search operation at a 170-ns cycle and haveachieved a typical read/write cycle time of 120 ns. This CAMLSI performs large-scale search operations very efficiently, andtherefore, has the possibility of broad applications to high-per-formance artificial intelligence machines and data-base sys-tems.

I. lNTRODUCTION

DATA processing that involves many search opera-tions performed by software consumes enormous

time. This is a hindrance to high-speed data processing.A fully parallel content addressable memory (CAM) com-pares search data with storage data in a parallel fashion,and is extremely suitable for high-speed data searching.A search operation carried out by a fully parallel CAM isseveral hundred times faster than that performed by soft-ware [1]. Therefore, there have been many studies thathave addressed the applicability of CAM’s to artificial in-telligence (AI) machines, data-base systems, and so on inwhich search operations are conducted frequently. For ex-ample, the studies on a Lisp machine [2], a Prolog ma-chine [3], [4], a data-base accelerator [1], [5], [6], [7],pattern inspection [8], address filtering for local area net-works [9], TLB for a RISC processor [10], and othershave been reported.

Similarly, there have been many studies concerninghigh-density CAM’s that use LSI technology, ever sincea CAM cell using MOS transistors was introduced in 1966

Manuscript received January 31, 1992; revised July 14, 1992.T. Yamagata, M. Mihara, T. Hamamoto, T. Kobayashi, and H. Ozaki

are with the LSI Laboratory, Mitsubishi Electric Corporation. 4-1 Mizu-hara, Itami, Hyogo 664, Japan.

Y. Murai is with the LSI Design Center, Mitsubishi Electric EngineeringCompany Ltd., 4-61-5 Higashino, Itami, Hyogo 664, Japan.

M. Yamada is with Kits-Itami Works, Mitsubishi Electric Corporation,4-1 Mizuhara. Itami, Hyogo 664, Japan.

IEEE Log Number 9204136.

[1 1]. It has been difficult to develop a large-bit-capacityCAM, because fully parallel CAM’s require an EXCLU-

SIVE-NOR circuit in each CAM cell for a match operation.Representative attempts to rectify this problem are a 1-kbCAM in 1983 [12], 4- and 8-kb CAM’s in 1985 [13],[14], and a 20-kb CAM in 1989 [15]. However, CAM’swith larger bit capacities are required for large-scale datasearching and for broadening CAM applications.

In this paper, a compact dynamic CAM cell with astacked capacitor structure and a novel hierarchical prior-ity encoder are proposed for expanded large-scale inte-gration. Utilizing these new techniques, a 288-kb (8Kwords x 36 b) fully parallel CAM has been successfullydeveloped. In order to achieve high-performance datasearching, this CAM LSI was also designed to performvarious functions. In the following sections, the CAMcell, the novel priority encoder, the chip architecture, andthe functions and features of this CAM LSI are described[16].

II. DYNAMIC CAM CELL WITH STACKED-CAPACITOR

STRUCTURE

Conventional CAM’s use a static CAM cell, whichkeeps storage data in a latch, to accomplish a stable op-eration [12]–[15]. Static CAM cells, however, take uplarge areas of the chip due to the large numbers of tran-sistors in the cell. Therefore, the static-type cell is notsuitable for high-density CAM’s. To address this prob-lem, a dynamic CAM cell that stores data on the gate ca-pacitance of transistors has been proposed [17], [18]. Thedynamic-type cell provides a compact cell area due to thesmaller number of transistors required. However, there isstill a serious problem with the conventional dynamicCAM cells. In the dynamic cells, since a charge is storedon the gate capacitance of a transistor, the storage capac-itance decreases as the transistor size decreases. There-fore, in a compact CAM cell using a submicrometer pro-cess, it is difficult to attain a storage capacitance of morethan 30 fF, which is necessary to be immune from thealpha-particle-induced soft error as described in dynamicRAM’s. This section presents an operationally stable,compact, dynamic CAM cell for large-scale integration.

The proposed CAM cell is shown in Fig. 1. It consistsof five NMOS transistors and two stacked capacitors [19].Four of the transistors (&l,O,M,l, Mti, MW1)are used to

0018-9200/92$03 .00 @ 1992 IEEE

1928 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27,NO. 12,DECEMBER 1992

Stack:d=Capacitor

MsO

(a)

— WL

— ML

Storage Node

1 1

(b)

Storage Node Cell Plate

G~:~#;;) (2 ‘“:julator ~il; 3 ‘“’y )

&

Cso Gate ( MsO)( 1 Poly )

“+ ~n+ ,*n+J” “n+b

p - Well

/p - Substrate

)

(c)

Fig, 1. Dynamic CAM cell with stacked-capacitor stnscture. (a) Cell cir-cuit diagram (V.,, = V,.: supply voltage). (b) Layout of CAM cell. Cellsize is 8,8 X 7.5 pmz. (c) Cross-sectional view of CAM cell.

store and access data, and one (Md) is used as a diode toisolate current paths during match operations. Charges arestored on stacked capacitors (C,o, C,l) and the ikl~oandM,, gates. The opposite electrodes of the C’,. and C,l areconnected to a cell plate voltage VCP,which is equal tohalf VCC( VCC:supply voltage). Two bit lines (Bit, Bit) aresupplied with data in write and search operations. Theword line (WL) allows write access to each cell in a word(36 b). The match line (ML) passes through a word toperform a logical AND of the results of each cell’s com-parison. The ML is also used to read cell data. The stor-age capacitor (C$o) is stacked on the gate of the M,. andMw, as shown in Fig. 1(c). The gate electrodes of the M~oand MWOare fabricated with the first poly-Si layer. Thestacked capacitor is composed of the second poly-Si layer,the insulator film, and the third poly-Si layer. The secondpoly-Si layer (storage node) is also used to connect thedrain (or source) of the MWOto the gate of the &f$o.Simi-larly, the storage capacitor (C~l) is formed on the gate ofthe M,l and M.l. A SEM micrograph of the CAM cellafter storage node layer formation is shown in Fig. 2.

Fig. 2. SEM micrograph of CAM cell after storage node formation.

,fp

M.

VcMwO Mwl

CSO Csl L

MsO Msl

Md

0.

WL WL

ML ML

(a) (b)

Fig. 3. Match operation of novel CAM cell: the case of (a) match and (b)mismatch. Match result is transferred to match line ML.

A write operation is performed by activating a selectWL and then driving the bit lines according to the writedata. Utilizing this process, the data are written on thestacked capacitors and the gates of M,. and M,,, via theMWOand M.l.

A match operation is achieved by precharging both thebit lines and the match lines to a high level, and then load-ing the bit lines with search data. As shown in Fig. 3, itis assumed that high data are stored in a CAM cell. TheBit, Bit, and ML are precharged to a high level before-hand. If a high potential and a low potential are suppliedto the Bit and Bit, respectively, the ML retains the highlevel, and “match” is detected (Fig. 3(a)). On the otherhand, if a low potential and a high potential are suppliedto the Bit and Bit, respectively, the ML is discharged viathe transistors M$o and Md, and the ML drops to a lowlevel. Therefore, “mismatch” is indicated (Fig. 3(b)). Inthis way, match information is transferred to match lines.

A read operation is accomplished by discharging the bitlines, and then driving a selected ML to a high level. Ifhigh data are stored in the cell, the Bit is charged via theMd and Mso from the ML,, and the Bit remains at a lowlevel. Similarly, if low data are stored in the cell, the Bitremains at a low level and the Bit is charged. In this way,the storage data in the cell are read out on the bit lines.

In the novel CAM cells, since a stacked capacitor isadopted as the storage capacitor, a storage capacitance of90 fF is attained in a 66-lum2 CAM cell using a O.8-~mCMOS process. This is sufficient for the high soft-errorimmunity and provides stable performance of the opera-

YAMAGATA etal.: 288-kbFULLY PARALLEL CAM USING STACKED-CAPACITOR CELL 1929

tions mentioned above. Furthermore, it suggests the pos-sibility of achieving a more compact CAM cell by devicescaling.

III. NOVEL HIERARCHICAL PRIORITY ENCODER

When a match occurs at several words in a search op-eration (multiple response), the CAM outputs the address

of the matched word with the highest priority. A priority

encoder (PE) circuit is utilized for multiple-response res-

olution and match address generation. As a bit capacity

of CAM’s becomes larger, the number of words increases

rather than the bit length of words. Therefore, in a high-

density CAM chip, the configuration must be such thatthe cell array is divided into several blocks. This createsa serious problem concerning the layout of the PE. Whenthe PE is incorporated in each block, the silicon area oc-cupied by the PE and the power dissipation of the PE areincreased in proportion to the number of divided blocks.We therefore propose a novel hierarchical PE architecturesuitable for high-density CAM’s, as shown in Fig. 4. Inthe architecture, an OR circuit and a switching circuit areprovided in each block, and a main priority encoder(MPE) and a block priority encoder (BPE) are located inthe peripheral area of the CAM array. In a search opera-tion, each OR circuit generates a block-hit signal, whichshows whether matched words exist in the block or not.Then, the block-hit signal is connected to the BPE andscrutinized by the BPE. The BPE then generates an en-coded block address and block-select signals which indi-cate the block with the highest priority. Next, the switch-ing circuit of the selected block is activated, and the matchinformation of the selected block is transferred to theMPE. Finally, the MPE generates an encoded main ad-dress, which combines with the encoded block address toform a match address.

In this architecture, the OR circuit and the switching cir-cuit, which occupy a very small silicon area and dissipatelittle power, are located in each block. Furthermore, onlyone BPE and MPE, which have large areas and dissipatemuch power, are placed in the peripheral area. Therefore,an increase in the silicon area and power dissipation inthe PE due to an increase in the number of divided blockscan be suppressed using this architecture.

IV. CAM ARCHITECTURE

A. Basic Architecture and Operations

A block diagram of a 288-kb CAM is shown in Fig. 5.The CAM LSI consists of an 8K word x 36-b memorycell array, an address decoder for address access opera-tions, a PE for search operations, registers, 110 buffers,and control circuits managed by instructions from exter-nal ports. Since the CAM utilizes dynamic-type CAMcells, a refresh operation is needed. Therefore, a refreshaddress counter is also prepared for the refresh operation.The PE has the hierarchical architecture previously de-scribed, the details of which will be discussed in the next

Fig. 4. Novel hierarchical priority encoder. BPE indicates block with thehighest priority and MPE indicates word with the highest priority in theselected block.

instruction

Data or

Match Adr.Reg.l I Adr,Reg. I lData Reg.1 lMaak Reg.

Array Interface

hv

,13

0 CAM Cell Array%o +

u+ & -Wit

( 8kword x 36bit )4a

k

Fig, 5. Block diagram of 288-kb CAM.

section. A match address register contains the match ad-dress received from the PE after a search operation. Anaddress register is provided to store an address for writeand read operations. A data register keeps search and writedata from external ports and read data from the memorycell array. The search and write data can be masked bymask control bits contained in a mask register, for maskedsearch operations and partial writing, respectively.

The search, write, and read operations are performedin one cycle, between the CAM cell array and’ registers.One cycle is also required for data transmission betweenthe registers and the external ports. The search operationis carried out as follows: in the first cycle, 36-b researchdata are transferred from the external ports to the dataregister via data buses; in the second cycle, the searchdata are simultaneously compared with 8K words storedin the CAM cell array, and the match address is thentransferred to the match address register; and in the thirdcycle, the match address is output to the external ports viathe data buses. Therefore, content addressing is achievedin three cycles. Similarly, the write and read operation byan address access can be performed in three cycles. In therefresh cycle, an internal address generated by the refreshaddress counter is supplied to the address decoder via amultiplexer. All CAM cell data are refreshed by 512 re-fresh cycles.

In addition, the CAM can perform logical ANDfORop-erations between previous and curent search results, and

1930 IEEE JOuRNAL OF sOLID-sTATE CIRcUITS, VOL. 27,NO. 12,DECEMBER 1992

TABLE IINSTRUCTIONSOF 288-kb CAM

Search

● search word● OR search● AND search● LINK search● NEXT search● search empty word

Write● write data to addressed word● write data to matched word

Read● read data from addressed word● read data from matched word

Empty* empty addressed word● empty matched words in parallel

36Bits —

13’lockController

*

, :“ llnDrlDon*. . . . . . . . . . . . . . . . . . . . . . . . . . .

! i Iluunnnn!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 6. CAM cell array architecture. CAM array is divided into 32 blocks.One BPE and four MPE’s are placed for novel PE architecture.

● resetothers

● refresh

can store the results in match flags which are providedeach word and show whether the word is matched or not(AND/ORsearch). This function facilitates relational searchoperations such as less-than search [15]. The CAM canalso carry out a logical ANDoperation among search re-sults of two or more successive words for wide-bandsearching (LINKsearch) [15]. When a multiple-responseoccurs in a search operation, the CAM can output the ad-dress of the next most closely matched word after gener-ating the match address with the highest priority (NEXT

search). By repeating this operation, the CAM can outputmatch addresses in order of priority. Furthermore, emptyflags are provided every word location to indicate whetherthe word is empty. The CAM LSI can empty desiredwords by address access, and also empty matched wordsat once. Moreover, the CAM can search for empty wordsand output the addresses of empty words. The main in-structions of the CAM LSI are summarized in Table I.The functions previously mentioned, in combination witha 288-kb memory cell array, contribute to the actualiza-tion of high-performance data processing.

B. CAM Cell Array Architecture

The memory cell array architecture is shown in Fig. 6.The CAM array is divided into 32 blocks. Each block hasa CAM cell subarray of 256 words x 36 b, a word op-eration circuit, a bit operation circuit, and a block con-troller. The word operation circuit drives the WL’S andML’s in write and read operations and latches search re-sult signals in every word’s match flags. The word oper-ation circuit also contains the ORcircuit and the switchingcircuit of the new priority encoder described in SectionHI. The bit operation circuit supplies the CAM cell sub-array with data from the array data buses during searchand wlite operations, and provides CAM cell data to thearray data buses during read operations. The block con-troller manages the word operation circuit and the bit op-eration. circuit. One BPE and four MPE’s are placed for

the novel hierarchical PE architecture, and each MPE isconnected to eight CAM cell blocks, as shown in Fig. 6.Moreover, data drivers and amplifiers that are connectedto the array data buses are povided as interfaces betweenthe peripheral circuit and the CAM array.

The block-hit signals generated in every block are sentto the BPE in parallel, and the search result of the selectedblock, from among 32, is transferred to one of the fourMPE’s by block-select signals from the BPE. The otherthree MPE’s are not activated. By utilizing this uniquehierarchical PE, the area the PE occupies is only 12% ofthe CAM array’s total area. (A conventional PE occupies35%.)

V, MULTIPLE-RESPONSE RESOLVER

A multiple-response resolver (MRR) in the BPE is de-signed using a binary tree structure [20], as illustrated inFig. 7. In a basic selection circuit, HBO and L?B1 are hit-signals from lower level circuits, and SBO and SB1 areselect-signals sent to the lower-level circuits. HBA is alogical OR result of HBO and HB1, and is sent to an upperlevel circuit. SBA is a select signal from the upper levelcircuit and controls the activation of the basic selectioncircuit. Here, it is assumed that SBA is activated (SBA =“1”). If ffBo = “1,>> SBO is activated and SB1 is notactivated, in spite of the value of HB1. SB1 is activatedonly when HBO = “O” and HBl = “l”. When SBA isnot activated (SBA = “O”), both SBO and SB 1 are notactivated. The hit signals (HBO, HB1) and select signals(SBO, SB1) in the lowest level circuits correspond to theblock-hit signals from the {CAMcell blocks and the block-select signals to the blocks, respectively. The HBA of thecircuit with the highest level indicates whether there arematched words in the CAM LSI (shown as “Hit” in Fig.7). As a result, the block with the highest priority matchedword is selected by the block-select signals.

Fig. 8 illustrates the configuration of a MRR in theMPE. This MRR has a tree structure based on lookaheadcircuits for high-speed operation. MO–M255 are matchsignals from 256 words in the CAM cell block selectedby the BPE. Conventional four-input Iookahead priority

YAMAGATA C?al.: 288-kbFULLY PARALLEL CAM USING STACKED-CAPACITOR CELL 1931

Basic selection circuit

CAM Cell

/

. . . . . . . . . . . . . . . ...>....I In

l—— ● .4Js ●

● ● -tf~

Fig. 7. Multiple-response resolver in BPE. The circuit is designed usinga binary tree structure.

/MO;I \

M2 ;7

‘3*

●

●

●

I till?-~,\

Ml ;

INewPrioritv

From

{

:256, .,-. A- !,,.,,,,,,,,,,,; TIHM!MA

] SM; ‘MA eMo. . .

,J&’ Decisi&rCircuit

ti!bMo J ‘k

..,,.,,,,.

~ ● “M&A~A● 8-inputs 1 HMAe...

● .,.,,..

3} To Encoder/

................

Fig. 8. Multiple-response resolver in MPE. The MRR has a tree structurebased on lookahead circuits for high-speed operation.

HMO SMO

HMI SM1

HM2 SM2

HM3 SM3

HM4 SM4

t’tM5 SM5

HM6 SM6

HM7 ,1

SM7~ HMA SMA

Fig. 9. New priority decision circuit. The circuit scheme b[ings small cir-cuit area because an OR circuit to generate HMA is merged in the lookaheadcircuit.

decision circuits are used for first level of the tree struc-ture, and new eight-input lookahead circuits are adoptedfor the second and third levels. Fig. 9 shows the newpriority decision circuit. HMO-lW17 are hit signals fromlower level circuits, and SMO-SM7 are select signals sentto the lower level circuits. SMA is a select signal from anupper level circuit and controls the activation of SMO–SM7. Here, it is assumed that SMA is activated (SMA =“1’’).IfEZMOis’’l, ” SM1–SM7 with lower priority areinhibited from outputting and only SMO is activated.

6 l----85E-95 I I 1

!;4$3 . 7

lBit Hit ;

1- Bit PA22: Addrees

~1

o - H-,”,,.,,,., * K!

., ~o 20 40 60 80 100 120

TIME (ns)

Fig. 10. Simulation result of search operation. PA is activating signal ofPE.

Fig. 11. Photomicrograph of 288-kb CAM.

When HMO is “O” and HM1 is “l, ” only SM1 is acti-vated. In this way, the outputs are decided based on thehit signal with the highest priority. Furthermore, an OR

circuit used to generate a hit-signal HMA, which is trans-ferred to an upper level circuit, is merged in the look-ahead circuit. The number of transistors is very smallcompared with that of a circuit utilizing conventional logicgates. Therefore, the new circuit contributes to circuit areareduction.

VI. CIRCUITSIMULATION

Fig. 10 shows the simulation result of a search opera-tion at 5 V of power supply. The generation time of amatch address is 85 ns, from the time the search data isloaded on the bit lines. The encoding time of this new PEis 40 ns, and the typical cycle time is 150 ns. The maxi-mum power dissipated in the PE is 52.2 mW at 6.7-MHzand 5-V operation, which is 20 times less than that ofconventional PE architecture. The maximum power dis-sipation of the chip is 1.1 W at 6.7-MHz and 5-V opera-tion.

1932 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27,NO. 12,DECEMBER 1992

sFE

Match Resultoutput

MatchAddress

Fig. 12. Measured waveforms in search operation at V<.= 5 V25”C.

- 6.0 . . . . . . . .PPPPPPPPPPPP

: %? :::::..,..PPPPPPPPPP....PPPPASS PP

s 4:5 ...........PPPPPPPPI i I I I

100 110 120 130 140Tc (ns)

and T<,=

Fig. 13. Schmoo plot of V., versus cycle time T, in readlwrite operationat TO= 25° C.

VII. EXPERIMENTALRESULTS

An experimental 288-kb CAM chip has been fabricatedusing a O.8-~m double-metal CMOS process technology.A photomicrograph of the CAM chip is shown in Fig. 11.The chip size is 10.3 X 12.0 mm2. Fig. 12 shows wave-forms measured in a search operation. The search opera-tion starts from CS clock falling, and then the match resultis output. Next, the match address is obtained from amatch address register after RE clock falling. The wave-forms indicate that a search operation is carried out within170 ns at a supply voltage VCCof 5 V and an ambienttemperature T. of 25 ‘C. Fig. 13 shows a schmoo plot ofVCCversus cycle time TCfor read and write operations whenT. = 25 “C. A cycle time of 120 ns has been achieved ata V.Cof 5 V. Furthermore, a data retention time of morethan 2 s has been obtained in a search operation cyclewhen VCC= 5 V and T~ = 25 ‘C. This means that a refreshcycle time of 3.9 ms is required considering the 512 re-fresh architecture. This value is much longer than that ofa dynamic RAM.

VIII. CONCLUSIONS

A 288-kb (8K words X 36 b) CAM with a fully parallelsearch operation has been successfully developed using adynamic CAM cell with a stacked-capacitor structure anda novel hierarchical priority encoder. This CAM LSI isfabricated using O.8-,um double-metal CMOS processtechnology. The chip measures 10.3 X 12.0 mm2. Thetypical search cycle time and maximum power dissipationare 150 ns and 1.1 W, respectively, using circuit simu-lation. In fabricated CAM chips, we have verified the per-formance of a search operation at a 170-ns cycle and haveobtained a readlwrite cycle time of 120 ns using a VCCof5 V. The features of the CAM are listed in Table II. This

TABLE 11FEATURES OF 288-kb CAM

OrganizationCycle TimeSupply VoltagePower Dissipation1/0 Interface

Number of PinsProcess Technology

Chip SizeCell SizeRefresh Cycle

8K words x 36 b150 ns (Typical)5V1.1 W (Max.) at 6,7 MHz110 Common,

TTL Compatible680.8-~m twin-well CMOS

2 A1/3 Poly-Si/ 1 Polycide10.3 X 12.0 mmz8.8 x 7.5 ~m’512

CAM LSI has possible broad applications to high-per-formance AI machines and data-base systems, which re-quire high-speed for large-scale data searching.

ACKNOWLEDGMENT

The authors would like to thank Dr. H. Komiya andDr. T. Yoshihara for their encouragement throughout thework, and also wish to thank Dr. S. Satoh, H. Miyamoto,Y. Ohno, Y. Yagoh, A. Hachisuka, and M. Takeuchi fortheir discussions and device processing.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

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[15] T. Ogura, J. Yamada, S. Yamada, and M. Tan-no, “A 20-kbit as-

YAMAGATAet al.: 288-kbFULLY PARALLEL CAM USING STACKED-CAPACITOR CELL 1933

sociative memory LSI forartiticial intelligence machines, ” D?EJ?.J.Solid-Stare Circuits, vol. 24, pp. 1014-1020, Aug. 1989,

[16] T. Yamagata, M. Mihara, T. Hamamoto, T. Kobayashi, and M. Ya-mada, “A 288-kbit fully parallel content addressable memory usingstacked capacitor cell structure, “inl%-oc. CICC, May 1991, p. 10-3.

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Tadato Yamagata was born in Osaka, Japan, onNovember 27, 1957. He received the B.S. andM.S. degrees inelectric engineering from OsakaUniversity, Osaka, Japan, in 1981 and 1983, re-spectiveiy.

He joined tbe LSI Laboratory, Mitsubishi Elec-tric Corporation, Itami, Japan, in April 1983.Since then he has engaged in the design of MOSdynamic RAM’s, content addressable memories,and MOS static RAM’s.

Mr. Yamagata is a member of the Institute ofElectronics, Information and Communication Engineers of Japan.

Masaaki Mlhara was born in Hyogo, Japan, onApril 13, 1961. He received the B.S. and M.S.degrees in electronic engineering from the OsakaCity University, Osaka, Japan, in 1984 and 1983,respectively.

In 1986 he joined the LSI Research and Devel-opment Laboratory, Mitsubishi Electric Corpora-tion, Hyogo, Japan.

Takeshi Hamamoto was born in Hyogo, Japan,on November 6, 1963. He received the B.S. de-grees in engineering physics from Kyoto Univer-sity, Kyoto, Japan, in 1986.

He joined the LSI Laboratory, Mitsubishi Elec-tric Corporation, Itami, Japan, in April 1987.Since then he has engaged in the design of ASICmemories and MOS dynamic RAM’s.

Yasumitsu Murai was born in Osaka, Japan, onJanuary 27, 1967. He received the B.S. degree inelectrical engineering from Kinki University,Osaka, Japan, in 1990.

He joined the LSI Design Center MitsubishiElectric Engineering Company Limited, Itami,Hyogo, Japan, in 1990. Since then he has beenengaged in the design of MOS memory.

Toshifumi Kobayashi (M’88) was born in Oka-yama, Japan, on August 14, 1955. He receivedthe B.S. and M. S. degrees in electronic engineer-ing from Okayama University, Okayama, Japan,in 1978 and 1980, respectively.

In 1980 he joined the LSI Research and Devel-opment Laboratory, Mitsubishi Electric Corpora-tion, Itami, Hyogo, Japan. From 1981 to 1989 hewas engaged in the design of MOS dynamicRAM’s and ASIC memories. Since 1990 he hasbeen involved in the development of amrlication

systems for 32-b microprocessors. His current resea~ch interes;s- includehigh-performance memory systems, computer architecture, and real-timeoperating systems.

Mr. Kobayashi is a member of the Institute of Electronics, Informationand Communication Engineers of Japan.

Michihiro Yamada was born in Japan on January10, 1950. He received the B.S. degree in appliedphysics from the University of Tokyo, Tokyo, Ja-pan, in 1972, and the Ph.D. degree from OsakaUniversity, Osaka, Japan, in 1984.

In 1972 he joined the Central Research Labo-ratories, Mitsubishi Electric Corporation, Ama-gasaki, Japan. In 1973 he started research and de-velopment on charge-coupled devices (CCD’S). In1976 he transfemed to Mitsubishi’s LSI Researchand DeVelODIIIentLaboratory.’ Itami. Jar)an. where

he has been involved in the development of CCD m&nories”and MOS dy-namic memories. In 1991 he transferred to Mitsubishi’s Kits-Itami Works,Itami, Japan, where he is currently working on production of MOS dy-namic memories.

Dr. Yamada is a member of the Institute of Electronics, Information andCommunication Engineers of Japan.

Hldeyuki Ozaki was born in Hyogo, Japan, onSeptember 23, 1951. He received the B.S. andM.S. degrees in electrical engineering from KyotoUniversity, Kyoto, Japan, in 1975 and 1977, re-spectively, and the Dr. degree in electronic engi-neering from Osaka University, Suita, Japan, in1988.

In 1977 he joined the LSI Laboratory, Mitsu-bishi Electric Corporation, Hyogo, Japan. Sincethen he has been engaged in the design of MOSmemories, especially MOS dynamic RAM’s.

Dr. Ozaki is a member of the Institute of Electronics, Information andCommunication Engineera of Japan.