advanced vlsi design (module 24151) - uni-rostock.de
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Course and Contest – Phase 4
Prof. Dirk Timmermann, Christoph Niemann, Jakob Heller, Hannes Raddatz, Franz Plocksties
Advanced VLSI Design(Module 24151)
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Institut fürAngewandte
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Outline
1. Presentation of final optimized FPGA designs
2. Information for synthesis flow
Synthesis for ST65 technology
3. Task and further information for phase 4
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Presentation of optimized designs
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Group Student Phase 1 Phase 2 Phase 3
2Koch, Christian
3,12E-11 1,89E-09 XMoray, Tanner
3Björner, Mathis
1,11E-11 4,66E-11 6.12E-10Kapikad, Rakshan
Premsagar
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Björner, Mathis/ Kapikad, Rakshan Premsagar
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Synthesis for ST65
• Synthesis of a working netlist for an ST 65 nm library
Gate level synthesis and technology mapping
• Remarks:
OS: CentOS6.X (accounts for R1218/R1216 are required)
Tools: Synopsys Design Vision, Synopsys VCS-MX
• Manuals and files:
Synopsys: Use help in GUI or with command line >help … >man …
ST65: /opt/lib/cmos065/CORE65LPSVT_SNPS-AVT-CDS_4.1/doc/*.pdf
System, design files and scripts: synopsys_WS18_19.tar.gz
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Synthesis for ST65 – User interface
Design Vision
• Toolbar
• Command window
• Design schematic
• Hierarchy editor
• ….
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Synthesis for ST65 - Preparation
1. Login with your RZ-Account
2. After login: right mouse click > “Open terminal”
3. Download synopsys_WS19_20.zip from StudIP into your home
directory
5. Unzip the archive: tar -xvzf synopsys_WS19_20.tar.gz
6. Change into directory synopsys: cd synopsys
7. Copy all your design files into the directory: /home/<user>/synopsys/your_design/
8. Change the synthesis script (synthesize_design.tcl) by entering
the file names of your vhdl files in the top part of the script (create a
new “analyze…“-line for every VHDL file)
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Synthesis for ST65 – Work flow
1. Login with your RZ-account
2. Start a terminal: right mouse click > “Open terminal”
3. Change directory: cd synopsys
4. Start Design Vision: csh start_design_vision.csh
5. Start synthesis script: File > Execute Script > “<script>”
Choose “synthesize_design.tcl”, which produces the verilog gate netlist
(“results/your_filter.v”)
6. Reports for area, power and delay are available in
“results/design_report.txt”
7. Perform functional simulation of the netlist with “execute_sim.tcl”
8. One error should occur at the start of the simulation -> ignore it
9. Frequency response diagram and updated design report are in “results”
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Synthesis for ST65 – Voltage Threshold Libraries
Approach: multiple threshold voltages to optimise delay or power
• Three flavors of standard cells: HVT, LVT, SVT
• High, Low and Standard Voltage Threshold
• subthreshold leakage is the most important contributor to static power
in CMOS Higher VT exponentially less current
• However, a high threshold voltage causes a high delay since more
power is needed in order to charging/discharging the capacitance of a
MOSFET
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Synthesis for ST65 – Voltage Threshold Libraries
• HVT:• lower sub-threshold leakage current
• delay of the cell is higher
• interesting for parts of the chip which don‘t need high performance or are idle of the most time
• LVT:• higher sub-threshold leakage current
• delay of the cell is lower
• for a boost in performance (useful for critical paths)
• SVT:• trade-off between HVT and LVT
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Nose, K., Hirabayashi, M., Kawaguchi, H., Seongsoo Lee und Sakurai, T.
V/sub TH/-hopping scheme to reduce subthreshold leakage for low-power processors
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Synthesis for ST65 – Synthesis script
Remarks on “synthesize_design.tcl“
1. Loading core libraries
2. Analysis and elaboration (translation of VDHL files and building the
design)
3. Compile options
Desired target frequency, set_cost_priority, …
Maximum power values (set_max_dynamic_power, …)
4. Compiling design (logic and gate level synthesis)
5. Preliminary results report (“./results/design_report.txt“)
Area, timing and power
6. Final gate level netlist (“./results/your_filter.v“)
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Synthesis for ST65 – Simulation script
Remarks on “execute_sim.tcl“
1. Loading core libraries
2. Loading of gate level netlist (“./results/your_filter.v“)
3. Setting the actual frequency you want to run at
change this in “sim/files/fir_filter_tb.vhd”, too
4. Simulating the design with VCS-MX
5. Back annotation of activities
6. Final results report (“./results/design_report.txt“)
Area, timing and power
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Synthesis for ST65 – Hints
• Take a look into the scripts and modify them with a text editor
• Consider the warnings and errors
• Synopsys help:
Man Pages for commands, variables and messages are available under
Help in the Design Vision GUI
Design Vision User Guide:
/eda/synopsys/2015-16/RHELx86/DOCS_2015.12/dc/dvug.pdf
Design Compiler Optimization Tutorial:
/opt/lehre/vlsi/dcrmo_rel1112.pdf
Design Compiler User Guide :
/eda/synopsys/2015-16/RHELx86/DOCS_2015.12/dc/dcug.pdf
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Synthesis for ST65 – Further options/hints
• Desired Speed: frequency …
• Desired Area: set_max_area …
• Desired Power: set_max_dynamic_power …
• Help in the command window: help compile
• Priorities for optimization (set_cost_priority):
max_transition, max_fanout, max_capacitance, cell_degradation,
max_delay, min_delay,….
• Setting targets (with reasonable values):
set_max_transition, set_max_fanout, set_max_capacitance, …
• Net Infos (capacitance, activity, fanout …): report_power –net, report_net
• Cell info (area, activity, leakage …): report_power –cell, report_cell
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Synthesis for ST65
User options within Design Vision
Menu:
Attributes > Optimization constraints > Design constraints
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Synthesis for ST65
User options within Design Vision
• Menu:
Attributes >
Optimization directives >
Design
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Synthesis for ST65 – Advanced hints
• Choose cells to be used/not used:
1. Definition in VHDL description
set_dont_touch LIBRARY/CELL_NAME
2. Definition for script
set_dont_use LIBRARY/CELL_NAME
E.g. set_dont_use CORE65LPSVT/HS65_LS_FA1X4
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Remark on timing
Steps in synthesis script1. frequency = 300 peri = 1000.0 / frequency
2. create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" }
Timing report:
• Desired target frequency = clk signal = 300 MHz period = 3.33 ns
E.g. library setup time -0.06
data required time 3.27
data arrival time -4.32
slack (VIOLATED) -1.05
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Remark on timing
Steps in synthesis script1. frequency = 300 peri = 1000.0 / frequency
2. create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" }
Timing report:
• Desired target frequency = clk signal = 300 MHz period = 3.33 ns
E.g. library setup time -0.06
data required time 3.27
data arrival time -4.32
slack (VIOLATED) -1.05
Tmin = tlogic + tsetup
Tmin = clk – slack
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(considers already registers)
(critical path delay)
FF FFLogic
clk
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Task and further information for phase 4
• Target: Presentation of results for a working and
optimized ST65 netlist, running at one GHz.
(Observe/discuss differences to FPGA results)
• Do not lock computers, at least leave a notice.
Notice visible in front of the machine
Your name
Project and name of advisor
• Particularly important because licenses are locked.
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Task and further information for phase 4
• Target benchmark: 𝑴𝒆𝒕𝒓𝒊𝒄 =𝑭𝒓𝒆𝒒𝟐
𝑨𝒕𝒕 ∗(𝑷𝒍𝒆𝒂𝒌 + 𝟎.𝟎𝟏∗𝑷𝒅𝒚𝒏)
• Required speed: 1 GHz!
• Consider impact on your design:
Differences to FPGA
Architecture (adders, multipliers, pipelining …)
Synthesis targets
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1 % Duty Cycle
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Task and further information for phase 4
Handover
• Upload your presentation (pptx or pdf)
• Submit the following files:
– Verilog netlist (./results/your_filter.v) of your final design
– Vhdl-files of your final design
– Synthesis script (synthesize_design.tcl) that has led to your final
netlist
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General remarks
• Check the integrity of your submitted files
• Submit your files in time
• Marks depend on systematic approach
don’t use trial-and-error strategies
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Full Grade
Penalty!!!
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Target: Presentation of results for a working and optimized
ST65 netlist.(Observe/discuss differences to FPGA
results)
Design Deadline: January, 6th, 23:59
Presentation Deadline: January, 7th, 23:59
Next meeting: January, 8th
Questions?