lab 9 asic logic

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Lab 9 ASIC Logic

第八組R91943003 陳方玉R91943007 陳建宏R91943072 柯鴻洋R89921022 吳佑焉

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Outline

Introduction to the ASIC Logic Experiment Steps RGB to YUV Conversion HW Module

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Outline

Introduction to the ASIC Logic Experiment Steps RGB to YUV Conversion HW Module

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Basics for Prototyping with Logic Modules

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Basic Platforms: AHB

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Core Module / Motherboard

memoryand peripherals

PCI

Core modulealias memory

Logic module 0

Logic module 1

Logic module 2

Logic module 3

LM registers

Interrupt

SSRAM

Bus Error response

test_register

0xC0000000

0xD0000000

0xE0000000

0xF0000000

0xC0000000

0xC1000000

0xC2000000

0xC21000000xC2100004

0xCFFFFFFF

Logic Module Registers

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Outline

Introduction to the ASIC Logic Experiment Steps RGB to YUV Conversion HW Module

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Steps for Example 1

(1)Flash the LEDs on the Logic Module from left to right.

(2)The speed of flashing the LEDs from left to right can be set by changing the configuration of the 8-way switch.

(3) Comparison of programming FPGA

FPGA version: programs the FPGA by writing the bit stream image into the FPGA directly. The image will start running right after programming into the FPGA.

Flash version: programs the FPGA by writing the bit stream image into the flash. The image will start after next power up of the development system.

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Setting Clock FrequencyControl Clock Frequency

by 8-Way Switches

Steps of Example 1

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(1)Determine the DRAM size on the Core Module and set up the system controller(2)Make sure the Logic Module is present in the AP expansion position(3)Report module information(4)Set the Logic Module clock frequencies(5)Test SSRAM for word, halfword, and byte accesses(6)Test the custom design device’s single register access Flash the LED(7)Remain in a loop that displays the 8-way switch value of the Logic Modules on its LEDs.

These steps are the same as in experiment 8:

AMBA BUS

Steps of Example 2

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Reminder

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Reminder

Remember to set the third switch on Program FPGA from Image 0

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Experiment Steps:example2

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Outline

Introduction to the ASIC Logic Experiment Steps RGB to YUV Conversion HW Module

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RGB to YUV Conversion

Implement with pure software. Implement with hardware.

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LM_MYIP=0xC2200040

Memory Definition

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RGB to YUV Program

(1)Add MYIP.v into top module.(2)Modify AHBDecoder.v.(3)Modify AHBMuxS2M.v.(4)Modify AHBAHBTop.v.

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Architecture

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Modification of AHBAHBTOP.v

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RGB to YUV Program

Modification of AHBDecoder.v

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RGB to YUV Program

Modification of AHBMuxS2M.v

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MYIP.v modified from AHBZBTRAM.v

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Divide HWDATA into r,g,b parts

Combine y,u,v into output HRDATA (2:1:1)

MYIP.v modified from AHBZBTRAM.v

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Initialize LM Module

Software Implementation

Write RGB value into LM_MYIPand read YUV as data_myip

Post processor for data_myip to read out YUV value

Logic.c

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Set Registor for LM_MYIP

Logic.h

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Input parameters

Result of Pure Software Implementation

Result of Hardware Implementation

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Verilog Coding

Confusion btw. Signed and Unsigned Multiplication

Truncation 負數的二進位轉換 小數點對齊

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Integrator ASIC Platform [DUI_0098B_AP_UG] System Memory Map [DUI_0098B_AP_UG 4.1]

Reference