ce4501 - cces.psau.edu.sa · lab-manual (vlsi technology and design) page 3 experiment - 1 aim :...

CE4501 VLSI DESIGN LAB

Kingdom of Saudi Arabia

Ministry of Education Prince Sattam Bin Abdulaziz University College of Computer Engineering & Sciences

Department of Computer Engineering

الصعوديةاململكة العربية

وزارة التعليم

جامعة األمري شطام بن عبدالعسيس

كلية هندشة وعلوم احلاشب

قصم هندشة احلاشب

Laboratory Safety :

Please read these Safety Guidelines, Safety is a priority at Prince Sattam Bin

Abdulaziz University .While it may seem unlikely that an accident could happen to

you, you should know the accident rate in universities is 10 to 100 times greater than

in the chemical industry. To help prevent accidents, safety notes are included in the

lab manual. In addition, any relevant Material Safety Data Sheets (MSDS) are

posted in a laboratory binder and guidelines.

Pay close attention to this information – our goals are:

1. To avoid accidents in the lab, and

2. To respond promptly and appropriately should an accident occur.

Safety depends on you!

It is your responsibility to follow the instructions in

the lab manual and any additional guidelines provided

by your instructor. It is also your responsibility to be

familiar with the location and operation of safety

equipment.

General Laboratory Safety Guidelines

• Wear appropriate protective clothing. Do not wear open-toed shoes, sandals,

shorts or shirts with dangling sleeves. Tie back long hair and avoid dangling

jewelry.

• Clean your workstation after each lab period, and return all equipment

and materials to appropriate stations before leaving the lab.

• Always turn off the power before working on any electric circuit or electronic

device.

• When operating with electric circuits and electronic devices other than just a

computer, you must work in pairs or teams.

• When in doubt about the operation of any circuit or device in lab, always have an

instructor check your work before connecting power to your system.

• Report any safety issues or violations that you are aware of as soon as

possible to your course instructor and program director.

• Ensure that you have a safe buffer area around you and that you are working

on an appropriate surface when using soldering irons in the lab.

• Always make sure that all lab equipment, soldering irons, project circuits

are powered down before leaving your lab area.

• Ensure that your work environment is clear and free of debris before starting your

work AND after finishing your project.

• Never block walkways in the laboratory with lab equipment, cables, and electrical

power cords.

• Do not eat, drink, smoke, or apply cosmetics in the laboratory.

• Avoid all horseplay in the laboratory.

• Dispose of sharps waste properly — place broken glass in the glass discard

container, metal in the metal waste container, and place other waste materials in

the designated container(s). Secure all sharps, including needles, blades, probes,

knives, etc.

INDEX

Lab-Manual (VLSI Technology and Design) Page 2

Sr. No.

Title of the experiment

1 Introduction to Back-end Design Tools - Microwind.

2

Draw a layout of Resistive Load Inverter & CMOS Inverter using CMOS 0.12um technology and simulate its transient characteristics.

3 Draw a layout of CMOS NAND Gate using CMOS 0.12um technology and simulate its transient characteristics.

4 Draw a layout of CMOS NOR Gate using CMOS 0.12um technology and simulate its transient characteristics.

5 Draw a layout of CMOS Half Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.

6 Draw a layout of CMOS Full Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.

7 Compare Transfer Characteristics of CMOS, Resistive Load and NMOS Load Inverter.

8 Draw a layout of CMOS XOR Gate using CMOS 0.12um technology and simulate its transient characteristics.

9 Simulate Substrate Bias ( Body ) effect in CMOS inverter.

http://www.gecdahod.ac.in/


Experiment - 1

Aim : Introduction to Back-end Design Tools - Microwind.

MICROWIND TOOL MICROWIND3 is user friendly layout and simulation tool for sub-micron CMOS design. The MICROWIND3

allows the designer to simulate and design an integrated circuit at physical description level. The package

contains a library of common logic and analog ICs to design and simulate. MICROWIND3 includes all the

commands for a mask editor as well as verification tools never gathered before in a single module.

MICROWIND3 is truly a complete and cost-effective design solution for your CMOS design.

nanoLambda VirtuosoFab MEMsim PROthumb PROtutor

DSCH Schematic editor and simulator User-friendly environment for rapid design of logic circuits.

Handles both conventional pattern-based logic simulation and intuitive on-screen mouse- driven simulation.

Supports hierarchical logic design. Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible with

PSPICE™ and WinSpice™). Current and power consumption analysis.

Generates a VERILOG description of the schematic for layout editor.

Immediate access to symbol properties (Delay, fanout). Sub-micron, deep-submicron, nanoscale technology support. Supported by huge symbol library.


NanoLambda Precision CMOS Layout tool upto 35 nanometers. Sub-micron, deep-submicron, nanoscale technology support.

Unsurpassed illustration capabilities.

Design-error-free cell library (Contacts, vias, MOS devices, etc..)

Advanced macro generator: capa, self, matrix, ROM, pads, path, etc..)

Incredible translator from logic expression into compact design-error free layout. Powerful automatic compiler from VERILOG circuit into layout.

On-line design rule checker: width, spacing, overlap, extension rule verification.

Built-in extractor which generates a SPICE netlist from layout.

Extraction of all MOS width and length.

Parasitic capacitance, crosstalk and resistance extracted for all electrical nodes.

Import/Export CIF layout from 3rd party layout tools. Up to 100,000 elementary boxes.

Lock & unlock layers to protect some part of the design from any changes.

Enhanced editing commands and layout control.

Support upto 8 metal layers for DSM technologies.

Global delay evaluation of circuit.

Global cross talk analyzer.

Inversion of diffusions boxes.

Easy label listing.

Enhanced mathematical signal description. Zoom in navigator.

Support till 22 nanometer technology. Enhanced memory utilization for faster simulation. Silicon atom viewer.

Technology library available Minimum feature size Cmos12.rul 1.2mm Cmos08.rul 0.7mm

Cmos06.rul 0.5mm

Cmos035.rul 0.4mm

Cmos025.rul 0.25mm Cmos018.rul 0.2mm

Cmos012.rul 0.12mm

Cmos90n.rul 0.1mm

Cmos70n.rul 0.07mm

Cmos50n.rul 0.05mm


Experiment - 2

Aim : Draw a layout of Resistive Load Inverter & CMOS Inverter using CMOS 0.12um technology and simulate its transient characteristics.

(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms


CMOS Inverter (CMOS 0.12um TECHNOLOGY using Microwind3)



Experiment - 3

Aim : Draw a layout of CMOS NAND Gate using CMOS 0.12um technology and simulate its transient characteristics.




Experiment - 4

Aim : Draw a layout of CMOS NOR Gate using CMOS 0.12um technology and simulate its transient characteristics.




Experiment - 5

Aim : Draw a layout of CMOS Half Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.




Experiment - 6

Aim : Draw a layout of CMOS Full Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.




Experiment - 7

Aim : Compare Transfer Characteristics of CMOS, Resistive Load and NMOS Load Inverter.



Experiment - 8

Aim : Draw a layout of CMOS XOR Gate using CMOS 0.12um technology and simulate its transient characteristics.




Experiment - 9

Aim : Simulate Substrate Bias ( Body ) effect in CMOS inverter.



ce4501 - cces.psau.edu.sa · lab-manual (vlsi technology and design) page 3 experiment - 1 aim :...

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