coniston 硬體線路說明 2006/09/04 rdee3

ConistonConiston

硬體線路說明硬體線路說明

2006/09/04 RDEE32006/09/04 RDEE3

Basic conceptBasic concept Block DiagramBlock Diagram Power up timing BlockPower up timing Block Power up flowchartPower up flowchart Circuits Exploded BlockCircuits Exploded Block VGA portionVGA portion

Agenda

Basic conceptBasic concept

What is the Bus?What is the Bus? A data transmission channel between ICs .A data transmission channel between ICs . Two types Bus – Parallel and serial BusTwo types Bus – Parallel and serial Bus How to debug Bus:How to debug Bus:

每一種每一種 Bus Bus 都有自己的都有自己的 protocolprotocol ，傳輸資料時無法以，傳輸資料時無法以示波器知道示波器知道 Bus Bus 現在在做什麼現在在做什麼 (( 一般以一般以 LA LA 為工具為工具 ).).

系統設計時就確保系統設計時就確保 Bus Bus 是健全的是健全的 , , 所以………所以……… ....• 先找出那個先找出那個 Bus Bus 出問題出問題 ..• 若整個若整個 Bus Bus 不動不動 ,, 先查先查 CLK, power (CLK, power ( 過過 bead)bead) 及控制訊號及控制訊號 ..• 目視相關線路零件有無空焊目視相關線路零件有無空焊 ,, 短路或錯料短路或錯料 ..• 以示波器直接掃瞄以示波器直接掃瞄 Bus Bus 有無短路有無短路 ,, 斷路斷路 ..• 照照 X ray.X ray.

Parallel BusParallel Bus

D0..

D64

A3..

A16

ADS#DRDY#

.

.TRDY#

D0..D64

A3..A16

ADS#DRDY#..TRDY#

Data Bus

Address Bus

Control Bus

Clocks

Parallel Bus 有 FSB, PCI, IDE, DDR, FDD, Parallel port

Serial BusSerial Bus

Data

CLK

Data

CLK

Data/Address/Control Bus

Serial Bus 有 DMI, PCIE, SATA, AC97, USB, IR,

IC active sequenceIC active sequencePower

Clocks

Power good

ResetSome ICs complete Power good and Reset together ex. ICH

What is +V?A, +V?, +V?SWhat is +V?A, +V?, +V?S

電源插入時

系統開機後

系統進入待命

系統關機或進入休眠

+V?A

+V?A, +V?, +V?S

+V?A, +V?

+V?A

Block DiagramBlock Diagram

Coniston Block DiagramConiston Block Diagram

Power up timing BlockPower up timing Block

Power up timing BlockPower up timing Block

KBC ICH

Power IC

Charger

Clock-G

NB CPU

Reset IC /DC +V3A/+V5A

AdapterAdapter

Battery

+VBAT

+V3A/+V5A

1 2

3

Power button

4

RSMRST#

5

SLP_S5/S4/S36

7IMVP_CKEN

8 Clocks out

Power up timing Block Power up timing Block Cont.Cont.

KBC ICH

Power IC

Charger

Clock-G

NB CPU

Reset IC /DC +V3A/+V5A

PWROK9

PLT_RST#

11H_CPURST#

12

H_ADS#13

H_PWRGD10

Coniston power up timingConiston power up timing

Coniston power up timing Coniston power up timing cont.cont.

Coniston Power up timing Coniston Power up timing cont.cont.

Power up flowchart

Power Up FlowchartPower Up Flowchart First Step – Power InFirst Step – Power In

Charger CircuitsCharger CircuitsU716 (sheet4)U716 (sheet4)TI_BQ24721TI_BQ24721

Adapter In 19VAdapter In 19V ORORBattery In Battery In

+V5LA source+V5LA source++V3LA SourceV3LA SourceU32 (sheet6)U32 (sheet6)TI_TPS51120TI_TPS51120

Reset ICReset ICU29 (sheet5)U29 (sheet5)GMT_G680LT1GMT_G680LT1

+VBAT

+VBAT

+V5LA +V5AUXON

DC/DC (+V3A/+V5A)U32 (sheet6)TI_TPS51120

+V_RTC sourceD718 (sheet 39)

BAT54C+V5AUXON

+VBAT

+V3A

+V5A

+V_RTC

KBC activeU25 (sheet52)

KBC1122

BIOSU1500 (sheet53)SST_39VF080

Access BIOS

Power Up FlowchartPower Up Flowchart 2’th Step – Push power button2’th Step – Push power button

This page shows power sequence between power button to all system powers up

KBC1122U25 (sheet52)

ICH7U708(sheet39~43)

U707 (sheet8)Ti_TPS51124RGER

Q729 (sheet10)A04406

+V3A

32.768KHz

PWR_SWIN#_3

32.768KHz

+V_RTC

LOW_BAT#

Q52,Q53(Sheet12)

Q36


+VGAVCC

+V1.5S_PWRGD

+V1.8

U718 (sheet10)GMT_G966

U22(sheet10)GMT_G2997F6U

RSMRST#

+V1.8S

+V5S

+V3S

+V1.2S

+V0.9S

M_VFER

SLP_S3#_3R

SLP_S5#_3R

SLP_S3#_3R

SLP_S5#_3R

U27 (sheet10)GMT_G966

+V2.5S

+V5S

+V1.5S


+V1.5S

Power Up FlowchartPower Up Flowchart 3’th Step – CPU power up and Reset timing3’th Step – CPU power up and Reset timing

U5 (sheet12)

NC7W17U709(sheet7)ADI_ADP3207

CN712 (sheet14~17)

CPU

U707 (sheet8)Ti_TPS51124

U708 (sheet41)ICH7

+V1.5S_PWRGD

SLP_S3#_3R

VR_PWRGD_CK410

+V5AUXON

VR_PWRGD_CK410

U7 (sheet7)NC7WZ17

+VCCPIMVP_CKEN#

U717 (sheet20)945PM/GM

U25 (sheet52)KBC1122

PWR_GOOD_#

PM_PWROK

IMVP_CKEN#

MCH_GOOD

Clocks

+VCC_CORE

SLP_S3#_3R

SB_3S_VRMPWRGD

PLT_RST#

H_CPURST#

U28 (sheet13)ICS9LPR316

H_ADS#

H_PWRGD

Circuits Exploded BlockCircuits Exploded Block

Reset IC Reset IC

Page 5

thermal IC 過熱時會透過 KBC 拉 low 關閉整個系統電源

開啟 +V3A/+V5A 的第一個訊號

+VBAT (lo)= 7.59V = 1.245 X( R1+R2+R3) / (R2+R3)+VBAT (hi)= 8.27V = 1.245 X (R1+R2+R3) / R3

+V5AUXON will declare DC/DC circuits to output +V3A/+V5A

(R1)

(R2)

(R3)

Another control logic for +V5AUXONAnother control logic for +V5AUXON

Page 72

也就是說 DC mode 要等 user 按 power Bottom 才會將 +V5A,+V3A 打開AC mode EC 會自動將 +V5A, +V3A always 的電打開

DC/DC DC/DC +V3A, +V5A, +V5LA+V3A, +V5A, +V5LA

Page 6

EC activeEC active這是 EC 的 Power Bottom 訊號

KBC 第一次收到 PWR_SWIN#_3 low 時 , 會把 RSMRST# 拉 high to reset ICH

Page 52

這是 Power Switch 的訊號

RSMRST# is for KBC to reset ICH

Make sure 32.768KHz is oscillating.

EC_PWRSW# is for KBC to power on ICH, In normal it will be high.

南橋要開電前的必要條件南橋要開電前的必要條件

1. RTC have to be oscillating(32.768KHz).2. RTCRST# have to be high.3. RSMRST# have to be inactive (high).4. PWRBTN# have a trigger.5. LOW_BAT#_3 have to be inactive (high).

If true, then ICH will issue SLP_S3#_3R / SLP_S4#_3R.

Page 40

Page 39

南橋會送出南橋會送出 S3#,S5#S3#,S5# 的訊號去開啟的訊號去開啟系統系統 +V? +V?S +V? +V?S 的電源的電源

Page 40

SLP_S3#_3R turn on +V?S powers

SLP_S4#_3R turn on +V? powers

南橋會送出南橋會送出 SLP_S3/SLP_S4 SLP_S3/SLP_S4 去開啟系統去開啟系統所有需要的電源所有需要的電源

Page10

電源概分兩種 : PWM & LDO. 但開電的必要條件都一樣 ~~ source power, enable pin

以下兩種線路都是 LDO type

Source power

Enable Pin

Power_GoodPower_Good 訊號的產生與目的訊號的產生與目的

Page 12

When All +V?S/+V? powers are ready, PWR_GOOD_3 will tie to

high to turn on CPU powers (+VCCP and +VCC_CORE).

確認 CPU 外的電源都已起穩定 , 並準備去開 CPU powers.

開啟開啟 +VCCP+VCCP 電源和電源和MCH_GOODMCH_GOOD 的產生的產生

Page 54

PWR_GOOD_3 turn on +VCCP

When +VCCP is ready, this DC circuits will issue MCH_GOOD to turn on +VCC_CORE.

開啟開啟 +VCC_CORE+VCC_CORE 電源和電源和VR_PWRGD_CK410 / IMVP_CKEN# VR_PWRGD_CK410 / IMVP_CKEN# 的產生的產生

Page 7

MCH_GOOD enable IMVP to generate +VCC_CORE

When +VCC_CORE power is ready, VR_PWRGD_CK410 will go high to inform

system that CPU powers are ready.

When +VCC_CORE is ready, IMVP_CKEN# will go high to enable

clock-G

CLOCKs CLOCKs 的產生的產生

Page 13

Turn on all clocks by IMVP_CKEN#

PCI_STOP#_3 and CPU_STOP#_3 must be at high otherwise some

clocks will be turned off.

Chipset’s power good Chipset’s power good 產生產生

Page 7

當 CPU power 穩定時 , 用 VR_PWRGD_ck410 經 delay 線路產生 SB_3S_VRMPWR

GD 通知南橋及 KBC – cpu 電源已穩定

為確保 clocks 已穩定送出 , 所以再經一次 delay 送出 PM_PWROK 給南北

橋

南橋南橋 Power GoodPower Good 的來源的來源

南橋收到這兩個 power good 訊號後 , 會 reset 內部的邏輯線路 , 並發 H_PWRGD 告之 CPU 電源控制部分已備妥 . 接著發 PLT_RST# reset 北橋 , 然後起動 DMI 與北橋溝通 .

Page 40

RESETRESET 北橋北橋

南橋會送 PLT_RST#來 Reset 北橋

Page 18

FSB BUS FSB BUS 的第一個訊號的第一個訊號

ADS# 是 RESET CPU 後的第一個系統訊號去和北橋溝通

Page 14

DMI DMI 的第一個訊號的第一個訊號

這是北橋和南橋間的溝通訊號

Page 18

ICH ICH 與與 KBC KBC 間的間的 Bus - LPCBus - LPC LPC LPC 的第一個訊號的第一個訊號

量測 FRAME#看 LPC 是否有動作

Page 39

系統讀系統讀 FLASH ROMFLASH ROM的第一個訊號的第一個訊號

量測 FLASH 看系統是否有解到FLASH ROM的第一個位址Page 53

希望這份資料對各位有幫助希望這份資料對各位有幫助如果有問題請電郵如果有問題請電郵Power MemberPower Member 謝宗翰謝宗翰 [email protected]@inventec.com

EE MemberEE Member 溫淑惠溫淑惠 [email protected]@inventec.com 范仁和范仁和 [email protected]@inventec.com

謝謝指教謝謝指教

coniston 硬體線路說明 2006/09/04 rdee3

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