logic simulation 한양대학교 신현철 교수 [email protected]

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Logic Simulation 한한한한한 한한한 한한 [email protected]

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Page 1: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

Logic Simulation

한양대학교신현철 교수

[email protected]

Page 2: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Circuit Simulation (1/2) Real-delay Simulation (Using HSPICE)

V1

V2 Vout2

Vout1

Page 3: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Circuit Simulation (2/2) Zero-delay Simulation (Using ModelSim)

V1

V2 Vout2

Vout1

Page 4: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Logic Simulation (1/3) Digital Logic Circuit Diagram

Boolean Function Y = (A&B) | (!(B&C)&D) Z = (!(B&C)&D) | (!(B&C)&E)

A

B

C

D

E

W1

W2 W3

W4

Y

Z

ISCAS’85 C17 benchmark circuit

Page 5: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Given the boolean function of a net, you can calculate the logic value.

If the circuit size is doubled, the cost for logic simulation will be quadrapled. Recently, the number of CPU gates is over one million.

Ex) Pentium 4 chipset, Altera FPGA, …

Logic Simulation (2/3)

Page 6: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

If the boolean function is simplified, logic simulation time becomes shorter. Simplification of boolean function using BDD Simplification of boolean function using Espresso tool Simplification of boolean function using SIS tool

But, if the input vector is changed, all logic values of the nets have to be recalculated. Simulation cost is still high.

If only changed values are calculated, simulation time can be shorter.

Logic Simulation (3/3)

Page 7: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Circuit Data Structure (1/3)

1

3

6

2

7

22

23

10

11

19

16

Input Pattern (ISCAS’85 C17 benchmark circuit)

output gate typeinput

10 5 1 3

11 5 3 6

16 5 2 11

19 5 11 7

22 5 10 16

23 5 16 19

** Gate type ** Inverter : 2 AND gate : 3 OR gate : 4 NAND gate : 5 NOR gate: 6 XOR gate: 7 XNOR gate : 8 INPUT PIN : 0 OUTPUT PIN : 1

Page 8: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Circuit Data Structure (2/3)

1

3

6

2

7

NANDGATE

NANDGATE

10

11 NANDGATE

NANDGATE

16

19

NANDGATE

NANDGATE

22

23

1

3

6

2

7

22

23

10

11

19

16

Build Graph

Page 9: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Circuit Data Structure (3/3)

Total switching countSuccessor netPredecessor net

Current logic valuePrevious logic value

LevelNet ID

Gate type

Predecessor net

Predecessor net Successor net

1

3

6

2

7

NANDGATE

NANDGATE

10

11 NANDGATE

NANDGATE

16

19

NANDGATE

NANDGATE

22

23

Vertex Structure

Page 10: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Level Decision Algorithm Pseudo code

Initialize all logic level to 0Current queue = primary inputsWhile (current queue != empty) { for (nets in current queue) { level of gate += 1 if (level of gate is change) next queue <- output net of the gate } if (current queue = empty) { current queue = next queue; next queue = empty }}

Page 11: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Level Decision Algorithm Initialize level to 0 and schedule primary inputs

A

B

C

D

E

W1

W2 W3

W4

Y

Z

0

0 0

0

0

0

Page 12: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Level Decision Algorithm Decide level

A

B

C

D

E

W1

W2 W3

W4

Y

Z

1

1 1

1

0

0

A

B

C

D

E

W1

W2 W3

W4

Y

Z

1

1 2

2

3

3

Page 13: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Logic Calculation Algorithm Pseudo code

Initialize all logic valuesSchedule changed primary inputsWhile (schedule != empty) { update nets in order of level for (gates whose outputs are changed) schedule output of the gate}

Page 14: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Logic Calculation Algorithm (1/3) Initialize all logic values

A

B

C

D

E

W1

W2 W3

W4

Y

Z

1

1 0

1

1

1

0

1

0

1

0

Page 15: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Logic Calculation Algorithm (2/3) Calculate logic value

A

B

C

D

E

W1

W2 W3

W4

Y

Z

0

1 0

1

1

1

1

0

0

1

0

A

B

C

D

E

W1

W2 W3

W4

Y

Z

0

1 0

1

1

1

1

0

0

1

0

A

B

C

D

E

W1

W2 W3

W4

Y

Z

0

1 0

1

1

1

1

0

0

1

0

Page 16: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

16

Logic Calculation Algorithm (3/3) Calculate switching count

A

B

C

D

E

W1

W2 W3

W4

Y

Z

1 - 0

0

1

1

1

1-1

0-1

1-0

0-1

0-0

1 - 0

A

B

C

D

E

W1

W2 W3

W4

Y

Z

0

0

0-1

1-1

11

0

0

1

11

A

B

C

D

E

W1

W2 W3

W4

Y

Z

0

0

1

1

1-1

1

1

1

0

01-0

Level 0 : 3Level 1 : 2

Level 2 : 1 Level 3 : 1

Page 17: Logic Simulation 한양대학교 신현철 교수 shin@hanyang.ac.kr

CAD and Design Project Course for SoC

Result Format

You are to print the switching count of each gate and the

total switching count for each

level.

################################################################## RESULT!!! #

#################################################################

####### 0 Level ####### 6 Net's Switchng count : 2 5 Net's Switchng count : 1 4 Net's Switchng count : 2 3 Net's Switchng count : 1 2 Net's Switchng count : 2 1 Net's Switchng count : 1

************************* 0 Level's Total Switching count : 9

####### 1 Level ####### 21 Net's Switchng count : 2 10 Net's Switchng count : 2 9 Net's Switchng count : 0 8 Net's Switchng count : 1 7 Net's Switchng count : 1

************************* 1 Level's Total Switching count : 6

####### 2 Level ####### 17 Net's Switchng count : 2 16 Net's Switchng count : 0 15 Net's Switchng count : 0 14 Net's Switchng count : 0 13 Net's Switchng count : 0 12 Net's Switchng count : 1 11 Net's Switchng count : 1

************************* 2 Level's Total Switching count : 4