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Risk Analysis during Deep Submicron ULSI Process Caused by Metal

Contamination

Po-Ying Chen1 , Shen-Li Chen2, Long -Yeu Chung3, Cheng-Chia Kuo3 and Wen-Kuan Yeh4

1 Department of Information Engineering, I-Shou University, NO.1, Sec. 1, Syuecheng Rd., Dashu Township, Kaohsiung

county, 840 , Taiwan (R.O.C.)

Tel: 886-7-6577711 ext 3394, Fax: 886-7-6577056, E-mail: PLin121@ms.ccafps.khc.edu.tw2 Department of Electronic Engineering, National United University, 1, Lien-Da, Kung- Ching Li, Miaoli 360,

Taiwan,

3Department of Electrical Engineer, Tung Fang Institute of Technology, NO.110, Tung Fang RD, Hu-Nei

Shang, Kaohsiung, Taiwan4Department of Electrical Engineering, National University of Kaohsiung

Abstract

Heavy metals such as Cu, Fe and Ni are well known to cause defects in Si substrate and degradation

of thin oxide quality in the ULSI circuits. Subsequently, this degradation in turn can severely restrict yield

and long term reliability, which are the two critical parameters in ULSI manufacturing.

The origin of these metallic contaminations can vary from process materials such as not only gases but

also wet chemicals to process equipment. As device geometry continuously shrinks, micro-contamination

has an increasingly negative influence on function yield. Semiconductor manufacturers can significantly

enhance the wafer yield by reducing the contamination problem. This investigation analyzes the

contamination of heavy metals on process wafers prior to gate oxide deposition. Many new-bamboo-like

defects are easy to discover on the wafer edge. Additionally, many pits also can be found in the active

region of a device, since the silicon substrate suffers heavy metallic contamination. TEM and EDS are

employed to investigate the new-bamboo-like defects and pits defects. A reasonable mechanism was

developed to verify the problem stage of manufacturing process.

This investigation demonstrates, for the first time, that the metal contaminant drives a spontaneous

generation reaction of dissolution between the contaminated metal and silicon substrate. Tiny pits exist on

the silicon surface. These pits become increasingly significantly in sub-micrometer and

deep-sub-micrometer ULSI’s(less than 0.13 um) manufacturing process, which always suffer yield loss in

wafer edge from new-bamboo-like defects owing to design rule limitation. A detailed analysis and process

flow check has concluded that metal contamination would lead to tiny pits located around wafer edge in

raw material wafer process flow. These tiny pits could result in new-bamboo-like defects in the non-OD

(periphery) region and 0.02 μm pits in the OD (active) region. These two defects cause device operation

to faille due to leakage.

This investigation is the first to report this issue in the ULSI manufacturing process, and observes that

tiny pits represent a high risk parameter at the deep submicron level. The effective solution is to manage the

metallic contamination level more tightly

Keywords: Pit, Metal contamination, Wet bench clean, Semiconductor process, New-bamboo-like defects

I. Introduction:

Device yield may be lowered if the wafers are contaminated during manufacturing process by metals

such as Al, Fe, Cr, W, and Ta, to name a few. These metals are frequently adopted in semiconductor

construction, and can be transported to wafer by puttering, beam constituents, or as chemical process.

Contamination issues in the microelectronic industry continue to play a crucial role in attaining the

industry’s roadmap goals. For the submicron technology nodes, in addition to metals and particles, organic

compounds are all suspected to be among the critical contaminants.

Previous works [1] have revealed that process chemicals in use today are even quite pure; depending

upon the grade used, but can easily be contaminated with metal ions through inappropriate handing or

storage techniques. Such metal impurities, if deposited on the wafer surface during processing can create a

generation-recombination center in silicon increasing reverse-bias junction leakage by dislocation

decoration and stacking fault formation [2]. Such device performance degradation can adversely affect the

function of ultra-large-scale integrated (ULSI) circuits. Because metal contamination can come from

several sources [3], the levels of contamination that are acceptable for a particular application and

effectiveness of the wafer cleaning solutions are important to determine. Additionally, test structures

provide an effective tool for measuring the effects of metallic homogeneous contamination on simple

device structures.

Perhaps the most influential impact is on the gate dielectric fabrication process, in which

contamination between pre-gate oxidation cleaning and thermal oxidation and before poly deposition can

result in substantial degradation of gate oxide integrity [4-6]. Because ultra-thin gate oxides thickness is

below 30 Å, the adsorbed heavy metal contaminant is expected to cause accelerated breakdown of CMOS

gates [7].

In the next stage of copper interconnection technology development, the application of the

technology to CMOS devices and circuits with a ULSI-size pattern need to be explored. To enable devices

to operate normally, the copper metallization process must be designed as part of the entire fabrication

process. If process-induced copper contamination remains on the surface, then it penetrates the active

devicearea, thus deteriorating device characteristics, because copper diffuses very quickly through 2SiO

even at a low temperature [8]. Therefore, an effective cleaning process and the formation of a metal

diffusion stopper are therefore extremely important in the metallization process.

Extended research has been performed to identify the sources of metal contaminants in a

clean-room environment. A previous study has revealed that the manufacturing tools cause contaminations

by heavy metals including Al, Zn, Ni, Cu and Fe in the order of 1210 1410 atoms/ 2cm [9]. Meanwhile,

to examine the effects of these contaminants in the subsequent wet cleaning process, the cleaning of

contaminated wafers in various chemical baths such as BOE (Buffered Oxide Etch), diluted HF, 22OH and

SC-1 (NH4OH+H2O2+H2O) must be examined. Additionally, the contamination levels of the bath chemicals

as well as the processed wafers surfaces should be measured using different analytical approaches.

Experimental results demonstrate that most contaminants can be eliminated from the wafer surfaces

through these chemical cleanings, but copper contamination remained on the surface without much

reduction.

This investigation explored the contamination of heavy metals on bare silicon wafer following wet

cleaning process and its effect on the subsequent manufacturing process. Additionally, the different defects

on the device-area and non-active area were also examined. The experimental results can provide

information for solving complex problems in the future development of technology.

This work covers four broad subjects: (1) the risk of low-concentration heavy metal

contamination, below which can be detected by current detection tools (e.g., EDS, SIMS, TXRF); (2) the

reason why the IC development roadmap needs to define the control specification in metal contamination,

(3) problems in deep submicron generation IC process resulting from heavy metal atoms encountering Si to

become ion with charge (+1), making them easy to dissolve in DI water, and. (4) how long duration does it

need for these tiny pits to create?

II. Experimental:

The MOS capacitors with 2SiO gate dielectric were fabricated on P-type (100) Si substrate, which

were CZ-grown boron-doped wafers with a resistivity of 8-12 Ω-cm 8-inch wafer. The analyzed low-yield

wafers were belonged to a 0.13μm-generation process before gate-oxide deposition. The suffered low

yield wafers was detected using a KLA-Tencor surface detect defector. The morphology of the cleaned Si

surfaces was measured using a KLA-Tencor defect detector. A KLA-Tencor defects detector was also

employed to detect the defects by using gray-level theory in the critical process.

The surface concentration of heavy metals, Fe and Cu on silicon surfaces before and after the

ultra-pure SC-1 cleaning was compared for various levels of initial wafer surface Cu or Fe concentration

and also for different numbers of wafers simultaneously immersed in the bath. The SC-1 solution was

prepared by mixing de-ionized (DI) water with an 22OH (30%) solution and a OHNH 4 solution (30%).

The blend ratio was OHNH 4 : 22OH : OH 2 =1:1:5. The Fe and Cu concentrations in the SC-1 solution

were both under 0.02ppb, which was near the detection limitation of atomic absorption spectrometry. The

solution temperature was maintained at 065 C. The treatment was same as the normal final cleaning

procedure of the wafering process. The SC-1 treatment was followed by wafer rising and drying.

The contaminated wafers were then followed by the normal 0.13 μm LOGIC CMOS device

manufacturing procedure, and stopped after the SIN layers were etched for failure mode analysis. The idle

duration between wafering final clean and semiconductor manufacturing wafer start was one week.

For defect comparison between the active and non-active regions after the heavy metal contamination

process, MOS capacitors with a capacitor area of 40 2mm were fabricated. The gate oxide was grown on

the Si wafer with LOCOS. A 35nm-thick gate oxide film was then grown, after which WSi and poly Si

were deposited and patterned by dry etching to form gate electrodes.

EDS and SIMS were widely employed for detecting metal contamination. However, EDS, TEM and

HRTEM were used for defects analysis in this investigation.

Even the metallic contamination concentration was less than that which can be detected using current tools. The

duplication experimental was conducted step-by-step using a KLA-Tencor scanning tool on both normal and

contaminated wafers in the IC manufacturing process. Experimental results reveal that both tiny pits and

new-bamboo-like defects were resulted from low-concentration metal contamination in the deep sub-micron IC

process flow.

III. Results and Discussion

Figure 1 illustrates the optical microscopy (OM) pictures, which were the image analysis of wader

edge low yield wafers. The figure indicates that some black shadows with size around 10μm area were

easily detected. The affected areas have irregular shapes and sizes.

Figure 2 reveals that the black shadow contained some new-bamboo-like defects with a diameter of 0.1

μm in size in periphery. The new-bamboo-like defects demonstrate cluster property, which may be

dominated by some attraction force. The SEM picture also reveals that the material on the top of

new-bamboo-like defects was different from bottom.

Figure 3 illustrates the EDS analysis of new-bamboo-like defects, which had with Si and N

characteristic peaks in the spectrums. This finding demonstrates that the new-bamboo-like defects were

caused by SiNx layer residue during the semiconductor manufacturing process.

The new-bamboo-like defects located at the wafer edge were caused by the electro-static charges

having accumulated on the wafer edge area during the final cleaning stage of wafering manufacture. We

believe that the electrostatic charges were accumulated on the parts of cleaning machine such as the lid of

final clean dryer by cycle and cycle; the accumulated charges induced the same quant on the silicon

surface in every run. The wafer edge area induced much more electric charge, since it may be dominated

by radial distribution on the wafer surface, thus attracting more heavy metal contamination

These new-bamboo-like defects were also analyzed using SEM and transmission electron microscopy

(TEM) as indicated in Fig. 4. This picture of Fig-4 (a) indicates that non-OD area has many needle-like or

new-bamboo-like defects with a sharp tips at the stage of silicon dry etching. Figure 4 (b) displays an

enlarged version of the image in Fig. 4 (a) created by TEM, which reveals that the new-bamboo-like

defects have a triangle shape architecture grown on silicon substrate; this defect had a size of about 0.18μ

m at the bottom and about 0.025μm on the top. Additionally, some parallel zones in the new-bamboo-like

defects have a gray color, indicating the deposition of oxygen diffusion layers through a small pit during

pad and gate oxide layers deposition as discussed later.

Figure 5 illustrates the mechanism causing the occurrence of new-bamboo-like defects. Figure 5 (a)

displays that the silicon surface had a small pit, and in which a SiN layer would grow during the SiN

deposition stage. The SiN layer would be reduced in the following SIN removal stage. Unfortunately, these

SiN layers residues act as a hard mask to protecting some small areas during the following silicon

dry-etching and over-etching process which are illustrated in Figs. 5 ( b) and (c), respectively.

Additionally, the failed area was examined in full to find out the differences between the OD and

periphery regions. Additionally, TEM was adopted to verify the interface near silicon substrate in the OD

region. Experimental results indicate that some pits were created with diameter of approximately 0.02μm

in size, as illustrated in Fig6. TEM is currently the only tool for detecting such small defects.

This sample was also checked using an EDS tool to determine the content represented by points 1 to 8

in Fig. 7. The EDS analysis demonstrates that oxygen atoms characteristic peaks were observed in points 1,

2, 4a, 4b, 5, 7 and 8. The detected data in points 1, 4a and 6 EDS demonstrate that oxygen atoms appear

near the diffusion path through little pits.

The above used sample was also analyze using AFM to the three-dimension morphology on the top

view of new-bamboo-like defects after removing the SiN layer using wet chemical dip. Figure 8 illustrates

a little with a concave hole of 2μm diameter and 18nm depth. This little pit is not only small in size but

also rough in profile. We believe that any CVD film is easily deposited by conform growth through

diffusion control. However, a residue is difficult to remove by wet chemical dipping owing to the surface

tension issue.

The above sample was also analyzed using high resolution transmission electron microscopy (HRTEM)

to check the lattice point distortion in the area nearby the pits, as illustrated in Fig. 9. HRTEM was adopted

to distinguish between defects located nearby the pits caused by oxide compounds. Figure 9(a) illustrates

the application of HRTEM to check the region # 1, which is near the pits. Figure 9(b) illustrates a

half-lattice point distortion among the oxygen diffusion impacted zone demonstrating that the silicon

crystal lattice contains oxygen atoms.

Such defects always occur beyond 0.13μm generation of semiconductor process flow. The impact yield

is about 10-15 % at reliability testing. The existence of pits exist on a bare silicon surface is interesting

topic. Figure 10 displays the general manufacturing process flow of 0.13um generation step by step. This

process is occurs at the beginning of manufacturing. Meanwhile, a new-bamboo-like defect was found at

step-8 as demonstrated in Fig. 10. The defect was found at step 8 because the new-bamboo-like defects

were found by KLA-Tencor surface scan tool. The new-bamboo-like defects were enlarged at step 8.

A chain reaction occurred when the heavy metal atom (Cu is for example) met with silicon as deplicted

in Fig. 11. This reaction is an activation-energy-free and spontaneous-generation reaction. The above

discussions demonstrate a detailed analysis of the root cause of new-bamboo-like defect. The silicon

substrate is normally dissolved by the contaminating heavy metal atom as illustrated in Fig. 12. The

experiment was the first to reveal evidence of the impact of metal contamination. We believe that this

evidence is important for the future development of semiconductor manufacturing.

Conclusion:

This investigation has proposed a low yield case and failure mode analysis concluding that metal

contamination deposited on silicon surface would create tiny pits during the wafering process.

These tiny pits are less than 0.02μm in size and are located at the wafer edge. All the pits classes

defect existing in the continuous IC process.

These tiny pits could appear as new-bamboo-like defects in non-OD (periphery device) region and

0.02μm pits in OD device region. These two defects will result in device operation failure because of

leakage.

This investigation demonstrates that sub-micrometer (beyond 100nm-generation) manufacturing

process always suffers yield loss at the wafer edge by new-bamboo-like defects due to design rule

limitations.

A chain reaction occurs when a heavy metal atom meets silicon. This reaction is an

activation-energy-free (spontaneous) reaction, nd continues cycle by cycle unless the heavy metal

concentration is below the critical level.

The tiny pits degrade the gate-oxide integrity (GOI) when the oxide thickness is too thin. In

particular metal contamination control dominates in deep submicron (less than 100nm) semiconductor

process and becomes a major issue in device reliability.

Acknowledgement

The authors would like to thank the National Ministry of Education of the Republic of China, Taiwan,

for financially supporting this research under Contract No. NME 95 -002. Professor S.H. Chen is

appreciated for his valuable discussions. Advanced Semiconductor Engineering, Inc. Taiwan is also

commend for use of their facilities.

References

1) H. G.. Parks, R. D. Schrimpf, B. Craigin, Ronald, and P. Resnick: IEEE Transactions on emiconductor

Manufacturing, 7 (1994) 249.

2) S. M. Sze: Physics of Semiconductor Devices. New York Wiley. (1981) .21, 35-38.

3) M. Itoh, Y. T. Jinbo, H. Akimori, T. Futase, and T. Saeki: IEEE Transactions on emiconductor

Manufacturing, 13 (2000) 300.

4) R. Kasi, and M. Liehr: J. Vac. Sci. Technol. A., 10 (1992) 795..

5) T. Ogata, C. Ban, A. Ueyama, S. Muranaka, T. Hayashi, K. Kobayashi, J. Kobayashi, H. Kurokawa, Y.

Ohno, and M. Hirayama: Jpn. J. Appl. Phys., 37 (1998) 2468.

7) H. G.. Parks, R. D. Schrimpf., B. Craigin, R. Jones, and P. Resnick,: IEEE Transactions on

Semiconductor Manufacturing, 7 (1994) 249.

8) J. D. McBrayer, R. M. Swanson, and T. W. Sigmon, : J. Electrochem. Soc., 133 (1986) 1242.

9) J. W. Y. Teo, H. W. Lim, Y. Jin, J. H. Huang, W. C. Chew, C. K. Leong, F. H. Gn, M. F. Li, and G. Su :

Proceedings of 8th International Symposium on the Physical and Failure Analysis of Integrated

Circuits (IPFA 2001, Singapore),. (2001) 216-219.

Figure Captions

Fig. 1 Optical Microscopy (O. M.) analysis for wafer-edge new-bamboo-like flaws.

Fig. 2 SEM top view analysis for wafer edge new-bamboo-like flaws.

Fig. 3 EDS analysis to verify the new-bamboo-like flaws.

Fig.4 (a) SEM analysis for new-bamboo-like defects, (b) the TEM image analysis for new-bamboo-like

flaws.

Fig. 5. (a)-(c) Mechanism for occurrence of new-bamboo-like defects during process.

Fig. 6. (a) Aalysis of TEM image (a) in active region, (b) near pits.

Fig. 7. Some EDS results which are same area as the checked point of Fig.6 (a).

Fig. 8. (a) AFM image for active region pit defects, (b) cross-section profile analysis as 6(a).

Fig. 9. (a) HRTEM analysis of active region pit-like flaw, (b) HR-TEM crystallizes lattice point analysis at

region #1.

Fig. 10. Deep submicron manufacturing process flow.

Fig. 11. Chain reaction occurred between Cu and Si

Fig. 12. Silicon substrate will be dissolved by contaminated metal.

Fig. 1

P. Y. Chen et al

20 um20 um

Fig. 2

P. Y. Chen et al

(a) (b)

(c)

0.2 um

(a) (b)

(c)

(a) (b)

(c)

0.2 um

Active deviceregion Periphery region

(a) (b)

(c)

0.2 um

(a) (b)

(c)

(a) (b)

(c)

0.2 um

Active deviceregion Periphery region

Fig. 3

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OO

Fig. 4

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(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

OD-area

Non OD-area

(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

OD device region

Non OD (periphery) region-

(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

OD-area

Non OD-area

(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

(a)

(b)

0. 10 um

0.025um

SINresidue

Diffusion

oxygen

OD device region

Non OD (periphery) region-

Fig. 5

P. Y. Chen et al

SIN residue

Si etching

Si over

etching

(a)

(b)

(c)

SIN residue

Si etching

Si over

etching

(a)

(b)

(c)

Fig. 6

P. Y. Chen et al

S iS iS i

0.1 um

SIN

Pad Oxidation

0.1 um

200 nm

(a)

(b)Pad Oxidation

6

5

4b4a

8731

2

0.1 um

SIN

Pad Oxidation

0.1 um

200 nm

(a)

(b)Pad Oxidation

6

5

4b4a

8731

2

Fig. 7

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Fig. 8

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(a)

(b)

Length (um)

Prof

ile(n

m)

(a)

(b)

Length (um)

(a)

(b)

(a)

(b)

Length (um)

Prof

ile(n

m)

Fig. 9

P. Y. Chen et al

(a)

(b)

Region #1

Region #1

(a)

(b)

(a)

(b)

Region #1

Region #1

tiny pit

tiny pit

1. Waferwith

tiny pit

tiny pit

1. Waferwith

tiny pit

tiny pit

1. Waferwith

Fig. 10

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.

Fig. 11

P. Y. Chen et al

“”in d ica te sO x id a tio n b y H 2O 2e .g .C u 0 C u 1 +

S i0 S i1 +

“(”in d ic a tese - tran s fe rfro m S i to C ue .g .C u 1 + + S i1 +

(C u 0 + S i2 +

C u 0+ S i0

C u 1 ++ S i1 +C u 1 + + S i3 +

C u 0+ S i2 +

C u 0+ S i4 +

S i4 +

C u 0

D is s o lu tio n

“”in d ica te sO x id a tio n b y H 2O 2e .g .C u 0 C u 1 +

S i0 S i1 +

“(”in d ic a tese - tran s fe rfro m S i to C ue .g .C u 1 + + S i1 +

(C u 0 + S i2 +

C u 0+ S i0C u 0+ S i0

C u 1 ++ S i1 +C u 1 ++ S i1 +C u 1 + + S i3 +C u 1 + + S i3 +

C u 0+ S i2 +C u 0+ S i2 +

C u 0+ S i4 +C u 0+ S i4 +

S i4 +S i4 +

C u 0C u 0

D is s o lu tio n

Fig. 12

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Si

Si

Cu

SiSi

Of Cu

Si

Cu

Si

Cu

Si

Cu

Pitting

Mirco-contamination

Si

Si

Cu

SiSi

Of Cu

Si

Cu

Si

Cu

Si

Cu

Pitting

Mirco-contamination