semiconductor thermal design

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RPS • 2010 April Corporate Research & Development Packaging Technology Semiconductor Device Thermal Characterization and System Design Roger Stout, PE Research Scientist Corporate R&D: Technology Development <[email protected]>

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Page 1: Semiconductor Thermal Design

RPS • 2010 April Corporate Research & Development Packaging Technology

Semiconductor Device Thermal

Characterization and System Design

Roger Stout, PE

Research Scientist

Corporate R&D: Technology Development

<[email protected]>

Page 2: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology1

Course outline

• Part I: Characterization (75 minutes)– Why Everything you Thought You Knew (about

device thermal characteristics) is Wrong

– Characterization Techniques

– Miscellaneous Measurement Techniques

• Part II: Linear Superposition (120 minutes)– Basic Theory

– The Reciprocity Theorem

– A Detailed Example and its Implications

– Building a System Model

– Time Varying Heat Sources

• Part III: Thermal Runaway (45 minutes)– Theory

– Datasheet example

– High-Temperature Reverse Bias “qual” example

Page 3: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology2

Characterization

Part I

Page 4: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology3

Can this device handle 2 W?

Page 5: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology4

Why is ON’s SOT-23 thermal number

so much worse than the other guy’s?

• ON– SOT-23 package

– 60x60 die

– Solder D/A

– Copper leadframe

– Min-pad board

– Still air

• some other guy– SOT-23 package

– 20x20 die

– Epoxy D/A

– Alloy 42 leadframe

– 1” x 2oz spreader

– Big fan

Page 6: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology5

Fundamental ideas

• Heat flows from higher temperature to lower temperature

• The bigger the temperature difference, the more heat that flows

• Three modes of heat transfer

– Conduction (solids, fluids with no motion)

– Convection (fluids in motion)

– Radiation (it just happens)

Page 7: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology6

Thermal-electrical analogy

temperature <=> voltage

power <=> current

Δtemp/power <=> resistance

energy/degree <=> capacitance

Page 8: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology7

“Junction” temperature?

Historically, for discrete devices, the “junction” was literally the

essential “pn” junction of the device. This is still true for basic

rectifiers, bipolar transistors, and many other devices.

More generally, however, by “junction” these days we mean

the hottest place in the device, which will be somewhere on

the silicon (2nd Law of Thermodynamics).

This gets to be somewhat tricky to identify as we move to

complex devices where different parts of the silicon do

different jobs at different times.

Page 9: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology8

adJAJ TPT

What’s wrong with theta-JA?

d

aJJA

P

TT

d

tabJJtab

P

TT

tabdJtabJ TPT

2

Page 10: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology9

Theta-JA vs. copper area

Page 11: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology10

Typical thermal test board types

Min-pad board

Minimum metal area to attach

device (plus traces to get

signals and power in and out)

1-inch-pad board

Device at center of 1”x1”

metal area (typically 1-oz Cu);

divided into sections based on

lead count

Page 12: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology11

Theta ( ) vs.. Psi ( )

• JEDEC <http://www.jedec.org/> terminology

– Z JX , R JA older terms ref JESD23-3, 23-4

– JA ref JESD 51, 51-1

– JMA ref JESD 51-6

– JT, TA ref JESD 51-2

– JB, BA ref JESD 51-6, 51-8

– R JB ref JESD 51-8

– Great overview, all terms: JESD 51-12

Page 13: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology12

“Theta” (Greek letter

Ty

We know actual heat flowing along path of interest

true “thermal resistance”

path

yxxy

q

TT

Tx

Page 14: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology13

“Psi” (Greek letter

Tx

Ty??

We don’t know actual heat flowing along path of interest

… all we

know is total

heat input

total

yxxy

q

TT

a reference number only

Page 15: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology14

Facts and fallacies

• Basic idea:

– “thermal resistance” is an intrinsic property of a package

• Flaws in idea:

– there is no isothermal “surface”, so you can’t define a

“case” temperature

• Plastic body (especially) has big gradients

– different leads are at different temperatures

– multiple, parallel thermal paths out of package

Page 16: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology15

An example of a device with two

different “Max Power” ratings

• Suppose a datasheet says:

– Tjmax = 150°C

– JA = 100°C/W

– Pd = 1.25W (Tamb=25°C)

• But it also says:

– JL = 25°C/W

– Pd = 3.0W (TL=75°C)

Where’s the “inconsistency”?

15012525

25.1*10025

1507575

3*2575

Page 17: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology16

Where’s the inconsistency?

What’s TL?

25°C/W

( JL)

100°C/W

( JA)

TJ =150°C

TA =25°C

Not 75°C !!

(try about 119°C)

…¾ of the way from

ambient to Tj

Page 18: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology17

Back in the good old days ...

metal can --

fair approximation of

“isothermal” surface

axial leaded device --

only two leads, heat

path fairly well defined

Page 19: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology18

Which lead? Where on case?

Page 20: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology19

silicon

die attach

wire/clip

flag/leadframe

case

circuit board

convection

60%10%

20%

10%

“Archetypal” package

Page 21: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology20

Then we change things …

optional heatsink

mold compound/

case

flag/leadframe

application board

silicon

die attach

wire/clip

optional heatsink

optional “case”

application board

silicon

die attach

optional underfill

pads/balls

add an external heatsink … flip the die over …

40%

20%

60%

20%20%40%

Page 22: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology21

A bare “flip chip”

application board

silicon

underfill

pads/balls

90%

10%

Page 23: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology22

OH of GPM 1

C25

W50

C/W2.1

2

c

d

tabJ

T

P

air still

C25

W5.1

C/W8.0

c

d

tabJ

T

P

Same ref, different values

Page 24: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology23

21

43

3

RR

RR1

R

0

10

20

30

40

50

60

1 10 100 1000board

rstnc. [C/W]

psi-JC - var brd only

psi-JC - var airflow

43

21

1

RR

RR1

R

4321 RR

1

RR

1

1

Even when it’s constant, it’s not!

0

100

200

300

400

500

600

700

800

900

1000

1 10 100 1000board

rstnc. [C/W]

thetaJA - var brd only

thetaJA - var airflow

0

5

10

15

20

25

1 10 100 1000board

rstnc. [C/W]

psi-JL - var brd only

psi-JL - var airflow

theta-JA

psi-JT

psi-JL

R1 (path down

to board)

constant at 20

R2 (board

resistance) vary

from 1 to 1000

R3 (path through

case top)

constant at 80

R4 (case to air path

resistance) constant

at 500, or 20x R2

TCTL

Tj

Tamb

total

LJJL

Q

TTtotal

CJJT

Q

TT

total

ambJJA

Q

TT

package

environment

Page 25: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology24

Ta

Tj

JA

Page 26: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology25

• Therefore, different application environments will

see different “package resistance”

• “Package resistance” isn’t fixed:

– multiple heat paths exiting package

– boundary conditions dictate heat flow

• Heat sinks

• Neighboring devices/power dissipation

• Single vs.. double-sided boards

• Local convection vs.. board-edge cooling

• Multiple layers/power/ground planes

Fallacies recap:

Page 27: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology26

Characterization Techniques

Characterization Techniques

Typical TSP behavior

Vf

Vf

T

125°C

25°C

0.7 V0.5 V

sense

current

calibrate forward voltage at controlled,

small (say 1mA) sense current

Page 28: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology27

DUT

true const. current supply

(1 mA typical)

DUT

10K

If Vf­0.7V, then

I­1mA

10.7V

How to measure Tj

OR

approximate const. current supply

Page 29: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology28

DUT

10Kheatingpowersupply

10.7V10.7V

DUT

10Kheatingpowersupply

10.7V

How to heat

OR

sample current is off

while heating current onsample current is always on

Page 30: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology29

0.90 W

0.70 W

0.64 W

The importance of 4-wire

measurements

Power

supply

+(1.00 V)

-(0 V)

1 A

0.18 V0.82 V

0.95 V0.05 V 0.85 V0.15 V

Output = 1 W

Page 31: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology30

Which raises an interesting question:

0.3 W

Power

supply

+(1.00 V)

-(0 V)

3 A

0.45 V 0.55 V

0.98 V0.02 V

Output = 3 W

Is this a fair characterization of a low-Rds-on device?

1.3 W 1.3 W

Page 32: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology31

Bipolar transistor

• TSP is Vce at designated

“constant” current

• Heating is through Vce

• Choose a base current that

permits adequate heating

bias supply

TSP=Vcebias resistor

TSP supply

switch

heating supply

10K

Page 33: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology32

Schottky diode

• TSP is forward voltage at “low” current

• Voltages are typically very small (especially as

temperature goes up)

• Highly non-linear, though maybe better as TSP

current increases; because voltage is low, higher

TSP current may be acceptable

• Heating current will be large

Page 34: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology33

MOSFET / TMOS

• Typically, use reverse bias

“back body diode” for both

TSP and for heating

• May need to tie gate to

source (or drain) for

reliable TSP characteristic

TSP=Vsd

TSP supply

switch

heating

supply

10K

+

-

Page 35: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology34

+

MOSFET / TMOS method 2

• If you have fast switches and

stable supplies

• Forward bias everything and use

two different gate voltages

TSP=Vds

TSP supply

close switch to heat

heating

supply

10K

-

+

-

V-gate

for

heating-

V-gate

for

measure

+

close switch to heat

close switch to measure

Page 36: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology35

RF MOS

• They exist to amplify high frequencies (i.e. noise)!

TSP supply

close switch to heat

heating

supply

10K

-

+V-gate

for

heating-

+

close switch to heat

close switch to measure

• Feedback resistors

may keep them in DC

+

-

TSP =

body

diode

TSP

supply

Page 37: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology36

IGBT

• Drain-source channel used for

both TSP and heating

• Find a gate voltage which “turns

on” the drain-source channel

enough for heating purposes

• Use same gate voltage, but

typically low TSP current for

temperature measurementTSP=Vds

gate

voltage

TSP supply

switch

heating supply

10K

Page 38: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology37

Thyristor

• Anode--to-cathode voltage path

used both for TSP and for heating

• typical TSP current probably lower

than “holding” current, so gate

must be turned on for TSP

readings; try tying it to the anode

(even so, we used 20mA to test

SCR2146)

• Hopefully, with anode tied to gate,

enough power can be dissipated to

heat device without exceeding

gate voltage limit

TSP supply

switch10K

heating

supply

TSP=Vac

cathode

anodegate

Page 39: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology38

Logic and analog

• Find any TSP you can

– ESD diodes on inputs or outputs

– Body diodes somewhere

• Heat wherever you can

– High voltage limits on Vcc, Vee, whatever

– Body diodes or output drivers

– Live loads on outputs

• (be very careful how you measure power!)

Page 40: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology39

Heating curve method

vs..

cooling curve method

Page 41: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology40

DUT

10Kheatingpowersupply

10.7V

Quick review:

Basic Tj measurement

DUT

10Kheatingpowersupply

10.7V

first we heat then we measure

Page 42: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology41

Question

• What happens when you switch

from “heat” to “measure”?

Answer: stuff changes

• More specifically, the junction

starts to cool down

Page 43: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology42

Vf

Vf

T

125°C

25°C

.7V.5V

calibrate forward voltage

@ 1mA sense current

pow

er-

off

coolin

g

high-

current

heating

measurements

convert cooling

volts to

temperature

Basic

“heating curve”

transient method vo

lta

ge

cu

rre

nt

1 ma

ste

ad

y s

tate

re

ach

ed

Te

mp

era

ture

Time

pow

er-

off

coolin

g

high-

current

heating

pow

er-

off

coolin

g

high-

current

heating

pow

er-

off

coolin

g

high-

current

heating

measured

temperatures

Page 44: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology43

po

we

r-o

ff c

oo

ling

high-

current

heating

vo

lta

ge

curr

ent

1 ma

Te

mp

era

ture

Time

po

we

r-o

ff c

oo

ling

high-

current

heating

po

we

r-o

ff c

oo

ling

high-

current

heating

pow

er-

off c

oolin

g

high-

current

heating

measured temperatures

Heating curve method #2

Time

Page 45: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology44

Basic

“cooling curve”

transient method

Vf

Vf

T

125°C

25°C

.7V.5V

calibrate forward voltage

@ 1mA sense currentpower-off

cooling

high-

current

heating

vo

lta

ge

cu

rre

nt

1 ma

measurements

heating

period

transient cooling

period (data taken)

ste

ad

y s

tate

rea

ch

ed

Te

mp

era

ture

Time

convert cooling

volts to

temperature

Te

mp

era

ture

Time (from

start of cooling)

subtract cooling curve from

peak temperature to obtain

“heating” curve equivalent

Page 46: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology45

• Heating vs.. cooling

– Physics is symmetric, as long as the material

and system properties are independent of

temperature

Whoa!

… that last step there …

Page 47: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology46

Heating vs.. cooling symmetry

(all the same

curves, flipped

vertically)

flag

lead

back of board

edge of board

Start of (constant)

power offjunction

Start of constant

power input

(“step heating”)

Page 48: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology47

• For a theoretically valid cooling curve,

you must begin at true thermal

equilibrium (not uniform temperature,

but steady state)

• So whatever your JA, max power is

limited to:

JA

j TTpower

ambientmax

Page 49: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology48

By the way …

Steady-state vs.. transient ?

• Since you must have the device at steady state in

order to make a full transient cooling-curve

measurement, steady-state JA is a freebie.

(given that you account for the slight cooling

which took place before your first good

measurement occurred)

Page 50: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology49

Effect of power on heating curve

< steady-state max power

Tj-max

Tamb

steady-state max power

2x steady-state power6x steady-

state power

24x steady-

state power3x steady-

state power

time

jun

ctio

n te

mp

era

ture

Page 51: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology50

Some initial uncertainty

heating period transient cooling period (data taken)

ste

ad

y s

tate

re

ach

ed

Te

mp

era

ture

Time

power-off

cooling

high-current

heating

but once we’re past

the “uncertain” range,

all the rest of the

points are “good”

a few initial points

may be uncertain

Page 52: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology51

Heating vs.. cooling tradeoffs

starting

temperature

heating

power

temperature of

fastest data

error

control

HEATING

ambient

limited by

tester

closer to

ambient

all points

similar error

COOLING

?

limited to

steady-state

closer to

Tj-max

error limited to

first few points

Page 53: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology52

• Varying the air speed is mainly varying the heat

loss from the test board surface area, not from

the package itself

• You just keep re-measuring your board’s

characteristics

Still air vs.. moving air

Page 54: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology53

total system thermal resistance

0

10

20

30

40

50

60

70

80

90

100

0.1 1 10

air speed [m/s]

theta

-JA

[C

/W]

little package

big package

medium-

sized

package

board resistance

package resistance

Page 55: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology54

• Min-pad board

• 1” heat spreader board

• You’re mainly characterizing how copper area

affects every package and board, not how a

particular package depends on copper area

Different boards

Page 56: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology55

1" pad vs min-pad

0

50

100

150

200

250

300

350

0 100 200 300 400 500 600 700

min pad thetaJA (C/W)

1" p

ad

th

eta

JA

(C

/W)

overall linear fit is:

1" value = [0.51*(min-pad value) - 7]

SMBSMA & Pow ermite

Micro 8

TSOP-6(AL42)SOT-23

SOD-123

TSOP-6

SOD-123

SOT-23

SOD-323

SOT-23

SOD-123

Top Can

D2pak & TO220

Top Can

Dpak

SO-8SOT-223

TSOP-6SO-8

SMC

Source:

Un-derated thermal data

from old PPD database

Roger Stout 5/25/2000

Page 57: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology56

Standard coldplate testing

• “infinite” heatsink (that really isn’t) for measuring theta-

JC on high-power devices

• If both power and coldplate temperature are

independently controlled, “two parameter” compact

models may be created

Page 58: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology57

Standard coldplate testing

• Detailed design and placement of “case” TC can

have significant effect on measured value

Page 59: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology58

2-parameter data reduction

heat in, Q

R1

R2

T1

Tj

T2

21 QQQ

)()( 2

2

1

1

11TT

RTT

RQ jj

bxmxmy 2211

)( 11

1

1

1TTx

Rm j

0b

)( 22

2

2

1TTx

Rm j

where:

heat up, Q1

heat down, Q2

This has the form of a two-variable linear equation:

Page 60: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology59

A “single coldplate” test

Rja

Rjc

Ta

Tj

Tc

ambient

coldplate -20.00

0.00

20.00

40.00

60.00

80.00

100.00

120.00

-20.00 0.00 20.00 40.00 60.00 80.00 100.00

Tja (¡C)

Tjc

(¡C

)

Incr easing Power, Chuck H eld

Cold

No P ower, Chuck T emper atureIncr eased

Tc coldplate

TjTa

Page 61: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology60

A “single coldplate” test,

package down

-20.00

0.00

20.00

40.00

60.00

80.00

100.00

120.00

-10.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00

Tjb (¡C)

Tjc

(¡C

)

Incr easing Power, Chuck H eld

Cold

No P ower, Chuck T emper atureIncr eased

Rjb

Rjc

Tb

Tj

Tc

ambient

coldplate

Rba

Ta

Tj TbTa

coldplateTc

Page 62: Semiconductor Thermal Design

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Miscellaneous Measurement Topics

• Thermocouple Theory 101

• Infrared Theory 202

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Thermocouple Theory 101

Page 64: Semiconductor Thermal Design

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Thermocouple Theory

region “A” - a 1cc box

around the junction

region “C” – 10cm of TC wire

length passing from inside of

chamber door to outside of

chamber door

TC scanner

region “D” – 100cm of TC wire

length from outside of chamber

to TC measuring instrument

perfectly uniform

temperature

chamber at 100°C

A

TC junction

region “B” - 20cm of wire length

between the junction and the door

of the temperature chamber

perfectly uniform ambient

temperature of 25°C

BC

D

Page 65: Semiconductor Thermal Design

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Thermocouple Theory

• Question #1:

– where is the temperature actually being “sensed”? or to put it another way, which region of the four defined above (A, B, C, D), is the one that matters, as far as generating the EMF being measured by the TC scanner? Why?

perfectly uniform

temperature

chamber at 100°C

A

TC junction

BC

D

perfectly uniform

ambient at 25°C

The emf is generated

where there is a

temperature gradient

Page 66: Semiconductor Thermal Design

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Thermocouple Theory

• Question #2:

– if the purpose of the TC scanner is to measure an EMF, theoretically how much current has to flow in the wire to make the correct measurement?

None. Ideally, a galvanometer circuit balances

the EMF at the scanner until no current flows.

Corollary: wire size, and therefore resistance, may affect

how long it takes the galvanometer circuit to stabilize.

Page 67: Semiconductor Thermal Design

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Thermocouple Theory

• Question #3:

– what do the two wires in the TC actually do, and why

do they have to be made of different materials?

Different materials have different Seebeck

coefficients, i.e., V/°C. So if you have two

different materials, the same temperature

gradient appearing in along both wires will

result in two different EMF’s.

100°C

25°C

25°C100°C

ΔV=0.0025V

ΔV=0.0037V

Page 68: Semiconductor Thermal Design

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ΔV=0.0025V

Thermocouple Theory

• Question #4:

– what does the “junction” in a TC actually do?

Provides the common electrical point that

relates the EMF’s in the two wires to

each other, hence the net difference

appears at the “open” end of the circuit.

The junction DOES NOT “measure”

the temperature; the wires do!

100°C

25°C

25°C

ΔV=0.0037V

Net

ΔV=0.0012V

Corollary: if the junction itself is isothermal,

it can be made of any material whatsoever!

Page 69: Semiconductor Thermal Design

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Thermocouple Theory

• Question #5:

– if you really wanted to “calibrate” this thermocouple, where would you need to apply the test conditions?

A

TC junction

BC

D

Everywhere along

its length!

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Infrared Theory 202

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Infrared Theory

A opaque surface radiates thermal

energy in proportion to its absolute

temperature (to the fourth power),

and some other things

4ATq

Page 72: Semiconductor Thermal Design

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Infrared Theory

It’s also absorbing infrared energy from

everything else around it (since

everything else has a temperature and

is therefore emitting)

It turns out that the

“absorptivity” equals

the “emissivity.”

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Infrared Theory

There is thus a net energy transfer which, in

the simplest situations, may be described by:

)( 44

enclobjobjobj TTAq

(typically applies to a small,

isothermal object in a big,

isothermal enclosure)

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Infrared Theory

But it quickly gets more complicated

when there are multiple objects (or

temperatures) hanging around.

• Each object has a “view factor” of

every other object

• Each object has its own emissivity

(usually NOT unity)

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Infrared Theory

The “emissivity,” , is also related

to the “reflectivity,” , as follows:

1

So the worse something emits, the

better it reflects, and vice-versa.

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Infrared Theory

In other words, unless you’re looking at a

perfect emitter (aka a “blackbody”), you

don’t simply see less radiation than you

would for a blackbody, you see some of

the radiation of what’s behind you!

Page 77: Semiconductor Thermal Design

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Infrared Theory

In even the simplest real-life situation,

you usually have four “objects,” and their

associated temperatures, to consider:

• The test specimen (130°C)

• The surrounding room (25°C)

• You (33°C)

• The detector (-195°C)

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Infrared Theory

(you)

(the detector

itself)

The “target”

(the room)

(the room)

Page 79: Semiconductor Thermal Design

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Infrared Theory

So if you’re looking at a shiny, low emissivity

specimen, you’ll see a combination of these

four temperatures (that is, the radiation

representing these four temperatures) all

bouncing into the detector!

Depending on the angles involved,

therefore, it is quite possible to see vastly

higher temperatures than are really there, or

vastly lower temperatures are really there.

Page 80: Semiconductor Thermal Design

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Hot water loop Footprints

Page 81: Semiconductor Thermal Design

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Direct view In mirror

Page 82: Semiconductor Thermal Design

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Reflection Emissivity

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View at 10 am View at 10 pm

Page 84: Semiconductor Thermal Design

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Page 85: Semiconductor Thermal Design

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Infrared Theory

Moral:

For accurate temperature measurements, you

must account for the emissivity of the target,

and you must control the background!

Page 86: Semiconductor Thermal Design

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Infrared Theory

IR camera

isothermal

enclosure, high

emissivity, opaque

to infrared

DUT

Here’s one way to approach it:

Page 87: Semiconductor Thermal Design

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Infrared Theory

411 TaII back

422 TaII back

41

42

12

TT

IIa

41

42

24

114

2

TT

ITITIback

4TaII back

41

a

IIT back

41

12

2

4

11

4

2 )()(II

IITIITT

Two reference scans

Solve for the unknowns

Governing equation

Solve for Temperature

In terms of the reference scan quantities:

Page 88: Semiconductor Thermal Design

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Linear Superposition

Part II

Page 89: Semiconductor Thermal Design

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• The total response of a point within the

system, to excitations at all points of

the system, is the sum of the individual

responses to each excitation taken

independently.

Linear superposition

– what is it?

nsource2source1sourcecomposite TTTT

Page 90: Semiconductor Thermal Design

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DCBA q21q3q2T .

• The system must be “linear” – in brief, all

individual responses must be proportional to

all individual excitations.

Linear superposition

– when does it apply?

DACABAAnet TTTT

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Linear superposition doesn’t

apply if the system isn’t linear.

2211 )()( ,, qqTbqqTaT

2

2

1

1

nnqbqaT

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Linear superposition

– how do you use it?

Tj3 Tj2

Tj1Tj4

Tj5Tj6

Tref1

Tref5

Tref3

TB

Tamb

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Linear superposition

– when would you use it?

When you have multiple heat sources

(that is, all the time!)

Page 94: Semiconductor Thermal Design

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a

nJnAnn

nAJ

nAJ

jn

j

j

T

q

q

q

T

T

T

2

1

21

2221

1121

2

1

theta matrix assembled

from simplified subsystems

junction

temperature

vector

power

input

vector

board

interactions

JT q aT

self-heating terms

JAθ

Page 95: Semiconductor Thermal Design

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a

nBAnJBnnn

nBAJB

nBAJB

jn

j

j

T

q

q

q

T

T

T

2

1

21

22221

11211

2

1

theta matrix assembled

from simplified subsystems

junction

temperature

vector

power

input

vector

device

resistanceboard

resistance

Page 96: Semiconductor Thermal Design

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visualizing theta and psi

(idle heat source “x”)

thermal ground

measurements

here are s

xAy A

AJ1

BJ1

BA

measurements

here are s

(idle heat source “y”)

heat in here

Page 97: Semiconductor Thermal Design

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3

2

1

321

312111

321

23212

13121

1

2

1

q

q

q

T

T

T

T

T

BBB

LLL

xxx

JA

JA

BA

AL

xA

j

j

one column for

each heat source

junction

temperature

vector

power input

vector

one row

for each

heat

source

one row for each temperature

location of interest

theta matrix doesn’t have to be square

(why is this

and not ?)

Page 98: Semiconductor Thermal Design

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Electrical reciprocity

5 V

+

-

? V

+

-0.3 V

-

+

2 A0.3 V-

+

I

V-

+

Page 99: Semiconductor Thermal Design

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Thermal reciprocity

heat input here

same

response

hereresponse

here

Page 100: Semiconductor Thermal Design

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Another thermal reciprocity example

heat input here

same

response

here

response

here

(s)

(s)

(r)

(r)

Page 101: Semiconductor Thermal Design

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When does reciprocity NOT Apply?

A

D

C

airflow

Heat in at “A” will raise temperature

of “C” more than heat in at “C” will

raise temperature of “A”

• Upwind and downwind in forced-convection

dominated applications

“B” and “D” may

still be roughly

reciprocal

B

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(square part of) matrix is symmetric

75 65 55 60 22 10

65 71 60 55 25 11

55 60 65 61 21 15

60 55 61 73 18 11

22 25 21 18 125 14

10 11 15 11 14 180

73 65 55 59 22 10

55 60 63 61 21 15

20 24 14 19 95 15

65 63 62 63 21 12

J1

J2

J3

J4

J5

J6

R1

R3

R5

B

rows are the

response

locations

columns are the heat sources

Page 103: Semiconductor Thermal Design

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Superposition example

Tj3=85.5 Tj2=96.5

Tj1=107.5Tj4=91.0

Tj5=49.2Tj6=36.0

Tref1=105.3

Tref5=47.0

Tref3=85.5

TB=96.5

Tamb=25

Device 1

heated, 1.1 W

Page 104: Semiconductor Thermal Design

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Reduce the data

j1A 75

j2A 65

j3A 55

j4A 60

j5A 22

j6A 10

r1A 73

r3A 55

r5A 20

BA 65

7511

255107

q

TT

1

amb1jA1j

.

.

6511

25596

q

TT

1

amb2jA2j

.

.

6511

25596

q

TT

1

ambBBA

.

.

Page 105: Semiconductor Thermal Design

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Device 2 heated, 1.2 W

Tj3=97.0 Tj2=110.2

Tj1=103.0Tj4=91.0

Tj5=55.0Tj6=38.2

Tref1=103.0

Tref5=53.8

Tref3=97.0

TB=100.6

Tamb=25

j1A 65

j2A 71

j3A 60

j4A 55

j5A 25

j6A 11

r1A 65

r3A 60

r5A 24

BA 63

Page 106: Semiconductor Thermal Design

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Device 3 heated, 1.3 W

Tj3=109.5 Tj2=103.0

Tj1=96.5Tj4=104.3

Tj5=52.3Tj6=44.5

Tref1=96.5

Tref5=43.2

Tref3=106.9

TB=105.6

Tamb=25j1A 55

j2A 60

j3A 65

j4A 61

j5A 21

j6A 15

r1A 55

r3A 63

r5A 14

BA 62

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Device 4 heated, 1.1 W

Tj3=92.1 Tj2=85.5

Tj1=91.0Tj4=105.3

Tj5=44.8Tj6=37.1

Tref1=89.9

Tref5=45.9

Tref3=92.1

TB=94.3

Tamb=25j1A 60

j2A 55

j3A 61

j4A 73

j5A 18

j6A 11

r1A 59

r3A 61

r5A 19

BA 63

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Device 5 heated, 0.7 W

Tj3=39.7 Tj2=42.5

Tj1=40.4Tj4=37.6

Tj5=112.5Tj6=34.8

Tref1=40.4

Tref5=91.5

Tref3=39.7

TB=39.7

Tamb=25j1A 22

j2A 25

j3A 21

j4A 18

j5A 125

j6A 14

r1A 22

r3A 21

r5A 95

BA 21

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Device 6 heated, 0.5 W

Tj3=32.5 Tj2=30.5

Tj1=30.0Tj4=30.5

Tj5=32.0Tj6=115.0

Tref1=30.0

Tref5=32.5

Tref3=32.5

TB=31.0

Tamb=25j1A 10

j2A 11

j3A 15

j4A 11

j5A 14

j6A 180

r1A 10

r3A 15

r5A 15

BA 12

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Collect the / values

75 65 55 60 22 10

65 71 60 55 25 11

55 60 65 61 21 15

60 55 61 73 18 11

22 25 21 18 125 14

10 11 15 11 14 180

73 65 55 59 22 10

55 60 63 61 21 15

20 24 14 19 95 15

65 63 62 63 21 12

J1

J2

J3

J4

J5

J6

R1

R3

R5

B

rows are the

response

locations

columns are the heat sources

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Now apply actual power

Tj3=134.9 Tj2=140.1

Tj1=140.0Tj4=135.8

Tj5=124.7Tj6=139.1

Tref1=138.8

Tref5=106.3

Tref3=134.1

TB=139.1

Tamb=25

Qj1 .4

Q j2 .4

Q j3 .4

Q j4 .4

Q j5 .5

Q j6 .2

Actual power

in application

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Compute some effective / values

Take Tj1, for instance. Remember when it was

heated all alone, we calculated its self-heating

theta-JA like this:

7511

255107

q

TT

1

amb1jA1j

.

.

28840

25140

q

TT

1

amb1jA1j

.

Now let’s see:

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And that’s not just a single aberration!

Self heating

j1A 288 vs. 75

j2A 288 vs. 71

j3A 274 vs. 65

j4A 277 vs. 73

j5A 199 vs. 125

j6A 309 vs. 180

Junction to Board

j1-B 2.2 vs. 10.0

j2-B 2.5 vs. 8.0

j3-B -10.5 vs. 3.0

j4-B -8.3 vs. 10.0

Junction to Reference

j1-R1 3.0 vs. 2.0

j3-R3 2.0 vs. 2.0

j5-R5 36.8 vs. 30.03.8x

4.1x

4.2x

3.8x

1.6x

1.7x

1.5x

1.0x

1.2x

0.2x

0.3x

-3.5x

-0.8x

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Is the moral clear?

• You simply cannot use published theta-JA values for

devices in your real system, even if those values are

perfectly accurate and correct as reported on the

datasheet and you know the exact specifications of

the test conditions.

• Not unless your actual application is identical to the

manufacturer’s test board – and uses just that one

device all by itself.

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ann12121A1J1j TqqqT

a

n

2

1

JnAn2n1

n2A2J12

n112A1J

jn

2j

1j

T

q

q

q

T

T

T

So is it really this bad?

Only sort-of. Let’s revisit the math for one device …

a

n

2

nn11A1J1j TqqT

00

“effective”

ambient

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a1A1J1j TqT

power, q

Tajunction temperature , TJ1

Ta’junction temperature , TJ1

a1A1J

a

n

2

nn11A1J1j

Tq

TqqT

Ta

shift in effective

ambient

Device in a

system

still the

same slope

1

J1A

1

J1A

Isolated

device

A graphical view

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What about that “system” theta

we saw earlier that was so

different?

junction temperature

power

Ta’

1

J1A

Ta

the “system”

theta-JA

the isolated-device

theta-JAn

2

nn1 q

1

J1A

device #1

power/temperature

perturbations will

fall on this line

NOT this oneq1

TJ1

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when Q1 is

zero, both of

these will be

zero

a

n

2i

ii11j1aj1 TQQT )(

How does effective ambient relate to board temperature?

temperature

rise, board to J1

“system” slope for

isolated device

temperature rise,

ambient to board

a1a1B1B1j TQQ

aa1BB1j TTT

a1B1aj1B TQ)(

if any of these are non-zero,

will be higher thanaT aT

when Q1 is

not zero, both

of these will

be non-zero

effective

ambient

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• The device and system are equally

important to get right

Predicting the temperature

of high power components

• The system is probably more

important than the device

Predicting the temperature

of low power components

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Using the previous board example …

75 65 55 60 22 10

65 71 60 55 25 11

55 60 65 61 21 15

60 55 61 73 18 11

22 25 21 18 125 14

10 11 15 11 14 180

73 65 55 59 22 10

55 60 63 61 21 15

20 24 14 19 95 15

65 63 62 63 21 12

J1

J2

J3

J4

J5

J6

R1

R3

R5

B

Qj1 0.5

Q j2 0.5

Q j3 0.5

Q j4 0.5

Q j5 0.2

Q j6 0.02

power

vector

theta array

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Observe the relative contributions

= (75 x 0.5) +

(65 x 0.5) + (55 x 0.5) + (60 x 0.5) + (22 x 0.2) + (10 x 0.02)

+ 25

For junction 1 (a high power component) we have:

= 37.5 + 32.5 + 27.5 + 30 + 4.4 + 0.2 + 25

= 37.5 + 94.6 + 25

the device itself …

the other devices …

Page 122: Semiconductor Thermal Design

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Graphically, a high-power device looks like this:

junction temperature

power

1

75 C/W

25 C

q1=0.5 W

TJ1

=94.6 C =37.5 Cn

2

nn1 q

note the “embedded”

theta-JA looks like

264 C/W

264 C/W

increasing

power

decreasing

power

)( 1J1Aqθ

1

157 C

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Relative contributions to TJ6

= (10 x 0.5) + (11 x 0.5) + (15 x 0.5) + (11 x 0.5) + (14 x 0.2)

+ (180 x 0.02)

+ 25

= 5.0 + 5.5 + 7.5 + 5.5 + 2.8 + 3.6 + 25

= 26.3 + 3.6 + 25

the device itself …

the other devices …

Page 124: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology123

Graphically, low-power device #6 looks like this:

junction

temperature

power

1

180 C/W

25 C

q6=0.02 W

TJ6

=26.3 C

=3.6 C

and just in case you were

wondering, the “embedded”

theta-JA looks like 1495 C/W !

54 C

Page 125: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology124

How to harness this math in Excel®

Controlling the matrix

Page 126: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology125

3x3 theta matrix, 3x1 power vector Excel® math

theta

matrix

power vector

Matrix MULTiply

{=array formula notation}

array reference to theta matrix

array reference to power vector

obtained by using Ctrl-Shift-Enter rather than ordinary Enter

multi-cell placement of array formula

Page 127: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology126

7x3 theta matrix, 3x1 power vector Excel® math

array formula now occupies 7 cells

theta matrix is no longer square –

# of columns still must equal

# of rows of power vector

don’t forget to use

Ctrl-Shift-Enter

to invoke array formula notation

Page 128: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology127

7x3 theta matrix, 3x2 power vector Excel® math

the single MMULT array formula now occupies 7 rows and 2 columns (one column for each

independent power scenario result)

power “vector” is now a 3x2 array –

each column is a different power

scenario, yet both are still processed

using a single array (MMULT) formula

Page 129: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology128

Temperature direct contributions and totals

0

20

40

60

80

100

120

J1 J2 J3 J4 J5 J6 R1 R3 R5 B

result location

tem

pe

ratu

re r

ise

[C

], e

ach

so

urc

e

J1 at 0.4 W J2 at 0.4 W J3 at 0.4 W

J4 at 0.4 W J5 at 0.5 W J6 at 0.2 W

0

20

40

60

80

100

120

J1 J2 J3 J4 J5 J6 R1 R3 R5 B

result location

tem

pe

ratu

re r

ise

[C

] su

m o

f so

urc

es

J1 at 0.4 W J2 at 0.4 W J3 at 0.4 W

J4 at 0.4 W J5 at 0.5 W J6 at 0.2 W

Page 130: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology129

Normalized responses at each

location due to each source

0

20

40

60

80

100

120

140

160

180

200

J1 J2 J3 J4 J5 J6 R1 R3 R5 B

response location

no

rma

lize

d r

esp

on

se

[C

/W], e

ach

so

urc

e J1 at 1 W

J2 at 1 W

J3 at 1 W

J4 at 1 W

J5 at 1 W

J6 at 1 W

Page 131: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Filling in the theta-matrix

• Handy formulas for quick estimates

• Utilizing symmetry

Page 132: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology131

Conduction resistance

L

TAk

dx

dTAkq

basic heat transfer relationship for 1-D conduction

if we define

then

q

TR

Ak

LR

Page 133: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology132

Convection resistance

TAhq

basic heat transfer relationship for surface cooling

if we define

then

q

TR

hA

1R

Page 134: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology133

T))((

))()((

)(

a

2

a

2

aa

2

a

2

4

a

4

TTTTAF

TTTTTTAF

TTAFq

Radiation resistance

temperatures must

be expressed in

degrees “absolute”!

basic heat transfer relationship for surface radiation

if we define

then

q

TR

))((1

a

2

a

2 TTTTFAR

Page 135: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology134

Thermal capacitance and time constant

RC=VcC p

Ah

1R

Ak

LR

Capacitance is ability to store energy

specific heat is energy storage/mass

Based on simple RC concept, relate

rate of storage to rate of flux,

result is

so if and if

and

thenthen

and)( ALcC pρ

22p L

k

Lc

)( ALcC pρ

h

Lcp

Page 136: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology135

Some useful formulas

• conduction resistance…………..………

• convection resistance…………...………

• thermal capacitance……………...……..

• characteristic time…………………..….

– (dominated by 1-D conduction)

• characteristic time……………………...– (dominated by 1-D convection)

• short-time 1-D transient response……...

RL

k A

R1

h A

C cpV

cpL2

k

cpL

h

TQ

A

2

cpkt

Page 137: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology136

Terms used in preceding formulas

• L - thermal path length

• A - thermal path cross-sectional area

• k - thermal conductivity

• - density

• cp - heat capacity

• - thermal diffusivity

• - thermal effusivity

• h - convection heat-transfer “film coefficient”)

• T - junction temperature rise

• Q - heating power

• t - time since heat was first applied

cpk

k

cp

Page 138: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology137

mainly package

materials/conduction effects

mainly local

application board

conduction effects

mainly environmental

convection and radiation effects

When do these effects enter?

time

jun

cti

on

te

mp

era

ture

typical heating curve

for device on FR-4

board in still-air

hundreds of seconds

a second or so

tens of seconds

Page 139: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology138

if

then and

R

R2

R4

Page 140: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology139

Cylindrical and spherical conduction (through

radial thickness) resistance formulas

Lk

r

r

R

Lk

r

r

R

i

o

i

o

2

ln

ln

• L – cylinder length

• ri – inner radius

• ro – outer radiuswhere

Half-cylinder

Full cylinderk

rrR

k

rrR

oi

oi

4

11

2

11

Hemisphere

Full sphere

[included angle][solid angle]

Page 141: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology140

Well, what if your cooling depends significantly on convection from the board surface

(whether free or forced air)?

Package-shrink “gotcha”

TAhqTh

qA

Remember how much of theta-JA depends

on what isn’t the package?

So never mind the package resistance, the boardcan only transfer a certain amount of heat to the air:

*Special thanks to Dave Billings for the idea behind this slide

Page 142: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology141

Th

qA

Package-shrink “gotcha”

1 SOT23 on a

250 mm2 spreader,

JA=200°C/W

1.0 W1000

mm21E-5

mm2 °C

W100°C

So if 4 SOT23’s each have

0.25 W, then

T=0.25*200=50°C

No problem!

Whew!Fortunately, 0.25 W each x 400°C/W→100°C

PROBLEM:

4 SOT23’s on a 1000 mm2

board, effective JA=400°C/W

*Special thanks to Dave Billings for the idea behind this slide

Page 143: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology142

4

NOW your favorite supplier comes out with the next

generation version (much smaller) of the same component.

Decrease size

(but not power

dissipation)

Decrease size

and reduce

power dissipation

(RDSON or other

electrical

performance)

Package-shrink “gotcha”

4 SOT723’s on a 1000 mm2

board, JA=400°C/W,

T=100°C, power = 1 W total,

0.25 W each

8 SOT723’s on a 1000 mm2

board, JA=800°C/W,

T=100°C, power = 1 W total,

0.125 W each

How many SOT723’s can you

put in that same 1000 mm2?

SOT23

SOT723

ANSWER: 8

4 SOT23’s on a 1000 mm2

board, JA=400°C/W,

T=100°C, power = 1 W total,

0.25 W each

*Special thanks to Dave Billings for the idea behind this slide

Page 144: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology143

PERIODIC and NON-PERIODIC

POWER INPUT

• Duty-cycle curves

– Normalized and non-normalized

• Linear superposition applied to time domain

Page 145: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology144

Square-wave duty cycles (aka ratios)

• What the heck are they?

– show peak junction temperature as a function of

duty cycle and “pulse width”

• Where do they come from?

– “heating curve” is equivalent to the limiting case of a

0% duty-cycle, where once the “pulse width” is over,

there’s never another cycle

– “linear superposition” allows you to generate the

whole family from the heating curve

Page 146: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology145

0

0.5

1

1.5

2

2.5

0.00001 0.0001 0.001 0.01 0.1 1 10t, time (s)

R(t

), T

he

rma

l R

esis

tan

ce

[°C

/W]

0.05

Single pulse

0.10.2

d=0.5

Representative “duty cycle” response chart

Page 147: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology146

It begins with one of these:

A “single-pulse” response is the same as a 0% duty cycle

- if you think in terms of a 0% duty cycle meaning you have

only one pulse (however long it lasts), but once you turn if

off, you never turn it back on again. So any finite “on” time

is zero percent of infinitely long “off”.

transient thermal response

for axial lead rectifier

Junction-to-Lead, 1/4" lead length

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100 1000time [s]

R(t

)JL

C/W

]

Page 148: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology147

“published” formulas

)()()( *1, trdddtr

d

trtr

d

ttrdddtr )()()( *1,

)()()()()( *1, prtrptrdddtr

)()()( 1, tRdRddtR

d

tRtR

d

ttRdRddtR )()()( 1,

RddtRt

)( ,lim0

RdtRt

)( ,lim

Non-dimensionalized versions dimensionalized versions

Page 149: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology148

A “normalized” curve:

Is this really such a bright idea?

normalized transient thermal response

for axial lead rectifier

Junction-to-Lead, 1/4" lead length

0.01

0.1

1

0.0001 0.001 0.01 0.1 1 10 100 1000time [s]

r(t)

JL [n

orm

alized

]

JL=27.4°C/W

Page 150: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology149

Consider this family of

“non-normalized” curves:

Transient thermal response for axial lead rectifier

Junction-to-Lead, varying lead length

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100time [s]

R(t

) JL [°

C/W

] R(t)-1"

R(t)-3/8"

R(t)-1/32"

Page 151: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology150

The danger!

normalized transient thermal response for

axial lead rectifier, Junction-to-Lead

varying lead length

0.001

0.01

0.1

1

0.0001 0.001 0.01 0.1 1 10 100time [s]

r(t)

JL

[no

rmali

zed

]

r(t)-1/32"

r(t)-3/8"

r(t)-1"

JL-1/32"=20.0°C/W

JL-3/8"=34.9°C/W

JL-1"=54.9°C/W

Transient thermal response for axial lead rectifier

Junction-to-Lead, varying lead length

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100time [s]

R(t

) JL [°

C/W

] R(t)-1"

R(t)-3/8"

R(t)-1/32"

See what

happens to

the short-

time

response

when you

“normalize”!

Page 152: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology151

Compare the families of curves:

square-wave duty cycles

for 1/32" lead length

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100time [s]

R(t

) JL

[°C

/W]

single pulse

1% duty cycle

2% duty cycle

5% duty cycle

10% duty cycle

20% duty cycle

50% duty cycle

square-wave duty cycles

for 1" lead length

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100time [s]

R(t

) JL

[°C

/W]

single pulse

1% duty cycle

2% duty cycle

5% duty cycle

10% duty cycle

20% duty cycle

50% duty cycle

Same short-

time 0%

(single-pulse)

Different

everything

between !!

Different

steady

states

Page 153: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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What to do if you’re given a

normalized curve

• Find out what reference value

it was normalized from

– Undo it

• If you can’t find out

– Throw the curve away

Page 154: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Linear Superposition

Applied to Time Domain

Page 155: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Basic heating curve - a “single pulse”

R(t)

t

t

Q

power input corresponding to single pulse heating curve

Page 156: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Single pulse (actually turned off)

t

Q

a

equals

t

Qplus

t

Q

a

R(t)

t

plus

R(t)

t

a equals

R(t)

ta

Finite pulse, decomposed into two infinite steps

(constructed from superposition of two single pulse responses)

Temperature response of a finite pulse

Page 157: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Two differing pulses

Two finite pulses decomposed into infinite steps

t

Q1

a b c

Q2

t

Q1

a

b

c

-Q1

Q2

-Q2

Temperature response constructed for two finite pulses

(constructed from superposition of four single pulse responses)

R(t) R(t)

is made up of

results in this

Page 158: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology157

An arbitrary pulse train

• Temperature at end of nth pulse

n

i

ininin ttRttRPT1

12122212 ][ )()(

Notes: times and pulses must be in

strictly increasing chronological order

When there is no “off” period between

two consecutive pulses, set

(i.e. do not “combine” them into a single

value)

P1

P2

Pn

t0 t1 t2 t2n-2 t2n-1 t3

Pow

er

time For temperature at the beginning of the

nth pulse, set 2212 nn tt

3222 ii tt

Page 159: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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An example

P1

P2

P3

100

80

60

40

20

0 t0 t1 t2 t4 t5 t3

P(P

K) P

eak P

ow

er

(Watt

s)

t, Time (ms) 1 2 3 4

T1

T2

T3

t0 t1 t2 t4 t5 t3

Ju

nctio

n T

em

pera

rure

t, Time (ms) 1 2 3 4

)( 111 tRPT

)(

)()(

232

13312 ][ttRP

ttRtRPT

)(

)()(

)()(

453

35252

15513

][

][

ttRP

ttRttRP

ttRtRPT

Item Value unit

P1 80 W

P2 40 W

P3 70 W

t1 0.0001 s

t3 0.0013 s

t3-1 0.0012 s

t3-2 0.0010 s

t5 0.0035 s

t5-1 0.0034 s

t5-2 0.0032 s

t5-3 0.0022 s

t5-4 0.0002 s

Item Value unit

t0 0.0000 s

t6 0.0003 s

t4 0.0012 s

Page 160: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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How to read the curve

• For small time differences, and on a low resolution

log-log plot, what can you do?

Transient thermal response for axial lead rectifier

Junction-to-Lead, varying lead length

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100time [s]

R(t

) JL [°

C/W

] R(t)-1"

R(t)-3/8"

R(t)-1/32"

Item Value unit

P1 80 W

P2 40 W

P3 70 W

t1 0.0001 s

t3 0.0013 s

t3-1 0.0012 s

t3-2 0.0010 s

t5 0.0035 s

t5-1 0.0034 s

t5-2 0.0032 s

t5-3 0.0022 s

t5-4 0.0002 s

Page 161: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology160

Assume power law

(straight line on log-log plot)

ntatR )(

nnt

tR

t

tRa

2

2

1

1 )()(

1

2

1

2

log

log)(

)(

tt

tR

tR

nt

ntRtRtR )()()(

nn

ttR

t

ttRtR 1)()()(

tt

tt

1

12

Page 162: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology161

How to read the curve #2

• For small time differences, and on a low resolution

log-log plot, what can you do?

Transient thermal response for axial lead rectifier

Junction-to-Lead, varying lead length

0.1

1

10

100

0.0001 0.001 0.01 0.1 1 10 100time [s]

R(t

) JL [°

C/W

] R(t)-1"

R(t)-3/8"

R(t)-1/32"

R(.0001) 0.22

R(.02) 3.3

anchors

R(t1) 0.22

R(t3) 0.82

R(t3-1) 0.79

R(t3-2) 0.72

R(t5) 1.36

R(t5-1) 1.34

R(t5-2) 1.30

R(t5-3) 1.08

R(t5-4) 0.32

interpolate

Page 163: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology162

Results

C

ttRPttRttRP

ttRtRPT

C

ttRPttRtRPT

CtRPT

8.324.228.86.1

32.07008.130.14034.136.180

2.318.284.2

72.04079.082.080

6.1722.080

)()(

)(

)()()(

)()(

)()()(

)(

45335252

15513

23213312

111

][

][

][

P1

P2

P3

100

80

60

40

20

0 t0 t1 t2 t4 t5 t3

P(P

K) P

eak P

ow

er

(Watt

s)

t, Time (ms) 1 2 3 4

T1

T2

T3

t0 t1 t2 t4 t5 t3

Ju

nctio

n T

em

pera

rure

t, Time (ms) 1 2 3 4

Page 164: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology163

Another transient analysis example

repeat 20 times, then stop for

6800 microseconds

23

18 25.2W

power

time

802

25.2W

power

time

last of 20 pulses ends 7600

20 pulses 20 pulses

Here’s our

power input

scenario:

Page 165: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology164

Superposition of average and

disturbance

“peak”

“valley”

Tavg

0

Actual duty cycle and

response

equivalence of non-zero average response with

(constant average) + (zero-average disturbance)

Tavg due to Qavg

Q

Qavg= d · Q

Power shifted to

average zero

0

(1-d) · Q

- d · Q

Page 166: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology165

repeat 20 times

23

18 25.2W

power

time

Another example, cont’

How do we analyze it? Over three time scales:

802

25.2W

power

time

last of 20 pulses ends 7600

20 pulses

25.2W

power

time

7600

burst

15200

instantaneous excursions

based on “local” duty cycle

average excursions based

on “global” duty cycle

“average” Tj based

on local avg power

“average” Tj based

on global avg power

Page 167: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Endless Possibilities

Page 168: Semiconductor Thermal Design

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A “ramp”

A finite ramp decomposed into several infinite steps

t

P

a t

P

a

Temperature response constructed for finite ramp

(constructed from superposition of many single pulse responses)

t

Q

a

t

Q

a

is made up of

results in this

Page 169: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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An arbitrary pulse

An arbitrary pulse decomposed into several infinite steps

t

Q

ais made up of

Q

Temperature response constructed for this arbitrary pulse

t

Q

results in this

t

Q

Page 170: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Multiple Time-Varying

Heat Sources

Page 171: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology170

)(

)(

)(

)()()(

)()()(

)()()(

)()()(

)()()(

)(

)(

)(

)(

)(

3

2

1

321

312111

321

23212

13121

1

2

1

tq

tq

tq

ttt

ttt

ttt

ttt

ttt

tT

tT

tT

tT

tT

BBB

LLL

xxx

JA

JA

BA

AL

xA

j

j

one column for

each heat sourcejunction

temperature

vector

power input

vector

one row

for each

heat

source

one row for each temperature

location of interest

Basically the same theta-matrix idea, only

now everything is a function of time as well

Page 172: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Each heat source

needs to be

independently heated.

Each temperature needs to be

measured whether heating itself

or being heated by another.

Po

we

r in

pu

t (W

)

Time (sec)

Time (sec)

Te

mp

era

ture

(°C

)

thermal system

boundary

Measurement cycle(s)

*Special thanks to Dave Billings for this slide

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• Grounded (Cauer) vs.. non-grounded

(Foster)

• Orders of magnitude, rungs

• Pulses and periodic waveforms

• Short-time behavior, limits, and limitations

Thermal RC networks

but first, some words about …

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Thermal capacitance

(grounded vs.. non-grounded)

• In electrical circuit, voltage on a capacitor is

difference between its two terminals, and you have

physical access to both

• A “lumped parameter” thermal model is predicated

on energy storage being determined entirely by one

temperature

• Therefore, in a thermal circuit, you only have access

to one “terminal” of each capacitor, namely the one

where you identify the temperature. The other

terminal is “ground”.

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• Physical significance: if thermal capacitors are grounded,

they bear some relationship to a physical system; not so

for non-grounded C’s

• Mathematical convenience: certain non-grounded

networks are mathematically “trivial”

• Interchangeability: single-input thermal systems can be

represented as either grounded or non-grounded;

• multiple-input thermal systems are easy to model as

grounded-C networks; it can be done, though with some

intricate bookkeeping, using non-grounded-C networks

“Cauer” ladders “Foster” ladders

Models: grounded vs.. non-grounded

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7.02E-04 W-sec/°C

4.41E-03

5.89E-02

1.55E-01

6.03E-01

1.46E+00

4.16E+00

1.7004 °C/W

2.6627

3.9740

10.0255

11.7747

35.3008

33.1212

Tj

Ta

Actual thermal RC networks

Tj

Ta

2.3207 °C/W 5.96E-04 W-sec/°C

2.7397

8.3551

14.6949

21.0538

39.637

9.7581

4.20E-03

3.67E-02

1.01E-01

4.13E-01

9.20E-01

1.14E+01

“Cauer” ladder“Foster” ladder

Non-grounded C vs.. grounded C comparison

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2-rung Foster model

1

sC1

1

R1

R2

R2C2s 1

R1

R1C1s 1

R2

R2C2s 1

1

sC1

1

sC2

R1

R2

C1

C2

R1

R2

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2-rung Cauer model

C1

C2

R1

R2

1

sC1

1

R1

R2

R2C2s 1

R1R2C2s R1 R2

R1C1R2C2s2

R1C1 R2C1 R2C2 s 1

1

sC1

1

sC2

R1

R2

1

sC1R1

R2

R2C2s 1

1

sC1

R1

R2

R2C2s 1

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• Time constants are roots of denominators

• "tau" is not RC product when capacitors are grounded !

R1

R1C1s 1

R2

R2C2s 1

can be written

1

C1

1

s1

1

1

C2

1

s1

2

where time constants are

1 R1C1 2 R2C2

non-grounded

capacitors:

where time constants are

1

2 R1C1

1c

rc 1

c

rc

2

4c

r

21

221

21

1 11

1 written becan

ss

CRR

RRs

C

R1R2C2s R1 R2

R1C1R2C2s2

R1C1 R2C1 R2C2 s 1

grounded-capacitors:

2

2 R2C2

1r

cr 1

r

cr

2

4r

c

and defining rR2

R1

cC1

C2

r c1

R1C1

2

R2C2

100 0.01 0.99 1.01

10 0.1 0.91 1.10

3 1 /3 0.73 1.36

1 0.1 0.90 1.11

1 1 0.38 2.62

(Cauer)

(Foster)

2-rung models compared

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7.02E-04 W-sec/°C

4.41E-03

5.89E-02

1.55E-01

6.03E-01

1.46E+00

4.16E+00

1.7004 °C/W

2.6627

3.9740

10.0255

11.7747

35.3008

33.1212

Tj

Ta

Tj

Ta

2.3207 °C/W 5.96E-04 W-sec/°C

2.7397

8.3551

14.6949

21.0538

39.637

9.7581

4.20E-03

3.67E-02

1.01E-01

4.13E-01

9.20E-01

1.14E+01

“Cauer” ladder“Foster” ladder

Rungs can be in any order

and Tj has identical behavior!

So where do you “split” it?

Order matters, so a “split” can

make good physical sense.

package

environment

??

Interesting (and important) implications

Page 181: Semiconductor Thermal Design

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Orders of magnitude and rungs

• It is a rare transient curve that cannot be followed very

accurately with time constants no closer than about 1

order of magnitude apart. This means that you need

only about one rung per decade of transient response.

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For what it’s worth ...

Every Foster (non-grounded-capacitor) ladder having

distinct (i.e. non-repeated) time constants, has a

corresponding Cauer (grounded-capacitor)

equivalent. (However, there is no a priori guarantee

that all R’s and C’s will be positive!)

Every Cauer (grounded-capacitor) ladder has a

mathematical solution. By definition, its

mathematical solution represents a corresponding

Foster (non-grounded-capacitor) ladder.

Ref: L. Weinberg, Network Analysis and Synthesis, McGraw Hill Book Company, Inc., 1962

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...

1...

1

1

1

1

2

2

1

1

R

sC

R

sC

Z

...1

...11 22

2

11

1

sCR

R

sCR

R

sCR

RZ

ii

i

sD

sNZ

n

n

1

Cauer ladder continued fraction:

Foster ladder,

sum of simple fractions:

with some

algebra, both

may be written:

RC network math

Page 184: Semiconductor Thermal Design

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Arbitrary repetitive pulse

Q

p 2p

p – period of waveform

t

Page 185: Semiconductor Thermal Design

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So consider a general rectangular pulse positioned arbitrarily within a

repetitive cycle of period p.

Generalized periodic square wave

Q

b – pulse turns off

p 2p

t – arbitrary time of interest

bta ptb

We can derive expressions for the

infinite sum of responses in three regions :

a – pulse turns on

m

i

t

iieRtR

1

1)(

t′ – measured from edge

of power step

m

i

at

iieRtR

1

1)(

1

1)(j

jpbt

iiieRtF

1

1)(j

jpat

iiieRtF

m

i

bt

iieRtR

1

1)(

at0

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Infinite summation

Utilizing the identities

and doing some algebra, we can show these results:

zz

j

j

1

1

0 1

1

1 zz

j

j

m

i

i tFtF1

)()(

i

ii

p

ptaptb

ii

e

eeRtF

1

)(

i

ii

p

taptb

ii

e

eeRtF

1

1)(

i

ii

p

tatb

ii

e

eeRtF

1

)(

bta ptbat0

and

In each domain, we then sum over

all rungs of the Foster model:

Page 187: Semiconductor Thermal Design

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RC Model for Multiple Square Waves in One CycleEnd result for arbitrary periodic power

An important point of this

example is that for complex

power inputs, absolute peak

temperatures do not always

correspond to the ends of

the highest power pulse!

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Short-time limits

• What do RC models do at shortest time?

– roll off linearly with time

2

1

2

1

12

1

2

1

1

2

2

2

2

22

1

2

1

1

21

22

211

211

11 21)(

ttR

ttR

ttR

ttR

eReRtR

tt

2

2

2

2

2

2

1

1

2

2

1

1)(tRR

tRR

tRSo for small t:

tconsttR )()(

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RC models and Surface Heating

• It turns out that if R’s and C’s grow at a uniform ratio, a

sqrt(t) behavior ( ) is approached in the limit

• If ratio is 1:3 (increasing with “distance” from junction

node), rung-to-rung time constant ratio will be about

one order of magnitude, and the network will follow

theoretical sqrt(t) within a few percent

tb

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1.0E+0

1.0E-4

1.0E-3

1.0E-2

1.0E-1

1.0E+11.0E-8 1.0E-7 1.0E-6 1.0E-5 1.0E-4 1.0E-3 1.0E-2 1.0E-1 1.0E+0

1 rung

2 rungs @ 3.0:1

3 rungs @ 3.0:1

4 rungs @ 3.0:1

5 rungs @ 3.0:1

Exact sqrt(t) model

Rungs vs.. sqrt(t) behavior

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Where does that leave us with respect to

the applicability of RC networks?

• We need to pay attention to silicon thickness vs..

device “technology”

– if surface heating is a good model, be sure your RC network

has time constants short enough to land “within” the silicon

– within the silicon timescale , if surface heating is a good

model, you have to “extend” the RC network into that region

2L

– on the other hand, if surface heating is not a good model

(implying that volumetric heating is better), the fastest rung of

your RC network can be set to the actual R&C corresponding

to the volume being heated

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Multiple heat-source RC networks

• You need data (experiment or simulation)

• Fit an RC network (or networks) to the data

– Foster networks, we’ll see an Excel-based approach

– Cauer networks, beyond the scope of this tutorial

• Using SPICE: directly input your RC networks

– Foster networks can be complicated

– Cauer networks are straightforward

• Using Excel:

– Foster networks, we’ll see an Excel-based approach

– Cauer networks are not practical

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Typical 2-input heating/response curves

0

50

100

150

200

250

1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3

heating time [s]

R(t

) [C

/W]

q1 self avg

q2 self avg

interact

q1 RC-fit

q2 RC-fit

q1<->q2 fit

q1

q2

Page 194: Semiconductor Thermal Design

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Fitting Foster ladders in Excel

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RMSE 1.9 1.3 0.5

test pow er [W] 1.00 1.00 1.00 TABLE 1: Foster model

Time

q1 self

avg

q2 self

avg interact

q1 RC-

fit

q2 RC-

fit

q1<-

>q2 f it taus q1 R's q2 R's

interact

R's

1.26E-4 8.48 1.16 0.00 9.18 1.01 -0.03 1.0E-4 11.2 0.8 -0.1

1.64E-4 9.68 1.32 0.00 10.51 1.20 -0.03 1.0E-3 7.6 2.9 0.3

2.09E-4 10.59 1.50 0.00 11.67 1.40 -0.03 1.0E-2 12.5 2.3 -0.7

2.60E-4 11.82 1.67 0.00 12.63 1.59 -0.03 1.0E-1 76.6 45.6 -2.3

3.18E-4 14.14 1.84 0.00 13.45 1.79 -0.02 1.0E+0 70.0 67.5 38.4

3.82E-4 14.64 2.02 0.00 14.14 1.98 -0.01 1.0E+1 2.3 2.2 4.0

4.58E-4 15.37 2.21 0.00 14.80 2.19 0.00 1.0E+2 41.0 37.7 34.1

5.48E-4 15.87 2.42 0.00 15.46 2.41 0.01

6.57E-4 16.37 2.65 0.00 16.16 2.67 0.02 TABLE 5: results at arbitrary times

7.78E-4 16.98 2.89 0.00 16.86 2.92 0.03 120.5 100.7

9.19E-4 18.45 3.14 0.00 17.60 3.20 0.04 0.00 25.0 25.0

1.09E-3 18.58 3.17 0.00 18.39 3.50 0.04 0.01 59.6 30.0

1.28E-3 20.29 3.76 0.00 19.21 3.80 0.05 0.05 90.0 39.1

Using RMSE as fitting parameter

{=SQRT(SUMSQ(E4:E100-

B4:B100)/COUNT(E4:E100))}

A B C D E F G H I J K L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

{=$G$2*SUM(interact_Rs

*(1-EXP(-A4/taus)))}

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Use Excel’s “solver” to

minimize the error between the

input data and the RC model.

0.1

1

10

100

1000

1E-

06

1E-

05

1E-

04

0.001 0.01 0.1 1 10 100 1000

Time (sec)

R(t

) (C

/W)

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

Fit e

rror

(C/W

)

Simlation data

R-C model

Fit Error

After optimization

Simulation data

Excel’s “Solver”

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Using SPICE to exercise the models

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Using Foster RC models in SPICE

Tself1 (volts)

Tpos2

Tneg2

Tj1

+

-

Tself2 (volts)

Tpos1

Tneg1

Tj2

+

-

identical networks of

negative interaction

elements

identical networks of

positive interaction

elements

different networks

of self heating

elements

Q2 (amps)

time

Q1 (amps)

time

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1/4th of a 4-input Foster RC SPICE model

Piecewise linear current source for power input from

each source generating heat.

Summing tool to add voltages from the separate

interaction networks with the self heating network

Thermal ground – by adding a voltage potential to the

ground point ambient temperature can be added.

Thermal equivalent Foster RC networks

(note that all these R’s are positive)

The output port (OUT1) will be where you want to

monitor the temperature response

Each heat source will require a similar block in order to

simulate the temperature response of the self heating

effect as well as the interactions.

*Special thanks to Dave Billings for this slide

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A 2-input Cauer network model

Tj1 Tj2q1 (watts)

q2 (watts) Apply q2 to Tj2 node

C11

C12

C6

C14

R11C21

C22

C5

C7

C23

C24

R21

R22R12R33

R44R13 R23

R24R14

R5

R6

R7

Apply q1 to Tj1 node

time

time

C13

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Using Excel to exercise Foster models

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Semiconductor Device Thermal Characterization

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ambient 25

TABLE 1: Foster model TABLE 2: pow er input vs time

taus q1 R's q2 R's

interact

R's t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11

1.0E-4 11.2 0.8 -0.1 change_at 0.00 0.10 0.25 0.40 1.00 1.10 1.50 2.00 2.60 3.00 5.00 10.00

1.0E-3 7.6 2.9 0.3 q1_pow er 1.0 1.0 0.0 0.8 0.8 0.0 0.0 0.0 0.0 0.6 0.6 0.0

1.0E-2 12.5 2.3 -0.7 q2_pow er 0.5 0.0 1.3 0.9 0.0 0.0 1.0 0.0 0.4 0.4 0.7 0.7

1.0E-1 76.6 45.6 -2.3 delta q1 1.0 0.0 -1.0 0.8 0.0 -0.8 0.0 0.0 0.0 0.6 0.0 -0.6

1.0E+0 70.0 67.5 38.4 delta q2 0.5 -0.5 1.3 -0.4 -0.9 0.0 1.0 -1.0 0.4 0.0 0.3 0.0

1.0E+1 2.3 2.2 4.0

1.0E+2 41.0 37.7 34.1 time TABLE 3: unit step relative to chosen time

0.5 0.50 0.40 0.25 0.10 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00

TABLE 5: results at arbitrary times TABLE 4: sum of terms

120.5 100.7 T1_terms 141.5 -5.1 -109.3 68.4 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0

0.00 25.0 25.0 T2_terms 51.7 -36.6 75.7 -15.1 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0

0.01 59.6 30.0

0.05 90.0 39.1

0.10 112.2 47.4

0.25 143.6 37.1

0.26 116.5 46.3

0.26 110.0 50.3

0.27 101.0 56.9

0.29 89.2 67.4

0

20

40

60

80

100

120

140

160

180

0.01 0.1 1 10

tem

pera

ture

[C

]

0

0.2

0.4

0.6

0.8

1

1.2

1.4Tj1

Tj2

q1_pow er

q2_pow er

Setting up a 2-input Excel modelI J K L M N O P Q R S T U V W X Y Z

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22{=TABLE(,time)}

=SUM(T1_terms)+ambient

=SUM(T2_terms)+ambient

{=SUM((R7*interact_Rs+R8*q2_Rs)*(1-EXP(-time/taus)))}

{=SUM((S7*q1_Rs+S8*interact_Rs)*

(1-EXP(-time/taus)))}

{=IF(time>change_at,time-change_at,0)}

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Results from a 2-input Excel Foster model

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

180.0

0 1 2 3 4 5 6time [s]

tem

pera

ture

[C

]

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

po

wer

[W]

Tj1

Tj2

q1_pow er

q2_pow er

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Organizing the sheet for transient solution

A section for power input

to the heat sources

A section for

power

changes

A section for

Temperature response

calculation

A cell for

keeping

track of the

overall time

progression

of ALL

blocks.

A section

for Time

changes

=IF(Master_Time>Row_Time,Master_time-Row_time,0)

Self heating column (each cell is a separate array formula)

{=dP-D#*SUM(R1:R10*(1-EXP(-dtime/Tau1:Tau10)))}

Interaction heated columns (each cell is a separate array formula)

{=dP-D#*SUM(R5:R10*(1-EXP(-dtime/Tau5:Tau10)))}

*Special thanks to Dave Billings for this slide

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Table for plotting temperature output

=SUM(D1:D1_by_D4) +T_ambient

Note!

Time in this column

can be independent of

the time values in the

power input section

Next, Select this

whole region

Apply a

Data > Table option

*Special thanks to Dave Billings for this slide

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0

0.5

1

1.5

2

2.5

3

0 0.05 0.1 0.15 0.2 0.25 0.3Time (Sec)

Tem

per

atu

re(C

)

0

0.5

1

1.5

2

2.5

3

0 0.05 0.1 0.15 0.2 0.25 0.3Time (Sec)

Tem

per

atu

re(C

)

Results from a 4-input Excel Foster model

00.20.40.6

0.81

1.21.4

0 0.05 0.1 0.15 0.2 0.25Time (Sec)

Po

wer

(W)

D1

00.20.40.6

0.81

1.21.4

0 0.05 0.1 0.15 0.2 0.25Time (Sec)

Po

wer

(W)

00.20.40.6

0.81

1.21.4

0 0.05 0.1 0.15 0.2 0.25Time (Sec)

Po

wer

(W)

00.20.40.6

0.81

1.21.4

0 0.05 0.1 0.15 0.2 0.25Time (Sec)

Po

wer

(W)

0

0.5

1

1.5

2

2.5

3

0 0.05 0.1 0.15 0.2 0.25 0.3Time (Sec)

Tem

per

atu

re(C

) T_D1

T_D2

T_D3

T_D4

0

0.5

1

1.5

2

2.5

3

0 0.05 0.1 0.15 0.2 0.25 0.3Time (Sec)

Tem

per

atu

re(C

)

Last

power

input

D2

D3

D4

*Special thanks to Dave Billings for this slide

Page 207: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology206

Recap

• With the right tools, a thermal RC network can be

generated from temperature data which is captured

from measurements or finite element simulation.

• Linear superposition provides a method for generating

transient thermal models with several heat sources.

• Foster networks can be used to simulate the thermal

response of a system using a spreadsheet, whereas

Cauer networks (which are closer to a physical lumped

system) may require special tools (e.g. SPICE).

Page 208: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Thermal Runaway

Part III

Page 209: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Thermal runaway

• Non-linear power vs.. junction temperature device characteristic

• System thermal resistance isn’t low enough to shed small perturbations

Page 210: Semiconductor Thermal Design

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and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology209

A linear thermal cooling system

xJxJ TQT

Jx

xJ TTQ

JxdT

dQ 1

junction temperature as function

of power, theta, and ground

… solving for power

sensitivity (slope) of power with

respect to temperature

Page 211: Semiconductor Thermal Design

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and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology210

power

junction temperature

Q

Tx TJ

device line

system line

tendency

to cooltendency

to heat

Effect of device line slope on system stability

Page 212: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology211

system cannot

be successfully

powered up

system

temperature

cannot be

maintained

Operating points of thermal system when

device line has negative second derivative

power

junction temperature

Q2

Tx

TJ2

power goes up with

increasing temperature

device line

system line

the stable (that is,

real) operating point

an unachievable

operating point

tendency

to cool

tendency

to heat

tendency

to cool

Q1

TJ1

but rate of increase

falls with increase

(negative second

derivative)

Page 213: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology212

even turning

the device on

destroys it

any

perturbation

will cause

runaway

Operating points of thermal system when

device line has positive second derivative

power

junction temperature

Q

Tx TJ

power goes up with

increasing temperature,

but rate of increase rises

with increase (positive

second derivative)

device line

system line

the stable

(that is, real)

operating

point

an unachievable

operating point

tendency

to cool

tendency

to heat

tendency

to heat

Page 214: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Let’s see how it works

device

operating

curve

25°C/W

system

stable

operating

point

unstable operating point

10°C/W

system

NO

operating

point!

40°C/W

system

0.0

0.4

0.8

1.2

1.6

2.0

20 40 60 80 100Junction Temperature [C]

Devic

e P

ow

er

Dis

sip

ati

on

[W

]

Page 215: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology214

A paradox

junction

thermal ground

50°C/W

lead

100°C/W

100°C

75°C

25°C

0.5 W

thermal runaway,

based on Jx=150°C/W,

calculated to be at 125°C

junction

thermal ground

50°C/W

lead

0.2°C/W

100°C

75°C

74.9°C

0.5 W

thermal runaway,

based on Jx=50.2°C/W,

calculated to be at 150°C

identical

Case A Case B

Page 216: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology215

100 + 5.02°C

75 + 0.02°C75 + 10°C

100 + 15°C

Paradox lost

junction

50°C/W

lead

100°C/W

(fixed) 25°C

junction

50°C/W

lead

0.2°C/W

(fixed) 74.9°C

Case A Case B

raise the power by 0.1 W and see what happens

0.5 + 0.1W 0.5 + 0.1W

Page 217: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Illustrating the paradox

100°C25°C 74.9°C

common nominal

operating point

0.5 W

Case A

Case B

device

line

Page 218: Semiconductor Thermal Design

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Generic power law device and

generic linear cooling system

power

junction temperatureTx

device

lineunstable

operating

point

system line B

Ty

stable

operating

pointrunaway point for

original theta

runaway point for

original thermal ground

system

line C

1

Jx1 Jx1

1

1

Jx2

system line A

TR2 TR1

Q

TJ

Page 219: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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Don’t get confused by the terms!

xay

xey

IVQ

a

mathematical

“power law”device

power

an “exponential”

power law (base is e)

Page 220: Semiconductor Thermal Design

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and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology219

Definition of power law device

10

T

o 2II

2

10

T

o10

T2

o eIeII lnln )(

T

oeII

2

1

21

II

TT

ln

T

o

T

oR eQeIVQ

T

o eQ

dT

dQT

2

o

2

2

eQ

dT

Qd

rule of thumb for leakage;

2x increase for every 10°C for constant voltage, power

does the same

1st and 2nd derivatives

both always positive

defining:

Page 221: Semiconductor Thermal Design

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The mathematical essence

Jx

xTTQ

T

oeQQ

xT

oJx

eQ

k

zekz

System line

Power law

device line

xTTz

QeQ

1q

xT

o

Non-dimensionalizing

temperature

power

where:

zeq

(power law device)

kzq

Leads to:

(system)

Eliminating q:

Page 222: Semiconductor Thermal Design

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Perfect runaway transformed

ez

at point of tangency,

slope equals height

zT1z0

k=ez

1zz 0T

xTTz

zT1z0

k=ez

zT1z0

k=ez

zT1z0

k=ez

Page 223: Semiconductor Thermal Design

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Transforming the nominal system

ez

at point of

tangency, slope

equals height

1

k=e

“operating”

pointsk > e(2 intersections)

k < e(no intersections)

nominal

system line A

Page 224: Semiconductor Thermal Design

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Everything transformed

non-dimensional

power

device line

unstable,

non-operating

point

stable

operating

point

system line A

zR2

runaway point for

original theta

runaway point for

original thermal ground

system line B

system line C

non-dimensional temperature

zR1

k1

1 zx1

k2

1

)( 1R1 kz ln1kz 1x1 )(ln 1z 2R

ek2

k1

1

q=k1z

q=k1(z-zx1)

q=k2z

q=ez

Page 225: Semiconductor Thermal Design

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“Perfect runaway” results

in original terms

o1Jx1R

QT ln

o1Jx1x

QT ln

1T

o2Jx

x

eQ

x2R TT

runaway temperature

based on original slope

max ambient that

goes with it

runaway temperature

based on original ambient

system resistance

that goes with it

Page 226: Semiconductor Thermal Design

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The “operating” points

ez

“operating”

points

1

kz

szs ekz

uzu ekz

sz uz

stable

unstable

Page 227: Semiconductor Thermal Design

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Newton’s method for the intersections

i

i

1i

z

11

ze

k

z

ln

)()(

i

i

i1izF

zFzz

zkzln

kzzzF ln)(

For k/e ranging between 1.01 and 1000, convergence is

to a dozen significant digits in fewer than 10 iterations.

zekz

e

ke

1

k

1zo

this initial guess

converges to lower,

stable point e

k1kzo lnln

this initial guess

converges to upper,

unstable point

z

11zF )(

Page 228: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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And the intersection points come from

stablexstable zTT

find the non-dimensional intersections first,

then

unstablexunstable zTT

Page 229: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

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[°C] 17.9 17.8

[W] 9.4E-5 1.02E-3

Real datasheet example

Vr [V] 12 40

Tmax [°C] 125 125

Tref [°C] 75 75

Itmax [A] 8.50E-3 2.80E-2

Itref [A] 5.20E-4 1.70E-3

oQ

the device power curve parameters

@12V @40V

ref

ref

II

TT

max

max

ln

oR0 IVQrefT

tref

T

t0 eIeIImax

max

T

0eII

14.42

10

)(ln

rule of thumb

gave us:

† MBRS140T3

raw device data†

Page 230: Semiconductor Thermal Design

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and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology229

1.609

83.5

101.3

[°C] 17.9 17.8

[W] 9.4E-5 1.02E-3

(compare to unity)10.6 0.97

given

theta

max [°C] 117.2 74.4

[°C] 135.1 92.2

given

ambient

max [°C/W] 1055 96.6

[°C] 92.9 92.8

Runaway analysis in nominal system

Vr [V] 12 40

Tmax [°C] 125 125

Tref [°C] 75 75

Itmax [A] 8.50E-3 2.80E-2

Itref [A] 5.20E-4 1.70E-3

oQ

ek

xT

1RT

2Jx

2RT

3120z .

raw device data†

computed results

@12V @40V @40V

3152z .

These translate into:

a stable operating point at 80.6°C (and 0.09 W),

an unstable point at 116.3°C (0.69 W)

1001Jx 601Jx

75Tx

1T

oJx

x

eQe

k

† MBRS140T3

Page 231: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology230

HTRB example

• Bidirectional Thyristor in reliability

stress test (High Temperature

Reverse Bias)

• Goal is life tests at elevated

temperature (say 125°C)

• Problem is, they don’t last very long,

and if junction temperature is

anything like the chamber

temperature, they appear to fail way

too early good!

G

MT1

MT2

40 kΩ

640 V

-

HTRB test circuit

+

*Special acknowledgements to Dave Billings and Geoff Garcia for their contributions to this project

Page 232: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology231

HTRB data - sockets without heatsinks

0

20

40

60

80

100

120

140

160

180

200

0 2000 4000 6000 8000 10000 12000

test time [s]

He

ats

ink

(ta

b)

tem

pe

ratu

re [

de

gC

]

DUT T1

DUT T2

DUT T3

DUT T4

DUT T5

DUT T6

DUT T7

DUT T8

DUT T9

DUT T10

HTRB DUT tab temperature vs.. test time

Page 233: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology232

HTRB data - sockets without heatsinks

0

0.5

1

1.5

2

2.5

3

0 2000 4000 6000 8000 10000 12000

test time [s]

DU

T P

ow

er

[W]

DUT W1

DUT W2

DUT W3

DUT W4

DUT W5

DUT W6

DUT W7

DUT W8

DUT W9

DUT W10

HTRB DUT power vs.. test time

Page 234: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology233

HTRB example

Page 235: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology234

Quick calculations from datasheet

JAdaJ PTT

)( 40000640 IIPd

• At room temp, if IDRM is 5 uA, then Pd is about zero (≈3mW),

and TJ should thus equal chamber set point.

• At 85°C, IDRM is about 0.1-0.2mA, thus Pd is on the order of

0.1W, so depending on theta-JA, TJ could be several

degrees hotter than chamber set point (note, however, that

TJ will still be well within 1°C of heatsink temperature, THS)

• HOWEVER, at 125°C, if IDRM is 2mA, then Pd will be in

excess of 1W. Depending on theta-JA, TJ could be 30-60°C

above chamber set point (though still within a couple of

degrees of heatsink temperature, if known).

G

MT1

MT2

40 kΩ

640 V

-

HTRB test circuit

+

HSJdHSJ PTT

or

Page 236: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology235

Calculations based on actual measurements

JAdaJ PTT

1000

senseVI

• At room temp, IDRM (via Vsense) is 0.2uA, thus Pd is about

zero (≈0.1mW), and TJ should thus equal chamber set

point.

• At 85°C, IDRM is about 0.1-0.2mA, thus Pd is on the order of

0.1W, so depending on theta-JA, TJ could be several

degrees hotter than chamber set point (note, however, that

TJ will still be well within 1°C of heatsink temperature, THS)

• At 125°C, IDRM is 2-3mA; Pd could be as high as 1.5W

• Max current observed was nearly 8mA (for Pd of 2.5W),

and estimated TJ of 170°C just prior to device failure.

G

MT1

MT2

40 kΩ

640 V

-

Modified HTRB

test circuit

-

+

1 kΩVsense

+

HSJdHSJ PTT

or

)( 41000640 IIPd

Page 237: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology236

Actual “blocking current” data (time implicit)

blocking current when theta-JA=35°C/W (DUT's in unmodified HTRB board)

1E-7

1E-6

1E-5

1E-4

1E-3

1E-2

20 40 60 80 100 120 140 160

estimated junction temperature [°C]

DUT I1

DUT I2

DUT I3

DUT I4

DUT I5

DUT I6

DUT I7

DUT I8

DUT I9

current

Page 238: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology237

Actual “blocking Pd” data (time implicit)blocking Pd when theta-JA=35°C/W (DUT's in unmodified HTRB board)

1E-4

1E-3

1E-2

1E-1

1E+0

1E+1

20 40 60 80 100 120 140 160

estimated junction temperature [°C]

DUT W1

DUT W2

DUT W3

DUT W4

DUT W5

DUT W6

DUT W7

DUT W8

DUT W9

power

Page 239: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology238

Power vs.. temperature (linear scales)

0

0.5

1

1.5

2

2.5

20 30 40 50 60 70 80 90 100 110 120 130

estimated junction temperature [°C]

Pd

[W

]

DUT W1

DUT W2

DUT W3

DUT W4

DUT W5

DUT W6

DUT W7

DUT W8

DUT W9

37°C/W

system

10°C/

W

system

4°C/W

system

Page 240: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology239

Proof-of-concept modified HTRB fixture

Page 241: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology240

Pd vs.. temperature on better heatsinksblocking current when theta-JA=10°C/W (using external 12°C/W heatsink)

1E-7

1E-6

1E-5

1E-4

1E-3

1E-2

20 40 60 80 100 120 140 160

estimated junction temperature [°C]

DUT I1

DUT I2

DUT I3

DUT I4

DUT I5

DUT I6

DUT I7

DUT I8

DUT I9

Page 242: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology241

Page 243: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology242

What if multiple devices on heatsink?

• Each device heats its neighbors to varying

degrees, depending on distance

• This adds background heat, that

is, it raises the “effective ambient”

of each device

Page 244: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology243

0.0

0.4

0.8

1.2

1.6

2.0

20 40 60 80 100Junction Temperature [C]

Devic

e P

ow

er

Dis

sip

ati

on

[W

]

Graphically, background heat does this

device

operating

curve

25°C/W

system

system with

“background

heating” of

other

devices

real

runaway

margin

jiiij Q

what you

thought

was your

margin

Page 245: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology244

Math and Electrical References1. M. Abramowitz, I. Stegun (eds), Handbook of

Mathematical Functions, Dover Publications, Inc., 9th Printing, Dec. 1972

2. S.D. Senturia, B.D. Wedlock, Electronic Circuits and Applications, John Wiley & Sons, 1975

3. M.F. Gardner & J.L. Barnes, Transients in Linear Systems (Studied by the Laplace Transformation), Vol. I, John Wiley and Sons, 1942

4. R.S. Muller, T.I. Kamins, Device Electronics for Integrated Circuits, 2nd Ed., John Wiley & Sons, 1986

5. Ben Nobel, Applied Linear Algebra, Prentice Hall, 1969

6. H.H. Skilling, Electric Networks, John Wiley and Sons, 1974

7. L. Weinberg, Network Analysis and Synthesis, McGraw Hill Book Company, Inc., 1962

8. H. Wayland, Complex Variables Applied in Science and Engineering, Van Nostrand Reinhold Company

Thermal Textbooks & References9. H.S. Carslaw & J.C. Jaeger, Conduction of Heat In

Solids, Oxford Press, 1959

10. E.R.G. Eckert & R.M. Drake Jr., Heat and Mass Transfer, McGraw Hill, 1959

11. J.P. Holman, Heat Transfer, 3rd Ed., McGraw Hill, 1972

12. J. VanSant, Conduction Heat Transfer Solutions, Lawrence Livermore National Laboratory, Livermore, CA, 1980

569: “Transient Thermal Resistance - General Data and its Use,” May 2003

1083: “Basic Thermal Management of Power Semiconductors,” October 2003

1570: “Basic Semiconductor Thermal Management,” January 2004

8044: “Single-Channel 1206A ChipFET™ Power MOSFET Recommended Pad Pattern and Thermal Performance,” December 2005

8072: “Thermal Analysis and Reliability of WIRE BONDED ECL,” April 2006

8080: “TSOP vs.. SC70 Leadless Package Thermal Performance,” January 2004

8199: “Thermal Stability of MOSFETs,” August 2005

8214: “General Thermal Transient RC Networks ,” April 2006

8215: “Semiconductor Package Thermal Characterization,” April 2006

8216: “Minimizing Scatter in Experimental Data Sets,” April 2006

8217: “What's Wrong with %Error in Junction Temperature,” April 2006

8218: “How to Extend a Thermal - RC - Network Model,” April 2006

8219: “How to Generate Square Wave, Constant Duty Cycle, Thermal Transient Response Curves,” April 2006

8220: “How To Use Thermal Data Found in Data Sheets,” April 2006

8221: “Thermal RC Ladder Networks,” April 2006

8222: “Predicting the Effect of Circuit Boards on Semiconductor Package Thermal Performance,” April 2006

8223: “Predicting Thermal Runaway,” April 2006

8402: “Thermal Considerations for the NCS5650”, June 2009

8432: “Thermal Consideration for a 4x4 mm QFN”, December 2009

Thermal-Related Applications Notes available at

http://www.onsemi.com/pub/Collateral/ANxxxx-D.PDF

Page 246: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology245

Thermal Test Standards

1. EIA/JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method

Environmental Conditions - Natural Convection (Still Air), Electronic Industries

Alliance, December 1995

2. EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method

Environmental Conditions - Forced Convection (Moving Air), Electronic Industries

Alliance, March 1999

3. EIA/JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method

Environmental Conditions - Junction-to-Board, Electronic Industries Alliance,

October 1999

4. EIA/JEDEC Standard JESD51-12, Guidelines for Reporting and Using

Electronic Package Thermal Information - Electronic Industries Alliance,

May 2005

5. JEDEC Standards No. 24-3, 24-4, 51-1, Electronic Industries Alliance, 1990

6. MIL-STD-883E, Method 1012.1, U.S. Department of Defense, 31 December 1996

Page 247: Semiconductor Thermal Design

Semiconductor Device Thermal Characterization

and System Analysis (RPS) April 2010 Corporate R&D : Packaging Technology246

1. “Two-Dimensional Axisymmetric ANSYS® Simulation for Two-Parameter Thermal Models of Semiconductor Packages,” 7th International ANSYS Conference & Exhibition, May 1996, R.P. Stout & R.L. Coronado

2. “End User's Method for Estimating Junction Temperatures Due to Interactions of Other Dominant Heat Sources in Close Proximity to the Device in Question,” ITHERM, May 1996, D.T. Billings & R.P. Stout

3. “Evaluation of Isothermal and Isoflux Natural Convection Coefficient Correlations for Utilization in Electronic Package Level Thermal Analysis,” 13th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, January 1997, B.A. Zahn and R.P. Stout

4. "Electrical Package Thermal Response Prediction to Power Surge", ITHERM, May 2000, Y.L. Xu, R.P. Stout, D.T. Billings

5. “Accuracy and Time Resolution in Thermal Transient Finite Element Analysis,” ANSYS 2002 Conference & Exhibition, April 2002, R.P. Stout & D.T. Billings

6. “Minimizing Scatter in Experimental Data Sets,” ITHERM 2002 (Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems), June 2002, R.P. Stout

7. “Combining Experiment and FEA into One, in Device Characterization,” ITHERM 2002 (Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems), June 2002, R.P. Stout, D.T. Billings

8. “A Two-Port Analytical Board Model,” ITHERM 2002 (Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems), June 2002, R.P. Stout

9. “On the Treatment of Circuit Boards as Thermal Two-Ports,” InterPack2003, July 2003, R.P. Stout

10.“A Conjugate Numerical-RC Network Prediction of the Transient Thermal Response of a Power Amplifier Module in Handheld Telecommunication,” InterPACK 2005, July 2005, T.Y. Lee, V.A. Chiriac, R.P. Stout

11.“Part 1:Linear Superposition Speeds Thermal Modeling,” Power Electronics Technology, January 2007, R.P. Stout

Related Papers by Stout, et al

12.“Part 2:Linear Superposition Speeds Thermal Modeling,” Power Electronics Technology, February 2007, R.P. Stout

13.“Power Electronics System Thermal Design: Linear Superposition,” IEEE Expert Now on-line tutorial <http://ieeexplore.ieee.org/articleSale/modulesabstract.jsp?mdnumber=EW1054>, February 2007, Roger Stout

14.“Power Electronics System Thermal Design: Thermal Runaway,” IEEE Expert Now on-line tutorial <http://ieeexplore.ieee.org/articleSale/modulesabstract.jsp?mdnumber=EW1055>, February 2007, Roger Stout

15.“Using Linear Superposition to Understand the True Meaning of Theta-JA,” 12th Annual Automotive Electronics Council Reliability Workshop, May 2007, R.P. Stout

16.“Using Linear Superposition to Solve Multiple Heat Source Transient Thermal Problems,” InterPACK 2007, July 2007, D.T. Billings, R.P. Stout

17.“Linear Superposition and the True Meaning of Theta-JA,” 1-hr Seminar at 2007 Power Electronics Technology Exhibition and Conference, October 2007, R.P. Stout

18.“Thermal Performance of a Monolithic Thin-Shell Concrete Dome,” ASME Heat Transfer Conference, July 2007, R.P. Stout

19.“Beyond the Datasheet: Demystifying Thermal Runaway,” Power Electronics Technology, November 2007, R.P. Stout

20.“The Datasheet is Not Your Mother” (Executive Viewpoint article for) Power Electronics Technology, February 2008, R.P. Stout

21.“Psi or Theta: Which One Should You Choose?” Power Electronics Technology, March 2008, R.P. Stout

22.“Don’t Be Misled By Power Device Specs” Power Electronics Technology, May 2008, R.P. Stout

23.“Reliability of NLDMOS Transistors Subjected to Repetitive Power Pulses,” IEEE International Reliability Physics Symposium, April 2008, Poster Session paper, Chris Kendrick, Roger Stout, and Michael Cook