Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock Slide 1

Spezielle Anwendungen des VLSI – Entwurfs

Applied VLSI design

Course and contest

Results of Phase <1>

<Ayad Mostafa, Florian Grützmacher>

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock Slide 2

Facts to present

Design and architecture:

Chosen Adder: Ripple Carry Adder

- works

- expected speed:slow

Chosen Multiplier: Booth-Wallace

- doesn’t work yet!

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock Slide 3

Facts to present

Figures to be given (with units):

• Facts involve your_design.vhd with Ripple-Carry-Adder but without a multiplier

Mandatory values for FGPA

Frequency f 229,253 MHz

Area A(# of LUT-FF Pairs)

1068

# Pipeline Stages 1

Metric 41,6

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock Slide 4

Flow for the presentation

Recommended flow for reasoning:

1. Observations: – A very fast adder

2. Discuss results– Virtex 6 FPGA have a Carry-Path

– Ripple-Carry may be optimized to this path

– -> very fast adder

– BUT: on ST65 probably slow because of no carry-path optimization

3. Outlook on next steps/optimizations– Implementing another adder like CLA

– Implementing a multiplier