A Survey of Spin Transfer Torque Magnetic Random Access Memory

Arielle Walker

EE 451 VLSI Design

Final Report

12/5/2014

Arielle Walker

Table of Contents

Introduction…………………………………………………..…………………………….………..……….…….page 3

STT-MRAM: A Universal Memory…………………………………………......…………………..........page 3

MRAM and MTJ Physics…….…………………………….......................................………………..page 5

MTJ Electrical Properties…………..………………………………………………………....……………….page 7

Spin Transfer Torque Switching…………………………………………………..………………..……….page 10

MRAM and CMOS Compatibility…………………………………………………………………….....….page 12

Recent Research Reviews

a. 16 kB STT-MRAM Design With Low Power and High Reliability……….…….page 14

b. Optimization Scheme to Minimize Resistance Distribution ……………..……page 19

Conclusion…………………………………………………………………….…………………………………......page 21

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Introduction

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a novel non-volatile

memory device, without the typical degradation seen in Flash memory, which combines the speed of

SRAM, the memory density of DRAM and overall high performance, making it a perfect candidate for a

universal memory system. According to 2007 Physics Nobel Prize Winner, Albert Fert, spin transfer

torque combined with MRAM is an innovating and exciting technology still in the early stages of

research, but with the potential for a future Nobel Prize award. While the physics of STT-MRAM are fully

compatible with CMOS, it adds extra design and layout constraints which make manufacturability a

current research challenge.

First a comparison of STT-MRAM to current available memory technologies will be presented.

Next, the physics of Magnetic Random Access Memory (MRAM) and its building blocks, the Magnetic

Tunnel Junction (MTJ) will be discussed, including electrical properties. Following will be the kinetics of

Spin-Transfer Torque (STT) and its application in the MRAM system. To wrap up a complete

understanding of the STT-MRAM model, a passage on the integration of STT-MRAM with CMOS

technology will follow. Finally, new research from early 2014 on improvements to this emerging

technology will be highlighted.

Spin Transfer Torque Magnetic Random Access Memory: A

Universal Memory

There are currently three commonly used types of memory, all of which collectively comprise a

standard computer. SRAM has excellent read/write speeds, but a large cell size of 6 or more transistors,

meaning low memory density. It is typically used in embedded applications, such as cache memory.

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DRAM has high memory density, usually a single transistor with a storage capacitor, but has high power

consumption through charge leaking off of the capacitor, requiring a frequent refresh cycle on the ~ms

range. It is typically used as the main memory system for a computer. Unlike the previous two

memories (SRAM and DRAM), Flash memory is non-volatile, meaning it can retain information even

through a power outage and does not require constant power. However, it has very low endurance,

~100,000 cycles, and although it has high density and fast read access times, it has very slow write

speeds. Flash memory is commonly used for mobile applications.

STT-MRAM combines the advantages of all three memory types, making it an ideal universal

memory, unifying and consolidating memory applications to improve system performance and

reliability, which consequently lowers cost and power consumption.

A complete comparison of STT-MRAM to different memory technologies can be seen in figure 1

below. This figure is from 2010 and may not accurately represent the most up to date research results

for the emerging technologies, including STT-MRAM, but it will give a rough idea as to how optimal STT-

MRAM is. It is the only available memory type which is “green” (for optimal) across the board.

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Figure 1: Comparison of memory technologies (source: Wolf et al [6])

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MRAM and MTJ Physics

MRAM is a unique technology, existing since the 1970s, which utilizes magnetic field direction to

store binary information (data) and reads it by exploiting magnetoresitive properties, described in detail

below. The MRAM cell is comprised of a Magnetic Tunnel Junction (MTJ) device, which consists of two

ferromagnetic thin films separated by a thinner insulating layer, optimally MgO according to most recent

research. One of the ferromagnetic layers is “fixed”, meaning the magnetic field constantly stays in the

same direction. This is achieved by keeping this layer sufficiently thick, or by putting it in contact with an

anti-ferromagnetic material, which will prevent it from re-orienting. The other ferromagnetic layer is

“free” and allowed to re-orient its direction. When the two ferromagnetic layers are in the same

direction, it is known as parallel configuration and the MTJ is in a low resistive state (with resistance RP).

When the two ferromagnetic layers are in opposing directions, it is referred to as anti-parallel

configuration, and the MTJ is in a high resistive state (with resistance RAP). A picture of the two possible

orientation follows in figure 2.

Figure 2: MTJ Magnetic Field Orientations Source ([1])

In MTJs, and other ferromagnetic materials, instead of the typical electronic device where

information processing is controlled by the flow of charge, information is stored by forcing the spin

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alignment of many electrons. In any magnetic field, only spin orientations parallel or antiparallel are

possible.

The first ferromagnetic layer of the MTJ acts as a polarizer. Although the current coming from

the rest of the circuit has a net flow of electrons in a certain direction (ie. the current), each individual

electron has its own spin orientation, which is a quantum mechanical property and allowed in only two

directions, “up” or “down”. Passing through the first ferromagnetic film aligns the spin of all electrons to

the same direction, creating a spin-polarized current. Then, although the MgO layer is insulating, since

the MTJ device is on the nanoscale, electrons are able to quantum-mechanically tunnel through,

allowing the spin-polarized current to pass to the second magnetic layer. The second ferrous layer acts

as a spin-filter. In the parallel case, it is clear that since the magnetic fields are aligned, the spins allowed

by each ferrous layer are also aligned. Thus, the most current can pass through, hence being referred to

as a low-resistive state, RP. In the anti-parallel case, the filter of the second ferrous film is opposing the

first, and thus very little electrons (current) can get through. Only the electrons whose spin has

precessed due to dephasing to the antiparallel direction can pass, which is a small amount. This clearly

refers to the high resistive state, RAP. The entire process is analogous to a light polarizing filter system

typically seen in an elementary optics class. An illustration of a spin-polarizer (first ferrous layer) and

spin-filter (second ferrous layer) is shown below in figure 3, to demonstrate the difference in current

going through, which directly correlates to the changing resistance of the MTJ structure via ohm’s law.

Combined, the spin-polarizer and spin-filter are known as a spin-valve operation. They are the defining

characteristics of an MTJ.

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Figure 3: Spin Polarizer/Spin Filter (Source: Modified from [1])

MTJ Electrical Properties

An important property of the MTJ is the Tunnel Magnetoresistance (TMR). The TMR is the

efficiency of the spin-valve operation in the MTJ. It is defined as:

TMR=R AP−RPRP

(Equation 1)

The higher the TMR is, the more efficient the MTJ is operating as a switch. The resistance of the tunnel

barrier, known as the resistance area (RA) product, is based on Rp, the low resistive parallel state

resistance, and characterizes the resistivity of the tunnel barrier. To optimize the TMR ratio using STT-

MRAM technologies, a TMR of several hundred percent can be achieved with a RA between 5 and 30 uΩ

* μm2. In general, the resistance of an MTJ is large (~kΩ) and there is a high signal voltage output (∆V ~

hundreds of mV) allowing a high-speed read operation.

Another important characteristic of the MTJ is the critical switching currents, that is, the

minimum currents necessary to change from RAP ¿ RP and vice versa. For a typical MJT, these critical

switching currents are somewhat asymmetric and the asymmetry is proportional to and increases

linearly with the TMR. This suggests the anti-parallel configuration is in a lower energy state than the

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parallel case and is highly undesirable since it is easier to switch to the antiparallel state. The use of STT-

MRAM reduces the asymmetric current ratio so it is nearly negligible, making it just as easy to switch to

either state.

It should be noted that the critical currents described above apply to the write operation, since

they change the data on the MJT. During a read operation, it is necessary for the current to be

significantly lower than the critical switching current for writing. This is to prevent potential read

disturbance, when the read current is larger than the critical current, Ic, and hence data is accidentally

written when it is meant to only be retrieved.

Since in MTJ the magneto-resistance properties are being exploited, it is common to see an R-V

curve, where the resistance is plotted as a function of increase or decreasing bias-voltage. There is one

phenomenon, called the zero-bias anomaly, where for decreasing bias voltage the resistance spikes up

at 0V. This is illustrated on the following resistance hysteresis figure of an MTJ. The asymmetrical

properties for a standard MRAM MTJ are shown below in figure 4.

Figure 4: Resistance Hysteresis of MTJ. Blue is from Parallel to Anti-Parallel. Red is from AP to P. Source [1]

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R-V results for a STT-MRAM are much more symmetrical, as mentioned above. A typical

resistance hysteresis is shown below in figure 5 measuring the resistance as a function of (a) magnetic

field, and (b) input current. Additionally the figure shows the impact of different insulating materials and

how it affects the TMR. The top figure uses Al2O3 and the bottom uses MgO. There is a significant

increase in the TMR when using MgO.

Figure 5: Switching Mechanisms in different STT-MRAM Devices (Source [6])

The intrinsic current density JCO required for current driven magnetization in a MTJ can be

referred to as:

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JCO=2eα M s t f (H+H k+2π M s)

ηℏEquation 2

H is the field applied along the easy access, Ms and tf are the magnetization and thickness of the

free layer respectively, α is the damping constant, Hk is the anisotropy field, and η is the spin transfer

efficiency (a function of current polarity, polarization, and the relative angle between the free and

pinned layer). This equation suggests when the current J is greater than JCO, the magnetization enters a

stable precessional state or a complete reversal occurs. Hence, for a writing operation the current must

be above the critical threshold current, and for a reading operation the current must be below.

In STT-MRAM the current passes directly through the MJT, so a much lower switching current is

needed than a traditional MRAM cell. This leads to a significantly simpler and smaller cell architecture,

lower manufacturing costs, and highly improved scalability. A conventional MRAM cell is compared to

an STT-MRAM cell below in figure 6.

Figure 6: Comparison of memory cell architecture Source: [5]

Spin Transfer Torque Switching

Spin Transfer Torque (STT) Switching is one of the most optimal ways to switch magnetic states,

as highlighted by the desirable properties above. When referring to spin of an electron, it is clear that

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some angular momentum is involved. When the electrons enter the second ferrous layer, the filter

layer, the magnet necessarily absorbs a portion of the spin angular momentum that is carried by the

electron spins. That change in angular momentum is the result of a net torque on the magnetic layer,

known as the spin-transfer torque. The actual value of the torque can be computed by considering the

net change in spin current before and after the interaction (IE, what is the spin current on the polarizer

vs. the filter). Any time a spin-polarized current interacts with a ferromagnetic layer and consequently

undergoes spin filtering, some spin-transfer torque is applied to the magnetic layer.

There are three major ways the STT switch occurs, (1) precessional, (2) thermally activated, and

(3) dynamic reversal. Precessional switching occurs on a nanosecond timescale, and requires a

switching current several times greater than the instability current. Dynamic switching occurs from

around 3-10ns at intermediate current pulses, corresponding to the operating speed of practical STT-

MRAM. Thermally activated switching is on long current pulses >10ns. A picture of the three types of

switching is shown in figure 7 below.

Figure 7: STT switching current density as a function of current pulse width. Source [5]

One downfall of STT switching is that since the devices are very small, and write currents are

potentially large, there can be very high power density during the write operation. This can lead to

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heating of the device, potentially causing hotspots (weaker spots in the insulating MgO barrier) or

pinholes (direct contact between the magnetic layers). This non-uniform heating can affect the spin-

polarization efficiency of the MTJ. Additionally, since tunneling is a rather inefficient electronic transport

process, Joule heating is a potential problem when large portions of energy are consumed during STT-

induced magnetization reversal.

MRAM and CMOS Integration

The actual data stored on an STT-MRAM’s MTJ cell still comes from a MOSFET, as they are

integrated in a standard CMOS circuit, albeit with some geometrical and manufacturing restrictions.

There are several ways to connect the FET to the MTJ.

One MOSFET transistor can supply to many MTJs in parallel, in a “shared” configuration,

allowing the access FET additional size and higher write current while maintaining a high memory

density. The downside is the parallel configuration allows for many parasitic current paths, meaning a

larger access device is needed and some cells could accidentally be flipped from the addition of these

parasitic currents. Additionally the parasitic paths lower the TMR, which is undesirable since that is a

measure of the effectiveness of the MTJ spin-valve.

Another configuration uses one MOSFET to supply to many MTJs in series, in a “stacked”

configuration. Each MTJ in this case would need to have a sufficiently different critical writing current for

functionality and the read/write cell would require multiple cycles.

There is also the option of 1-FET to 1-MTJ, however because of size constraints this is limited to

a 256 cells per bit line. Otherwise, most of the complications seen in the shared and stacked

configurations are avoided, although the additional cost is obvious.

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A write circuit consists of a source going through a FET, and the output writing current, IWRITE,

feeding into the MTJ where it can switch its configuration via STT. IWRITE is larger than the switch

threshold current IC.

A reading circuit is somewhat more complicated, comprising of a sensing and reference cell. In

this case, IREAD is smaller than the threshold current and it is sent through an MTJ to detect the resistance

difference between RAP and RP, and then compared with IREAD,REF going through the reference cell.

A figure comprising the structure of both the Writing (a) and Storing (B) cells are shown in figure

8, below.

Figure 8: Writing (A) and Reading (B) Circuits for STT-MRAM. Source [7]

There are three main structures for the STT-MRAM memory architecture, as shown below in

figure 9. The storage cells will all be compared to a reference cell, via the sense amplifier. In the case of

9(a), one storage bit is represented by several complementary MTJs. Although this provides fast speed

and good sensing reliability, both complementary MTJs need a driving circuit, resulting in area overhead

and low power-efficiency during the writing operation. In the case of 9(b), each storage bit is

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represented by one MTJ and there is one reference cell for every storage cell. In this structure there is

low power, but very clearly also large cell array to accommodate each bit. In the case of 9(c), each

storage bit is represented by one MTJ, and every column has one reference cell. This configuration

reduces cell array area, but the sensing reliability is limited because of parasitic resistances in the

storage cell and asymmetric reference cell branch.

Figure 9: Block Diagram of STT-MRAM with 3 types of cell arrays. Source [7].

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16 kB STT-MRAM Design With Low Power and High

Reliability [7]

There are three major areas of concern regarding STT-MRAM. The first area of concern, found in

the standard sensing (reading) STT-MRAM circuit outlined above, is the potential for thermal activation

to switch the MTJ state, relating to the reliability. Second, the traditional write cell requires a high

power supply voltage to ensure the desired data is stored correctly, leading to high writing power

consumption. Remember, the magnetic fields switch due to the spin-transfer torque of electrons. This

torque may need to be sufficiently high and the best way to achieve it is to supply a stronger current (i.e.

more electrons). Finally STT-MRAM can occasionally encounter stochastic switching behavior, again

providing low reliability.

To combat all of these issues a 16kB STT-MRAM design was successfully developed which

improved reliability and reduced power consumption. First, three small circuits were designed and

simulated, a writing circuit with low supply voltage, a self-enable switching circuit, and a fore-placed SA

scheme for the read circuit.

Writing Circuit with Low Supply Voltage

A write driver provides a bidirectional current passing through the MTJ. Depending on the

direction of the writing current, the free layer magnetization can change to be either parallel, or anti-

parallel, storing either “1” or “0”.

Looking at the conventional STT-MRAM writing circuit, below in figure 10, the IWRITE value

depends on the transistor N1-N4 resistance and the supply voltage at the end of the writing branch.

Additionally, a low IWRITE, would require a longer switching time to ensure the data be stored correctly.

With the current circuit, in order to increase IWRITE it is necessary to decrease the resistance and/or

increase the supply voltage value of the writing branch. Therefore, the column selected combination

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should be chosen to have a lower resistance and the value of Vdda should increase beyond Vdd. This

would increase the power consumption significantly since IWRITE has increased.

Instead, to decrease power consumption, a circuit with a lower power supply voltage is

proposed, as shown in figure 11. The different column selected gates are used in the writing and reading

operations, isolating writing from reading and implement selecting one column. This reduces the

number of transistors, and therefore the resistance, on the writing branch. In addition, the critical

current density of this model is much lower, allowing a write current of only ~100uA in a small MTJ. This

circuit provides nearly identical switching times, but the power supply voltage is equal to Vdd (instead of

greater than it), significantly reducing the power consumption. It was found that this writing circuit with

low power supply effectively reduced the power consumption by reducing the switching energy of a

conventional writing circuit from 6.0pJ/bit to 4.0pJ/bit.

Figure 10: Conventional STT writing circuit with high supply voltage. Source [7]

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Figure 11: Writing circuit with low supply voltage. Source [7]

Self-Enable Switching Circuit

The self-enable switching circuit was intended to further reduce write power consumption and

improve STT-MRAM reliability. There is a possibility that if the STT switching pulse is significantly low

(sub-nanoscale), occasionally some input data would not be stored correctly. Typically to combat this,

the writing pulse duration is extended or IWRITE is increased, which either results in slow speed, high

power consumption, short lifetime, or a combination of the above. Instead, the self-enable switching

circuit will overcome the power and reliability problems by taking advantage of the stochastic switching

sometimes seen in STT-MRAM.

In the improved self-enable switching circuit, the MTJ state can be switches after just one short

write pulse, which includes both switching and sensing operations. When the external W-enable STT-

MRAM is active, the SA detects the MTJ state and outputs the logic output data under the control of the

short periodic duration sense data. Then that output is compared with the input data, and a self-enable

logic level is obtained (1 when data is the different, 0 when the same). In additional, the MTJ will not

switch unless the sensing signals indicates the input and output data differ. This reduces the cycles going

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through MTJ, thereby increasing the lifespan. The timing diagram of a conventional STT-MRAM circuit,

compared to the self-enable switching circuit are compared in figure 12.

Figure 12: Timing Diagram Source [7]

The self-enable switching circuit succeeded in saving even more energy, reducing the switching energy

to only 1.6pJ/bit, and it also improved the lifetime of the MTJ.

Reading Circuit with fore-placed SA

Some research suggests the sensing operation suffers from high sensitive to process voltage

temperature variations. To improve the reliability of the reading circuit, a reading circuit with the

column selected transistor moved to the post of SA, and the output of SA to the column selected

transistor. The reduction of transistor number in sensing circuit decreased the sensitivity to process

variations. This increases the area overhead, but since this circuit is shared by many elements, it is still

desirable. The reading circuit with fore-placed SA improved the robustness of process variation.

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Optimization Scheme to Minimize Ref. Resistance

Distribution of STT-MRAM [9]

As MJTs continue to scale down, there are continual concerns regarding process variation and

the decreasing power supply voltage, posing a thread for the STT-MRAM sensing margin, the voltage

difference between the bit line voltage during the read operation and the reference of the sense

amplifier subtracting the offset voltage and noise. One suggested solution was to employ differential

sensing architecture, which double the sensing margin but reduces the memory density. Another

concern mentioned earlier is that of read disturbance, when the current is higher than the minimum

critical write current, and thus data is written when it is meant to only be retrieved (read). The sensing

margin in STT-MRAM can be expressed as:

SensingMargin=IREAD∗¿RMTJ−RREF∨¿ Equation 3

Where Iread is the reading current, Rmtj is the resistance of the MTJ, Either Rp or Rap, depending on parallel

or antiparallel states, and Rref is the equivalent resistance of the reference circuit. Low TMR ratio, low

sensing current, and distribution of resistance in both resistive states can further reduce the sensing

margin.

Conventionally two reference cells in parallel per row are used to generate a reference voltage,

reducing the sensing margin ever further because of the array cell resistance distribution and reference

cell resistance distribution. To maximize the sensing margin and increase the read reliability, one

suggestion is to reduce the distribution of the resistance of the reference cells. A mergence reference

line method is something used, however it consumes high power on the reference circuitry during the

read operation.

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Instead, a reference circuits proposed to increase the sensing margin is shown below in figure

13. This reference circuit architecture maximizes the sensing margin by averaging the resistance of

reference cells from one or two columns of the reference array from one or two memory banks, using a

folding technique.

Figure 13: Reference Circuit Architecture. Source [9]

With this architecture, two banks of the same dimension share sense amplifiers. Each bank has a

dedicated column of reference cells, and the two reference columns are connected to the reference

node of the sense amplifier through switches. If the number of cells in the reference column equals 22n,

the averaged resistance of that column of cells will be used as the equivalent resistance. These switches

turn off the switch and connect the equivalent sense amplifier to sense the cells in bank 1 or bank 2

respectively. Otherwise, if the number of cells in the reference column equals 22n-1, the averaged

resistance of both columns will be used as the equivalent resistance, asserting both S1 and S2 and

sensing cells in both banks 1 and 2.

The simulation results from this proposed optimized sensing scheme using a folding technique

to minimize the reference resistance distribution significantly reduced the resistance distribution effect

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and increased the reliability of readout data. Additional benefits include increased signal to noise ratio

and reduced design complexity.

Conclusion

Spin-Transfer Torque Magnetic-RAM is a promising emerging technology. Although in its

infancy, preliminary results are promising. The most challenging aspects ahead are being thoroughly

researched and primarily include constraints manufacturability (i.e., process variation). Overall, STT-

MRAM has the potential to be the first truly universal memory source, providing the benefits of all types

of memory in one device. This technology can decrease overall power consumption, reduce cost, and

improve reliability. Currently the largest commercially made STT-MRAM device is 64 Mb and it is already

being incorporated as cache memory. Only the future can tell how this research will progress.

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References

Background Information

1) Dorrance, R.W., “Modeling and Design of STT-MRAMs”, A Thesis from UCLA, 2011. 2) Fert, A., “Will Spin Transfer Torque Research be awarded a Nobel Prize? “, Youtube

Video: https://www.youtube.com/watch?v=BqBcxbW_Iqo&list=PL1ECB9CD585AC7400&index=1, April 2010.

3) Guchang, H., Jiancheng, H., et al, “Spin transfer torque (STT) MRAM and beyond”, Magnetics Symposium 2014 - Celebrating 50th Anniversary of IEEE Magnetics Society (MSSC50), 29 September 2014.

4) Ralph, D.C., Stiles, D.C, “Spin Transfer Torques”, Journal of Magnetism and Magnetic Materials, Feb 2009.

5) Huai, Y., “Spin-Transfer Torque MRAM (STT-MRAM): Challenges and Prospects”, AAPPS Bulletin, Dec. 2008.

6) Wolf, S.A, et al, “The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory”, Proceedings of IEEE, December 2010.

Special Topics7) Zhang, L., et al, “A 16 Kb Spin-Transfer Torque Ransom Access Memory with Self-Enable

Switching and Pre-charge Sensing Schemes”, IEEE Transactions of Magnetics, April 2014.8) Kim, K., et al, “A Split-Path Sensing circuit for Spin Torque Transfer MRAM”, IEEE Transactions on

Circuits and Systems –II, March 2014.9) Huang, K., et al, “Optimization Scheme to Minimize Reference Resistance Distribution of Spin-

Transfer Torque MRAM”, IEE Transactions on Very Large Scale Integration Systems, May 2014.

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