1

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N. Dehdashti, C.-W. Lee, A.Kranti, R. Yan,

I. Ferain, R. Yu, P. Razavi, JP Colinge

Tyndall National Institute

University College Cork, Ireland

Sub-60mV/dec Subthreshold Slope in Junctionless

Nanowire Transistors

Sub-60mV/dec Subthreshold Slope in Junctionless

Nanowire Transistors

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• Junctionless transistor

•Conduction mechanisms

•Drain electric field

• Subthreshold slope measurements

• Simulations

•Conclusions

OUTLINE

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GateDrain

Source

GateDrain

Source

Source Drain

DrainSourceN+ PolySi Gate

P+ PolySi Gate

B

C

A

N+ Silicon

P+ Silicon

GateDrain

Source

GateDrain

Source

Source Drain

DrainSourceN+ PolySi Gate

P+ PolySi Gate

B

C

A

N+ Silicon

P+ Silicon

A: 3D view of a junctionless transistor

B: cross section of an N-channel device

C: cross section of a P-channel device

Anantomy of Junctionless Transistor

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BOX

TEM Cross section

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• Junctionless transistor

•Conduction mechanisms

•Drain electric field

• Subthreshold slope measurements

• Simulations

•Conclusions

OUTLINE

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GateSource

Drain

The cross section must be small enough for channel region to be depleted on carriers: Electrostatic Pinchoff

Electrostatic Pinchoff

Wsi

tsi

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Increasing Gate Voltage

Below VTHSlightly above VTH

Higher VG Depletion gone

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• Junctionless transistor

•Conduction mechanisms

•Drain electric field

• Subthreshold slope measurements

• Simulations

•Conclusions

OUTLINE

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VD=50mVVD=200mV

VD=400mVVD=600mV

Increasing Drain Voltage

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The high-field

region is

in the drain,

not in the

channel

region

Drain electric field

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• Junctionless transistor

•Conduction mechanisms

•Drain electric field

• Subthreshold slope measurements

• Simulations

•Conclusions

OUTLINE

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-3.0 -2.5 -2.0 -1.5 -1.010

-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

Gate Voltage (V)

Drain Current (A)

Vth=-1.5V

JL; W=50nm

Vsd=1.50V

Vsd=1.75V

Vsd=2.00V

Vsd=2.25V

Vsd=2.50V

Vsd=2.75V

Vsd=3.00V

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Vbg=0

Gate Voltage (V)

Drain Current (A)

Waf 3;C1; 83

IM; W=50nm

Vsd=3.00V

Vsd=3.25V

Vsd=3.50V

Vsd=3.75V

Vsd=4.00V

Vsd=4.25V

Vsd=4.50V

Vsd=4.75V

Vsd=5.00V

Subthreshold slope

”Regular” inversion-

mode trigate FETJunctionless trigate FET

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0.0 0.4 0.8 1.2 1.610

-14

10-12

10-10

10-8

10-6

Gate Voltage (V)

Drain Current (A

)

VDS=3.0V~5.0V

Step=0.5V

”Regular” inversion-mode trigate FET

VD=4V

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-3.0 -2.5 -2.0 -1.5 -1.010

-14

10-12

10-10

10-8

10-6

Gate Voltage (V)

Drain Curren

t (A

)

VDS=1.5V~2.25V

Step=0.25V

Junctionless trigate FET

VD=1.75V

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• Junctionless transistor

•Conduction mechanisms

•Drain electric field

• Subthreshold slope measurements

• Simulations

•Conclusions

OUTLINE

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Device simulation (ATLAS)

BOX

Gate

Source

DrainLgate

Wsi

tsiA-A’

BOX

Gate

Source

DrainLgate

Wsi

tsiA-A’

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0.0 0.1 0.2 0.3 0.4 0.5 0.6

0.0

5.0x105

1.0x106

1.5x106

2.0x106

Cutline from source to drain (µµµµm)

Electric field (V/cm)

Junctionless

Inversion-mode

Electric field

W=20nm Tsi=5nm, Tox=10nm, L=200nm

Source Drain

Electric field

VDS=2.2V, VGS=VTH-200mV

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Junctionless

Nd=1e19:

Impact ionization is

in the drain

Inversion-mode

Na=2e18:

Impact ionization

is in the channel

region

Impact gen rate_ VDS=2.2V, VGS=0V,

20x5nm_L200

Impact Ionization Rate

Drain

Gate

Drain

Gate

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0.0 0.1 0.2 0.3 0.4 0.5 0.6

8.0

6.0

4.0

0.0

x103

2.0

Drain

Distance along x-direction (µµµµm)

Electron Temperature (K)

Junctionless

Inversion-mode

Source

Electron Temperature

VDS=2.2V, VGS=VTH-200mV

dxxTMe

)()1( ∫=− α

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0.0 0.1 0.2 0.3 0.4 0.5 0.6

x1026

0.0

0.5

1.0

1.5

Source Drain

Distance along x-direction (µµµµm)

Junctionless

Inversion-mode

Impact Ioniczaton G

erneration Rate (s-1cm

-3)

2.0

VDS=2.2V, VGS=VTH-200mV

dxxTMe

)()1( ∫=− α

Impact Ionization Rate

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• Peak electric field is in the drain itself

• Wider high-field region accelerates

electrons to higher impact ionization

rates

• Bandgap narrowing in highly doped silicon

70 to 150 meV for ND=1e19-5e19 cm-3

• Sub-60mV slope observed at VDS=1.75V

instead of 4V in regular device

Conclusions