2008.09EDA

ISE ModelsimISE 9--

- ISEImplement 3TranslateMapPlace & Route

- Xilinx XilinxPLD

- 5CLKRESETLAP_LOADMODESRTSTPHDLEDIFUCF 1Source Tabstopwatch 2ProjectNew SourceImplementation Constraints File 3 stopwatch.ucf Next 4stopwatchUCFUCFNextFinish

- 1Source Tabstopwatch 2ProcessesImplement Design 3PropertiesProcesses Properties 49.1,Advanced

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- 5Post-Map Static Timing Report Properties 6Verbose Report 7Post-Place & Route Static Timing Report Properties 8Verbose Report 9Place & Route Properties 109.2Place & Route Effort Level (Overall)High 11OKProcess Properties

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- HDLVerilogVHDLHDLHDL

- 1Source Tablcd_cntrl_inst ; 2New Partition 3timer_state 4timer_inst ISE9.1i

- RoutingRoutingPlacementSysnthesisPartition Properties

- UCF 1Source TabStopwatch 2ProcessesUser Constraints 3Create Timing Constraints9.4

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- ISEISEimplementImplement DesignNGDBuild 1NGD 2 3UCF

- Create Timing Constraints 1UCF 2 1NGDNative Generic Database NGDNCD (Native Circuit Description) 2UCF (User Constraint File) NGDUCFUCF

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- 9.5UCFNGDBuildUCFNGDNGDstopwatch.ngd stopwatch.ucf PERIODOFFSET INOFFSET OUTTIMEGRP OFFSET INUCF9.6

- 1CLK 2Specify Time 3Time7.0

- 4ns 5 Time60 6ps 7OK50% 8Pad to Setup6nsGlobal OFFSET IN 9Clock to Pad 9.738nsGlobal OFFSET OUT

- 10SoucesPort 11Port NameSF_D 12ShiftSF_D 13Group Namedisplay_grpCreate Group 14Select Group

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-15Clock to PadClock to Pad16Timing Requirement 3217Relative to Clock Pad NetCLK18OK19FileSavestopwatch.ucf20FileClose

- FloorplanNGDFloorplan UCFUCFNGDFloorplan ,Ram (DCMs), (GTs), BUFGs IOBFloorplanUCF

- 1Sourcesstopwatch 2+Implement Design 3+Translate 49.11Assign Package Pins Post-TranslateFloorplanEDIFAssign Package Pins 59.12Package

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- 6Processes Design Object 7Design Object, ALLIOs, LCD_

-89.13LOC LCD_E->AB4; LCD_RS->Y14; LCD_RW->W13

- 9Design Object LAP_LOAD T16 RESET U15 MODE T14 STRTSTOP T15 10FileSavestopwatch.ucf 11FileCloseFloorplan

- 1Sourcesstopwatch 2ProcessesMapRunMap 3Implement Design

- CLBsIOBs 1CLBIOB 2

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TranslationMap NGDBUILDMAP Development System Reference GuideISEHelp > Software Manuals, http://www.xilinx.com/support /sw_manuals /xilinx9/.

- 19.14TranslateMap

9.14

- 2Translate reportMap repor 39.15Warnings, ErrorsInformationDesign Summary

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- Post-Map Static Timing Report

- 50/50 50/50 50% 10ns20ns

- PERIOD 1Processes+Map 2Generate Post-Map Static Timing 39.16Analyze Post-Map Static Timing Report

- 49.17timing constraintTS_dcm_inst_CLKX_BUF

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- 88.0 12.0 5File Close

- PARPlace & Route 1 2 PAR

- PAR 1ProcessesPlace & Route 2+Place & Route 3Place & Route Report 9.2Pad ReportAsynchronous Delay Report

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PARPadRARDevelopment System Reference GuideISEHelp >Online Documentationhttp://www.xilinx.com/support /sw_manuals/xilinx9/.

- 9.18

-FPGA Editor FPGA EditorFPGAFPGAsFPGANCDNMCPCFPhysical ConstraintsFPGA 1 2 3 4BitGenbitstream 5Integrated Logic Analyzer (ILA)

-FPGA Editor FPGA 1+Place & RouteView/Edit Routed Design (FPGA Editor)2.19

-FPGA Editor 22.20FPGAAll Nets

-FPGA Editor 32.21clk_262144K ()

- Post Layout Timing Report 1Generate Post-Place & Route Static Timing 2Analyze Post-Place & Route Static Timing ReportTiming AnalyzerDesign SummaryTiming ConstraintTiming Analyzer

- stopwatch Post-Place & Route Static Timing Report 1Post-Map timing 80%90%post-layout30%40% 2Post-layout50/50

- 3 4Sources Timing ProcessesTiming Objects 5Timing Analyzer TS_DCM_INST_CLKFX_BUF Maximum Data PathFloorplan Implemented

- 69.22 View Overlays Toggle Simplified Actual Views

- 7 8File CloseFloorplan Implemented 9File ClosePost-Place & Route Static Timing report

-HDL HDLLCD_CNTRL_INST , 1SourcesLCD_CNTRL_INST 2HDL Verilog377564sf_d_temp =8b00111010; // [colon]sf_d_temp = 8b00101110; // [period] VHDL326514 sf_d_temp

-HDL 3 LCD_CNTRL_INST, File Save 4Sources, stopwatchProcesses Place & Route. 5Run9.23LCD_CNTRL _INST

-HDL

-HDL 6Design Summary, Synthesis Report, Partitions Report MAP Report, Guide Report Place and Route Report, Partition Status

- ModelsimXilinx ISE

- 1HDLVHDLVerilog NetGen 2VHDLVerilog HDL 3

- 1Sources tab(xc3s700A-4fg484)Properties 2ISEProject NavigaterModelSimISENC-Sim VCSNetgenISEProject NavigatorISE SimulatorVHDL/VerilogModelsim

-ModelSim Xilinx ISE MentorModelSimISEModelSim ISEXilinx ISE ModelSimISE

- Modelsim 1Sourcessources forPost-Route Simulation 2stopwatch_tb 3ProcessesModelSim Simulator+

- ModelSimModelSimISEmodelsim.exe.ModelSimprocessesModelSim locationEdit>PreferencesISE General+ISEIntegrated ToolsModel Tech Simulatormodelsim.exec:\modeltech_xe\win32xoem\modelsim.exe

- 4Simulate Post-Place & Route ModelPropertiesSimulation Model Properties9.24NetGen

- Advancedglobal setting Display Properties ModelSimISE Simulation Properties 9.25ModelSimHelpSimulation PropertiesSimulation Run Time2000nsOKProcess Properties

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- 5 Simulate Post-Place and Route ModelISENetGenISEModelSim 100HzDCM

- WaveISEsignalsignalstructure 1Signal/Object windowWave windows 2Signal/Object windowAdd > Wave >Selected Signals

- ModelSim6.0Undock1Structure/Instance windowuut+9.26Structure/InstanceStructure/Instance VerilogVHDL2Structure/InstanceEdit > Find

-3X_DCMEntity/Module4ModelSimX_DCMX_DCMsignal/objectsDCM5signal/objectsEdit > Find6CLKINExact7CLKINCLKINsignal/objectsWave8RSTCLKFXCLK0 LOCKEDsignal/objects

- CtrlAdd to Wave > Selected Signals

- ModelsimWaveDCM1Wave23WaveInsert > Divider4DCM Signals5CLKIN

- Tools > Options > Wave Preferences2OK69.27

- ModelsimModelsimWaveWave

- 1Restart Simulation2RestartModelSimrun 2000nsEnter32000nsWaveDCM

-

- DCMCLK050MhzCLKFX26MhzLOCKEDDCMLOCKEDDCM ModelsimCLK0

- 1Add > Cursor2LOCKEDCLK034Find Next TransitionCLK052000050Mhztest benchDCM CLK06CLKFX3846226Mhz

- ModelSimWave1WaveFile > Save Format2Save Formatwave.dodcm_signal_tim.do3Save waveFile > Load

-ISE ISE1SourcesPost-Route Simulation2test bench(stopwatch_tb)3ProcessesXilinx ISE+4Simulate Post-Place & Route ModelProperties5Simulation Model PropertiesNetGen

-6Advanced7ISE Simulator Properties9.28

-8Simulation PropertiesSimulation Run Time2000ns9OKProcess Properties

- ProcessesSimulate Post-Place and Route ModelProject NavigatorNetGenISE 100HzDCM

- ISEwaveformSim HierarchylDCM1Sim Hierarchyuut+29.29Sim HierarchyFindFind SignallockedOKDCM_SP_INST/LOCKEDOK

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- Sim HierarchyVHDL3Sim HierarchyLOCKEDwaveform4SIM HierarchyX_DCM_SPRST CLKFXCLK0CLKINCtrl

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- 1waveform9.30ISEISEwaveformwaveformRestart SimulationSim Consolerun 2000nsEnter2000nsSimulationDCM

- DCMCLK050Mhz,CLKFX26MhzLOCKEDDCM ISECLK0

-1waveAdd Measure2LOCKEDCLK0 3.31CLK0320ns50Mhztest benchDCM CLK09.31 4CLKFX38.5ns26Mhz

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1ISE2345ISE6Modelsim79