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2816 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 11, NOVEMBER 2006

New Generation of Predictive Technology Model forSub-45 nm Early Design Exploration

Wei Zhao, Student Member, IEEE, and Yu Cao, Member, IEEE

AbstractA predictive MOSFET model is critical for earlycircuit design research. To accurately predict the characteristicsof nanoscale CMOS, emerging physical effects, such as processvariations and correlations among model parameters, must beincluded. In this paper, a new generation of predictive technologymodel (PTM) is developed to accomplish this goal. Based onphysical models and early-stage silicon data, the PTM of bulkCMOS is successfully generated for 130- to 32-nm technologynodes, with an Leff of as low as 13 nm. The accuracy of PTMpredictions is comprehensively verified: The error ofIon is below10% for both n-channel MOS and p-channel MOS. By tuningonly ten primary parameters, the PTM can be easily customizedto cover a wide range of process uncertainties. Furthermore, thenew PTM correctly captures process sensitivities in the nanometerregime, particularly the interactions among Leff, Vth, mobility,and saturation velocity. A website has been established for therelease of PTM: http://www.eas.asu.edu/~ptm.

Index TermsMobility degradation, predictive modeling,process variation, saturation velocity, threshold voltage.

I. INTRODUCTION

THE relentless scaling of CMOS technology has acceler-ated in recent years and will arguably continue toward the

10-nm regime [1]. In the nanometer regime, physical factors

that previously had little or no impact on circuit performanceare now becoming increasingly significant. Particular exam-ples include process variations, transistor mobility degradation,and power consumption. These new effects pose dramaticchallenges to robust circuit design and system integration. Tocontinue the design success and make an impact on leadingproducts, advanced circuit design exploration must begin inparallel with early silicon development. This new design para-digm demands predictive MOSFET models that are reasonablyaccurate, scalable with main process and design knobs, andcapable of correctly capturing emerging physical effects.

To predict future technology characteristics, an intuitive ap-

proach would simply scale down the geometry and voltageparameters from an existing technology. For instance, based onthe current standard MOSFET model, Berkeley Short-ChannelIGFET Model 4 (BSIM4) [2], we can shrink the parametersof effective gate length Leff, equivalent electrical oxide thick-

Manuscript received May 3, 2006; revised August 15, 2006. This work wassupported in part by the MARCO Focus Center for Circuit and System Solutionand in part by the Materials, Structures, and Devices Focus Center. The reviewof this paper was arranged by Editor M. J. Deen.

The authorsare with the Department of Electrical Engineering, Arizona StateUniversity, Tempe, AZ 85287 USA (e-mail: [email protected]).

Color version of Figs. 38 are available at http://www.ieeexplore.ieee.org.Digital Object Identifier 10.1109/TED.2006.884077

Fig. 1. Simple method fails to predict the overall IV characteristics.

ness Toxe, threshold voltage Vth0, drain and source paratacticresistance Rdsw, and supply voltage Vdd to the target valueswhile keeping all the other parameters unchanged. However,as shown in Fig. 1, this approach is too simple to capture thebasic MOSFET behavior. In Fig. 1, the IV characteristicsof a preliminary 65-nm technology are predicted based on a

well-characterized 130-nm technology by scaling Leff, Tox,Vth0, Rdsw, and Vdd. Compared to experimental data, thissimple prediction underestimates the overall performance. Thisobservation matches the fact that during technology scaling,process developers will optimize many other aspects of thedevice beyond sole geometry scaling.

An improved predictive method was developed by the Berke-ley Predictive Technology Model (BPTM) [3]. Compared toBSIMs, the BPTM includes more physical parameters into theprediction. Their values are empirically fitted from publisheddata of early-stage experiments. Although the BPTM providesreasonable models for technology nodes from 180 to 45 nm,

its empirical nature constrains the physicality and scalability ofpredictions. As the model file for each technology node is inde-pendently fitted, the overall trend of scaling is not smoothenedby the BPTM (Fig. 2). Furthermore, intrinsic correlationsamong physical parameters are not sufficiently considered. Forinstance, the scaling ofVth0 not only requires the change ofchannel doping Nch but also impacts other physical parameters,such as mobility 0 and saturation velocity Vsat. Insufficientmodeling of these correlations limits the accuracy of predictionfor process sensitivities. As process variations become increas-ingly significant in 65-nm CMOS technology and below, it iscritical to include these correlations into future compact modelssuch that robust circuit design can be correctly guided [4].

0018-9383/$20.00 2006 IEEE

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ZHAO AND CAO: NEW GENERATION OF PREDICTIVE TECHNOLOGY MODEL FOR SUB-45 nm DESIGN EXPLORATION 2817

Fig. 2. BPTM is not smoothly scalable from 180- to 45-nm nodes.

In this paper, a new generation of PTM is developed toovercome these limitations. First, new physical models areintegrated into the predictive methodology to correctly capture

the correlations among model parameters, as presented inSection II. These models include Vth0 dependence on Nch,mobility degradation, and velocity overshoot. Second, basedon comprehensive studies of published data over various tech-nology generations, i.e., from 250- to 45-nm nodes, the scalingtrend of key physical parameters is concluded. By integratingthese results into PTM, both nominal and variational transistorperformances are predicted, following the traditional trend ofscaling. As demonstrated in Section III, smooth and accuratepredictions are obtained from 250- to 32-nm nodes, with Leffas low as 13 nm. Compared to various published data, the errorin prediction ofIV characteristics is less than 10%. PTM canalso be easily customized by adjusting only ten primary para-meters in order to cover a wide range of process uncertainties.Based on the new PTM, the impact of process variations isfurther investigated for nanoscale CMOS design. Overall, thispaper develops a solid predictive base for exploratory circuitdesign with extremely scaled CMOS. Furthermore, PTM willcontinue to incorporate physical models for new technologyadvances, such as strained silicon, high-k dielectrics, and metalgate in order to make a far-reaching impact on future design.

II. NEW PREDICTIVE METHODOLOGY

A. Parameter Categorization

Based on our previous work on the BPTM, it is recog-nized that the appropriate categorization of transistor-modelparameters is crucial for an efficient physical prediction [3],[6]. Although there are typically more than 100 parametersin a compact transistor model to calculate the IV and CVcharacteristics, only about ten of them are critical in deter-mining the major behavior of a nanoscale transistor. The per-formance of a transistor is less sensitive to the rest of thesecondary parameters. Based on their physical meanings, thesefirst-order parameters, including technology specifications aswell as process and physical parameters, are listed in Table I[5], [6]. Such a categorization keeps the physicality of scaling

while reducing the complexity of prediction. Furthermore, thiscategorization is relatively independent of model formats as

TABLE IPRIMARY PARAMETERS OF THE PTM

Fig. 3. Trend of EOT scaling from 250- to 32-nm nodes.

those key parameters are mostly shared among different transis-tor models to represent the underlying silicon technology. Ac-curate modeling and prediction of their values are the key to thedevelopment of PTM. In this paper, BSIM4 is used as the modelbasis, while the predictive methodology is general enough to beapplied to other model formats. A detailed approach to predictnominal model parameters is presented in Section II-B.

In addition to predicting nominal values, it becomes increas-ingly important to capture process sensitivities as well. Asprocess variations are vastly exacerbated at future technologynodes, the current deterministic design paradigm needs to beshifted toward a statistical design flow in order to reduce designuncertainties [1], [4]. Thus, physical correlations among mainmodel parameters should be explicitly expressed in compactmodels for both accurate technology extrapolation and robustdesign exploration. While such a consideration is absent in theBPTM [2], [3], the new generation of PTM identifies thosecritical correlations, particularly the interactions among Leff,Vth, mobility, and saturation velocity.

B. Prediction of Model Parameters

As presented in Table I, the first group of parameters isrelated to the process specifications in technology scaling,including Vdd, Toxe, Leff, Vth0, and Rdsw . Their nominal valuesare determined by literature survey from published industrydata, including the International Roadmap for Semiconductors(ITRS) [1]. Based on the collected data, Fig. 3 presents the trendof equivalent oxide thickness (EOT). EOT is steadily scalingdown, although the pace may slow down in recent years. Thetrend of Vdd and Vth scaling is plotted in Fig. 4, where thevalue ofVth is extracted from the subthreshold IV curves.

Due to the concern of subthreshold leakage, Vth almost staysthe same in the nanoscale. The fifth technology parameterRdsw

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Fig. 4. Trend ofVdd and Vth scaling from 250- to 32-nm nodes.

Fig. 5. Trend ofRds scaling from 250- to 32-nm nodes.

is extracted by fitting the IV curves in the linear region, afterlow-filed mobility 0 is predicted [i.e., (1) and (2)]. The trend ofRdsw is shown in Fig. 5. The reduction ofRdsw becomes moredifficult in short-channel devices and results in constant scaling,as shown by the data. These trends, which are supported byexperimental data, are then integrated into PTM to predict thenominal values during CMOS technology scaling.

Values of technology specifications not only define thebasic characteristics of a process but also further determineother important electrical details of a transistor. In particular,

channel doping concentration Nch

is mainly defined by thethreshold voltage. The exact value of Nch is reversed frompublished data of Vth0 in [12][28] using the Vth model inBSIM [2]. Fig. 6 illustrates the trend ofNch scaling. Based onNch, the main coefficient K1 for the body effect ofVth is alsoestimated with analytical models [2]. Furthermore, to model theVth behavior of short-channel transistors, drain-induced barrierlowering (DIBL) must be accounted for. To the first order, thiseffect is captured by Eta0, which is a model parameter forthe DIBL effect. Its value is extracted from published data ofthe Vth rolloff [12][28]. A clear trend ofEta0 is illustratedin Fig. 7.

The amount of channel doping Nch is actually important for

both the threshold voltage and the transportation property ina conductive channel, i.e., the effective carrier mobility eff

Fig. 6. Trend ofNch scaling from 250- to 32-nm nodes.

Fig. 7. Trend ofEta0 scaling from 250- to 32-nm nodes.

and the saturation velocity Vsat. For example, low field carriermobility degrades as Nch increases, and so does the effectivecarrier mobility; Vsat also depends on Nch and Leff due to thephenomenon of velocity overshoot [9]. To account for theseeffects, the following formulas are adopted in the new PTM[9][11] to estimate Vsat and 0, respectively:

NMOS : 0= 1150 exp(5.34 1010Nch) (1)

PMOS : 0= 317 exp(1.25 109Nch) (2)

Vsat=Vsat0 + 0.13effeffkT/q

Vd/L

2

eff

(3)

Equations (1) and (2) are based on the physical model ofmobility [10], [11]; the values of the coefficients are extractedfrom advanced silicon data [10], [11]. Equation (3) of thevelocity overshoot is a simplified solution of the energy-balance equation in [9]. These equations describe importantdependence on Nch and are compatible with the current BSIMframework. The value ofVsat is extracted from published IVdata, particularly the saturation current Ion; its trend duringscaling is plotted in Fig. 8. The effect of velocity overshoot ispronounced as technology scales down to sub-100-nm regime.

Fig. 8 also demonstrates excellent model prediction by (3) withthe extracted Vsat.

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Fig. 8. Trend ofVsat scaling from 250- to 32-nm nodes and verification ofequation (3).

Combining these steps together, the ten primary parameters

Vdd, Toxe, Leff, Vth0, Rdsw, Nch, Eta0, K1, 0, and Vsat canbe extrapolated toward future technology nodes. Furthermore,their values can be adjusted to cover a range of process un-certainties, e.g., from one companys to another ones or fromintrinsic process variations. In general, the error caused by con-sidering these primary parameters only can be reduced to 5%,as demonstrated in [6]. This is further verified by comparing themodel predictions with published data, as shown in Section III.

The remaining model parameters are secondary ones. Thereare no explicit models to predict their values. To improve theaccuracy of predictions, they are further classified into twogroups, depending on their importance in the determination of

transistor performance. The first group is not as critical as theprimary parameters, but it also has observable impact on theIV characteristics. They are related to the determination ofshort-channel effects (Dvt0 and Dvt1 are short-channel-effectcoefficients whose values are extracted from published data ofthe Vth rolloff [12][27] [28]), subthreshold behavior (Dsub,Nfactor, Voff, Cdsc, and Cdscd), mobility (a and b), and earlyvoltage. During the scaling of CMOS technology, their valuesmay change from one generation to the next but are relativelystable within one generation. In this context, their values are fitfrom experimental data for each technology node and then fixedover a range of process conditions. The remaining secondaryparameters have little impact on transistor performance. Thus,for the purpose of early prediction, it is reasonable to leave theseparameters unchanged from previous generations. Finally, theparameters for CV characteristics are extrapolated based onBSIM models.

The new predictive methodology is first implemented withVerilog-A since the physical models [i.e., (1)(3)] are currentlynot available in the standard model format. After generatingthe PTM for each technology node, the Verilog-A modelscan be mapped to the standard BSIM4 model for nominalperformance prediction so that designers can directly use themwith available circuit simulators. In addition, the Verilog-Aformat is also compatible with Simulation Program with In-

tegrated Circuit Emphasis simulation tools, such that circuitdesigners can directly use them. Presently, PTM model files

for 130- to 32-nm technology generations are available. Foreasy access, a website is established to release the latest models(http://www.eas.asu.edu/~ptm).

III. EVALUATION OF PTM

A. Verification ofIV Characteristics

About 20 sets of published IV data from 250- to45-nm nodes at room temperature are collected to verify thenew PTM. Using the methodology previously presented, we areable to generate the corresponding PTM model files. By tuningten primary parameters, the predicted IV characteristics arethen compared to published data for verification. The para-meter tuning steps are explained as follows: First, Vdd, Toxe,Leff, and Vth0 are directly adjusted to the published values.Then, Nch is reversely calculated from Vth0 using analyticalmodels [2]. Based on Nch, 0 and Vsat can be calculated with(1)(3). Finally, Rdsw is extracted from the linear region of the

IV curves. Figs. 9 and 10 illustrate two examples at 45- and65-nm nodes, respectively. The predicted IV curves are com-pared to the measured silicon data from [13] and [14]. Excellentagreement between predicted and published data is achievedin both sub- and superthreshold regions. More comprehensiveverifications are listed in Table II [12][27] [28]. Withoutany further model optimization, the error of Ion predictionsis smaller than 10% for both n-channel MOS (NMOS) andp-channel MOS (PMOS) transistors. Such an excellent match-ing proves the physicality and scalability of the new PTM.

Based on the successful verifications, a PTM for 130- to32-nm technology generations has been generated and released

at http://www.eas.asu.edu/~ptm. Fig. 11 illustrates the trend ofnominal Ion and Ioff. Fig. 12 illustrates the trend of nominalCV/I and switch power (CV2dd). Table III further highlights themajor characteristics of PTM predictions in technology scaling.Note that the threshold voltage almost remains unchanged dueto the leakage concern (Fig. 4). With continuous efforts, thePTM will be extended to 22-nm technology node and below.

B. Impacts of Process Variations

According to the ITRS [1], a similar or larger amount ofprocess variations is expected for future technology nodes.

What matters is not only the amount of variations but also thesensitivity to variations. In the nanometer regime, the sensitivityof transistor performance on process variations becomes moresignificant and is critical for robust CMOS design. Particularneed is observed in the phenomenon of velocity overshoot (3).Fig. 8 illustrates the trend ofVsat over technology generations.When Leff is larger than 100 nm, Vsat can be treated as a con-stant value, e.g., about 80 000 m/s. However, as Leff scales be-low 100 nm, Vsat can no longer be approximated as a constant.Even though mobility eff decreases with technology scalingdue to higher Nch, Vsat increases because of its inverselyquadratic dependence on Leff (1) due to velocity overshoot. Asa consequence, Ion, which is somewhat proportional to Vsat, is

more sensitive to variations ofLeff, mobility, and Vdd in thenanoscale (3). When the channel length is further reduced (e.g.,

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Fig. 9. Verification of PTM with [13].

beyond 22-nm node), the importance of velocity overshoot may

degrade due to ballistic transportation and the source-injectionlimit [2]. In that case, the upper bound of velocity will be thethermal velocity [2].

The importance of velocity overshoot in the study of processvariations is further illustrated in Fig. 13. Fig. 13 decomposesthe variation of Ion into various physical mechanisms at the45-nm node for the variation ofLeff. Without considering DIBLand velocity overshoot, Ion is relatively insensitive to Leffvariations as a result of pronounced velocity saturation in ananoscale transistor. However, the Vth of a nanoscale transistorchanges when there exists a variation ofLeff, i.e., DIBL. Forexample, a 20% Leff variation will result in approximately

18% higher Ion

due to DIBL. An additional amount of 27%Ion variation can be observed if velocity overshoot is included(Fig. 13). Therefore, it is critical to include these physicalmodels in the prediction in order to provide correct guidanceto robust design explorations.

Aside from Leff variation, the random fluctuation of thechannel doping concentration is another leading source ofprocess variations. When Nch deviates from the target value,not only Vth0 but also K1 (i.e., the body effect), 0 (i.e.,mobility), and Vsat will change accordingly. Fig. 14 shows theimpact ofNch variation on Ion. Similar to Fig. 13, the sensitiv-ity ofIon on Nch variation increases when additional physicalmechanisms are included. Considering the dependence of 0

and Vsat on Nch, 12% Nch variation leads to 15% incrementin Ion at the 45-nm node. These physical correlations are not

Fig. 10. Verification of PTM with [14].

considered in the previous BPTM, which causes significant

underestimation of performance variability.The overall map of process sensitivities is shown in Fig. 15

across technology generations from 130 to 32 nm. Due toincreasing process sensitivities, the variation of Ion becomeslarger during technology scaling, even if the normalized processvariation remains constant, e.g., 20% and 12% for Leff andNch variations, respectively (Fig. 15). For future technologygenerations, Leff will continue to be the dominant factor thataffects performance variation because of its role in velocityovershoot and the DIBL effect. Aside from that ofLeff vari-ation, the impact of Nch variation also keeps increasing astechnology scales. Fig. 15 shows the decomposition of the im-

pact ofLeff variations during technology scaling. It reveals thatvelocity overshoot plays a more important role than DIBL fornanoscale MOSFET. Therefore, physical modeling of velocityovershoot is necessary in a variation-aware design. Since PTMcan be easily customized by tuning Leff, Toxe, Rdsw, Vth0,Eta0, Vdd, and other primary parameters, robust circuit designresearch under different conditions is fully supported.

IV. CONCLUSION

A new generation of PTM is developed for 130- to 32-nmtechnology nodes. Compared to the previous BPTM, the newpredictive methodology has better physicality and scalability

over a wide range of process and design conditions. Both nom-inal values and process sensitivity are captured in the new PTM

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TABLE IICOMPREHENSIVE EVALUATION OF PTM PREDICTIONS

Fig. 11. PTM nominal prediction ofIon and Ioff from 250- to 32-nm nodes.

Fig. 12. Nominal prediction ofCV/Iand CV2dd

from 250- to 32-nm nodes.

for robust design research. Excellent predictions have beenverified from 250- to 45-nm nodes. The importance of physicalcorrelations among parameters and the impact of process varia-tions have been evaluated. Model files for bulk CMOS with Leff

as low as 13 nm are available at http://www.eas.asu.edu/~ptm.These predictive model files enable early-stage circuit design

TABLE IIISUMMARY OF THE PTM

Fig. 13. Decomposition of the impact ofLeff variation (45-nm node).

for end-of-the-roadmap technologies. In the future, the PTMwill be extended to more advanced technology generations,with appropriate models for nontraditional front-end processes,such as high-k gate dielectrics and strained silicon. Feedbacks

from both industrial and academic researchers will be veryhelpful to improve the accuracy and flexibility of the PTM.

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Fig. 14. Decomposition of the impact ofNch variation (45-nm node).

Fig. 15. Impact ofLeff variation on Ion across technology generations.

ACKNOWLEDGMENT

The authors would like to thank the BSIM group at theUniversity of California, Berkeley, for the valuable discussionson this project.

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Wei Zhao (S05) received the B.S. degree in elec-tronics engineering from Tsinghua University, Bei-

jing, China, in 2004. He is currently working towardthe Ph.D. degree in electrical engineering at theArizona State University, Tempe.

His research interests include the modeling anddesign of robust circuits using nanoscale silicon.

Yu Cao (S99M02) received the B.S. degree inphysics from Peking University, Beijing, China, in1996 and the M.A. degree in biophysics and thePh.D. degree in electrical engineering from the Uni-versity of California, Berkeley, in 1999 and 2002,respectively.

He was a Summer Intern with Hewlett-PackardLabs, Palo Alto, CA, in 2000, and with IBM Mi-

croelectronics Division, East Fishkill, NY, in 2001.After working as a Postdoctoral Researcher at theBerkeley Wireless Research Center, he joined Ari-

zona State University, Tempe, where he is currently an Assistant Professor ofelectrical engineering. He also serves as a Consultant for several electronicdesign automation companies. He has published numerous articles and coau-thored one book on nano-CMOS physical and circuit design. His researchinterests include modeling and analysis of nanoscale circuits, design for low-power and reliable circuit and system integration, modeling and integration ofpostsilicon technologies, and high-speed signaling techniques.

Dr. Cao was a recipient of the 2006 National Science Foundation CAREERAward, the 2006 IBM Faculty Award, the 2004 Best Paper Award at the Interna-tional Symposium on Quality Electronic Design, and the 2000 Beatrice WinnerAward at the International Solid-State Circuits Conference. He currently serveson the technical program committee of numerous design automation and circuitdesign conferences.

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