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48 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008

Analytical Modeling of the Suspended-Gate FETand Design Insights for Low-Power Logic

Kerem Akarvardar, Christoph Eggimann, Dimitrios Tsamados, Yogesh Singh Chauhan,Gordon C. Wan, Adrian Mihai Ionescu, Senior Member, IEEE,

Roger T. Howe, Fellow, IEEE, and H.-S. Philip Wong, Fellow, IEEE

AbstractAn analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFETlogic circuits, is developed. The model is based on the depletionapproximation and expresses the pull-in voltage, the pull-out volt-age, and the stable travel range as a function of the structuralparameters. Gate position is explicitly expressed as a functionof the gate voltage, thus enabling the convenient integration ofthe analytical SGFET relationships into the standard MOSFETmodels. Starting from the new SGFET model, the influence ofthe mechanical hysteresis on the circuit steady-state behavior is

discussed, the potential of using the SGFET as an ultra-low powerswitch is demonstrated, and the operation of the complementarySGFET inverter is analyzed.

Index TermsElectrostatic actuators, inverter, microelectro-mechanical system (MEMS), MOSFET, nanoelectromechanicalfield-effect transistor (NEMFET), nanoelectromechanical systems(NEMS), resonant-gate FET, subthreshold swing, suspended-gateFET (SGFET).

I. INTRODUCTION

IN ADVANCED CMOS technology nodes with supply volt-

ages 1 V, one of the major issues is the limited scalabilityof the threshold voltage. Due to the fundamental minimum

value of the subthreshold swing, lowering the threshold voltagebelow about 150 mV results in intolerably high off-current

[1]. In this paper, we analyze the suspended-gate field-effect

transistor (SGFET) as a candidate to circumvent this limitation.

Due to their extremely low standby power consumption and

ideal switching characteristics, SGFETs can be used as sleep

transistors for efficient power management and partitioning

in highly scaled CMOS ICs. SGFETs can also be used to

implement low-power (full-SGFET or SGFET/MOSFET) logic

circuits.

Manuscript received May 17, 2007; revised August 9, 2007. The works of

K. Akarvardar, G. C. Wan, and H.-S. P. Wong are partially supported by theFocus Center for Circuit & System Solutions (C2S2), one of five researchcenters funded under the Focus Center Research Program, a SemiconductorResearch Corporation Program; C. Eggimann, D. Tsamados, Y. S. Chauhan,and A. M. Ionescu were supported in part by the Integrated Project MINAMI;and R. T. Howe were supported in part by a grant from the Charles PowellFoundation. The review of this paper was arranged by Editor T-J. K. Liu.

K. Akarvardar, G. C. Wan, R. T. Howe, and H.-S. P. Wong are with theDepartment of Electrical Engineering and the Center for Integrated Systems,Stanford University, Stanford, CA 94305 USA (e-mail: [email protected]).

C. Eggimann, D. Tsamados, and A. M. Ionescu are with the Swiss FederalInstitute of Technology Lausanne, 1015 Lausanne, Switzerland.

Y. S. Chauhan is with the Semiconductor Research and Development CenterIBM, Bangalore 560045, India.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2007.911070

The idea of combining an electrostatically actuated mechan-

ical switch with a MOSFET was first introduced 40 years ago

[2]. The motivation behind this earliest resonant-gate FET

was to simultaneously obtain a stable and high-Q frequency se-lection provided by the electromechanical beam and an efficient

readout provided by the FET. After [2], hybrid MEMS/FET

structures were mainly used in gas [3][5] and pressure sensing

[6]. The use of the resonant-gate FETs in radiation-resistant

applications was also proposed [7].First in 2002, the SGFET (a variant of the resonant-gate FET)

was conceived as an abrupt current switch [8]: Dynamic thresh-

old operation and the possibility of a subthreshold swing below

60 mV/dec limit were reported. Subsequently, several other

papers described the use of the SGFET as a switch, resonator,

and memory [9][14]. The CMOS-compatible fabrication of

the SGFETs and the experimental characteristics, confirming

the theoretical predictions on the steep, < 60 mV/dec, sub-threshold swing and dynamic threshold operation were also

reported [9], [15]. Recently, the accumulation-mode SGFET

was introduced as a promising device for high-performance

logic circuits [16]. It is shown that such a structure can meet,

in theory, International Technology Roadmap for Semiconduc-tors performance specifications for low-power applications at

25-nm gate length.

Previous work on SGFET modeling is based on the Enz

KrummenacherVittoz (EKV)-based [17] expression of the

gate-to-channel capacitance [8]. This model is valid in all

regimes of operation. However, it requires time-consuming

iterative calculations for the simultaneous resolution of the

force-balance and capacitance equations. Additionally, it does

not provide simple guidelines for the transistor operation since

the variation of the transistor parameters as a function of the

structural parameters (dimensions and material properties) is

not explicitly shown.This is why, in this paper, by considering the operation

region of interest for the logic circuits, we derived a fully

explicit static model for the SGFET. Our new analytical model

provides physical insights related to the SGFET operation and

basic design rules suitable for hand calculations. We develop

simple relations for the pull-in and pull-out voltages, the travel

range, and the SG position with respect to the gate voltage.

In addition, by combining our model with a conventional

MOSFET currentvoltage model, we estimate the behavior and

performance of the SGFET logic circuits.

This paper is organized as follows. In Section II, we in-

troduce our analytical model following a brief description of

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AKARVARDAR et al.: ANALYTICAL MODELING OF THE SGFET AND DESIGN INSIGHTS FOR LOW-POWER LOGIC 49

Fig. 1. N-channel SGFET. (a) Three-dimensional structure: The channel width is equal to the beam length (W = WFET = Lbeam), and the channel length isequal to the beam width (L = LFET = Wbeam). (b) Cross section parallel to device length. (c) Equivalent capacitor circuit. (d) Symbol.

the SGFET operation. In Section III, we discuss the optimal

choice of the structural parameters for logic applications. Thecurrentvoltage characteristics of the SGFET are presented in

Section IV. In Section V, we illustrate the use of our model

and the operation of complementary SGFET logic circuits by

introducing the SGFET inverter.

II. OPERATION AND ANALYTICAL MODELING

The 3-D structure, 2-D cross-section, equivalent capacitor

circuit, and symbol of the n-channel SGFET are shown in

Fig. 1. The dimensional parameters are defined as follows: L isthe SGFET channel length, h is the thickness of the suspended-

gate (SG), tox is the gate-oxide thickness, tgap0 is the initialgap thickness, and W is the SGFET channel width that canbe assumed equal to the beam (suspended bridge) length if

W tgap0; the beam width is equal to channel length L.An SGFET combines an electrostatically actuated NEMS

switch and an inversion-mode MOSFET (Fig. 1). It is distin-

guished from a regular MOSFET by the presence of an air

gap between the doubly clamped gate electrode and the gate

oxide. The SG structure in Fig. 1(a) is usually realized by

the sacrificial etching of a material (such as cured polyimide,

polycrystalline, or amorphous silicon) that is deposited on the

gate insulator before the gate formation [9], [15], [18]. The SG

material is typically polysilicon [18] or aluminum (AlSi) [15].

The bottom range of the values reported so far for the SGFETair gap is around a few hundred nanometers [9], [11], [15]

(130 nm minimum [9]). An important challenge regarding the

fabrication of SGFETs featuring CMOS-compatible actuationvoltages is to realize both the gap and the gate electrode in the

10-nm range. Atomic-layer deposition seems a very promising

technique for both structural and sacrificial layers, due to its

monolayer-level thickness control, and can be used for fabri-

cating SGFETs with vertical or lateral dimensions controlled

at the atomic scale [19]. It is important to mention that gap

values below 10 nm were already demonstrated in biosensors

[20]; however, the layer over the gap was much thicker and

not movable. On the other hand, fully released and functional

h = 20 nm-thick nanocomposite AlMo resonators were alsoreported [21].

The operation of the SGFET is explained as follows: At

flatband condition, (VG = VFB), the charge density at thegate electrode and inside the semiconductor is zero, yielding

x = tgap0, where x shows the actual distance between the gateoxide and the gate electrode [Fig. 1(b)]. As VG increases, apositive charge (and also an equal amount of negative charge

inside the semiconductor) is built up in the gate electrode,

giving rise to an electrostatic force pulling down the SG and

resulting in x < tgap0 [Fig. 2(a)]. Until the gate voltage reachesthe pull-in voltage Vpi, the electrostatic force can be balancedby the counteracting elastic force. However, for VG Vpi(corresponding to a critical surface potential s = pi and acritical gap thickness xpi), the electrostatic force overcomes the

elastic component, and the gate collapses (is pulled in) on thegate oxide [Fig. 2(b)]. When the gate is pulled in, the abrupt

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Fig. 2. Cross-section of the n-channel SGFET parallel to device width.(a) Gate up (VFB < VG < Vpi, tgap0 > x > xpi). (b) Gate down (VG

Vpi, x = 0).

increase in gate capacitance leads to an abrupt reduction of

the threshold voltage and, consequently, a sharp increase in the

drain current [8]. As will be detailed later, the SGFET features

mechanical hysteresis, which means that the pull-out of the SG

requires a pull-out voltage VG = Vpo that is lower than Vpi.In the following, the SGFET pull-in and pull-out voltages

will be separately modeled, and an explicit relationship between

the gate position and the gate voltage will be developed.

A. Pull-In ModelingWe start with the force-balance equation related to the SG

[8], [16]

W LgapV2gap

2x2= k(tgap0 x). (1)

The left-hand side of (1) designates the electrostatic attraction

force applied to the SG, whereas the right-hand side designates

the counteracting elastic force [Fig. 1(b)]. gap is the gap per-mittivity, and Vgap is the voltage drop across the gap. The elasticforce is represented by a linear spring constant k. This is a sim-

plified assumption since the nonlinear stretching component ofthe spring constant, which can lead to a nonnegligible restoring

force (and can alter the pull-out behavior [22]), is neglected.

In (1), the van der Waals attraction [23], [24] between the

SG and the substrate is not taken into account. However, it is

worth mentioning that the impact of the van der Waals forces

on the SGFET characteristics becomes nonnegligible if the air

gap is extremely scaled: As an example, for tgap0 2 nm andVgap = 1 V, the van der Waals forces are theoretically evenhigher than the electrostatic force.

Vgap is expressed as a function of the actual gap thicknessand the VG-dependent semiconductor charge density Qsc as

Vgap = Qsc

gap/x. (2)

The denominator of (2) shows the actual gap capacitance per

unit area, Cgap [Fig. 1(c)]. The substitution of (2) into (1) yields

x = tgap0 W L

2gapkQ2sc. (3)

Note that the second term on the right-hand side of (3) corre-

sponds to the gate displacement x [Fig. 1(b)]. Equation (3) isvalid for x > xpi. Beyond this limit, the system is no longer inequilibrium, and the gate snaps down to the gate oxide, leading

to x = 0.For a uniformly distributed electrostatic force along the beam

and neglecting the residual stress, the spring constant k is givenin terms of the structural parameters by [25], [26]

k =32ELh3

W3. (4)

In a simple MEMS switch, consisting of two parallel metallic

plates separated by an air gap, the stability analysis yields

xpi = 2tgap0/3. When a second capacitance Cf is connectedin series with Cgap, xpi is reduced to

xpi =2Cgap0/Cf

3tgap0 (5)

where Cgap0 = gap/tgap0 is the minimum gap capacitance[27], [28]. Cf induces a negative feedback on Vgap and is nor-mally used to increase the travel range of the moving electrode

in MEMS switches. Note from (5) that, for Cgap0/Cf 2, theinstability (i.e., pull-in) is completely suppressed [27], [28]. In

the case of the SGFET, Cf is equal to the series equivalent ofCox with Csc [Fig. 1(c)].

Simple relationships for the pull-in voltage Vpi, the SGposition at pull-in, xpi, and the surface potential at pull-in(pi) are obtained starting from the depletion approximation.Since our ultimate goal is to use the SGFET in logic circuits

by taking advantage of the sharp onoff transition, we are

naturally interested in the case where the pull-in (and hence

pull-out) occurs before the formation of the inversion channel

(this implies that pi < 2F, where F is the substrate Fermipotential). Therefore, in terms of our objective, the depletion

approximation does not lead to a limitation.

Although SGFETs can be designed in such a way that the

gate is pulled-in in the strong inversion region (see, for instance,

currentvoltage characteristics in [8]), this case exacerbates theshort-channel effects due to the weak gate-to-channel coupling

in the OFF-state [16] and, therefore, will not be considered here.

By contrast, the occurrence of the pull-in in weak inversion

enables to suppress short-channel effects since the threshold

voltage and the subthreshold swing are determined by the

mechanical pull-in of the gate. As will be shown in the next

section, the weak inversion switching allows the SGFET to

eliminate the usual subthreshold region, where the slope of

the currentvoltage characteristic is finite, and to reduce the

threshold voltage without increasing the off-current.

Using the depletion approximation, the depletion charge is

given as a function of the surface potential by

Qd(s) =

2SiqNAs (6)

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where Si is the silicon permittivity, qis the elementary charge,and NA is the substrate doping. Substituting (6) into (3) forQsc, the gate position is expressed as a function of the surfacepotential

x(s) = tgap0 W LSiqNA

gapks. (7)

According to (7), as long as the substrate is in depletion, the

gate position is a linear function of the surface potential.

The limit gate position at pull-in (xpi) is written in termsof the limit surface potential at pull-in (pi) by using (5)and by expressing Cf as a series combination of the oxidecapacitance Cox and the semiconductor capacitance Csc (indepletion, Csc = Si/xdi, where xdi is the depletion depth ats = pi)

xpi =2 ( + pi)

3

tgap0 (8)

where

Cgap0

Cox(9a)

Cgap0

2

SiqNA. (9b)

The surface potential at pull-in is expressed by replacing s bypi and x by the expression of xpi [given by (8)] in (7), andsolving the resulting quadratic equation for pi

pi =+

2 2

22(10)

where

3W LSiqNA

tgap0gapk(11a)

2(1 + ) + 2. (11b)

Equation (10) is the largest of the two distinct roots of

the quadratic equation, which provides an accurate xpi.Equations (8) and (10) are the relationships expressing xpi and

pi, respectively, in terms of the structural parameters, and theyare valid for 0 pi < 2F.

The pull-in voltage is defined as the gate voltage leading

to s = pi. From the equivalent capacitor divider circuit inFig. 1(c), the effective gate voltage can be expressed as the sum

of the voltage drops across the gap (Vgap), across the gate oxide(Vox), and on the semiconductor (s)

VG(s) = VFB Qsc(s)x(s)

gap

Qsc(s)

Cox+ s (12)

where VFB is the flatband voltage related to the work function

difference and the oxide charge density. Substituting x(s) byxpi, Qsc(s) by Qd(pi), and s by pi in (12), the pull-in

voltage of the SGFET, provided that the switching occurs in the

weak inversion, is expressed as

Vpi = VFB +

pi + pi (13)

where

1 + Coxgap/xpi

(14)

and = (2SiqNA)0.5/Cox is the usual MOSFET body effect

coefficient. The term inside the parenthesis in (14) corresponds

to the increase in capacitance once the gate is pulled in.

Equation (13) is a general relationship for Vpi. It reducesto the well-known pull-in voltage of the simple NEMS switch

[29], Vpi(sw), for NA (metallic bottom electrode case,leading to pi 0 and xpi (2 )tgap0/3) and VFB 0(same material for both electrodes):

lim Vpi(SGFET)NA

VFB0

= Vpi(sw) =8k(tgap0 + tox/r)3

27gapW L . (15)

In (15), r is the dielectric constant of the gate oxide material.

B. Pull-Out Modeling

In this section, we present a simple relationship for the

SGFET pull-out voltage, starting from the forces acting on

the gate while the gate is pulled in. We take into account

the restoring elastic force and the opposing electrostatic and

adhesion forces.

In the SGFET, once the gate is pulled in, the gate capacitance

increases abruptly, and so do the surface potential and the

charge density. The abrupt increase in charge density can also

be explained by the abrupt reduction of the threshold voltage.

For VG > Vpi, the SGFET behaves as a conventional MOSFET.When VG is swept back from a larger value than the pull-involtage, pull-out does not occur at VG = Vpi because the sur-face potential is higher than pi. This leads to a higher chargedensity and, to a higher electrostatic force than those at the

onset of pull-in (while x = xpi). The release of the gate is alsoretarded (if not completely prevented) by the surface adhesion

forces [30]. Therefore, VG should be reduced to Vpo < Vpiin order for pull-out to happen.

The force-balance equation in the gate-down state, just be-fore the pull-out, can be approximated in the first order as

W LoxV2ox2t2ox

+ Fa = ktgap0 (16)

where the first term on the left-hand side represents the elec-

trostatic force applied to the gate, whereas the term on the

right-hand side shows the elastic restoring force of the doubly

clamped beam. Fa is the surface adhesion force. In (16), we as-sumed that the spring constant is given by (4) even after the gate

is pulled in [Fig. 2(b)]. The restoring elastic force can be more

accurately calculated by taking into account the influence of

the nonlinear stretching component on the spring constant [22].Furthermore, we neglected the peeling of the gate [31][33]

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when VG is swept back toward Vpo, and we assumed that thegate stays in contact with the whole gate oxide area until the

occurrence of the pull-out.

In the absence of capillary forces and at small roughness

values, the adhesive interactions are dominated by the attractive

van der Waals forces between noncontacting surfaces rather

than by the areas that are actually in contact [34], [35]. Dueto the surface roughness, which prevents the intimate contact

of dry MEMS surfaces, the adhesion energies are very low,

typically in microjoules per square meter range [34], [35].

When the gate is in the down state, Fa can be expressed as

Fa = 2W L

D0(17)

where is the interfacial adhesion energy per unit area [34]. D0is an offset corresponding to the closest approach of the two sur-

faces and is determined by the average surface roughness [34].

For VG = Vpo, the depletion approximation leads to

Vox|VG=Vpo =

po, where po is the surface potential atpull-out. From (16) and (17), po is given by

po =ox

SiqNA

ktgap0

W L

2

D0

. (18)

Since po > 0 for an n-channel SGFET, the condition

Fa < ktgap0 (19)

needs to be fulfilled in order for the beam not to stick to the

substrate. In other words, in the absence of the electrostatic

force (at flatband condition), the restoring force should be large

enough to overcome the surface adhesion force.The pull-out voltage is given as the sum of the flatband

voltage, the voltage drop on the gate-oxide, and the surface

potential at pull-out

Vpo = VFB +

po + po. (20)

Equation (20) stands as a general pull-out expression: It re-

duces to the pull-out equation of the simple MEMS switch

featuring a dielectric layer [29] for NA , VFB 0,and 0

lim Vpo(SGFET)NA

VFB0

0

= Vpo(sw) =

2ktgap0t2

oxoxW L

. (21)

It is worth mentioning that, besides the surface adhesion

forces, the hysteresis window can also be enlarged by the oxide

surface charge, whose density depends on the gate position

(pulled in or pulled out). Indeed, this property is exploited in

[12] to build a capacitorless 1T memory cell. However, it is

experimentally shown that this effect is mostly significant when

the gate oxide is degraded, for instance, by an oxygen plasma

process that induces traps on the oxide surface [9], [12]. More

promising future SGFET memory architectures are likely to use

controlled thin storage layers in the gate dielectric instead ofthe oxide traps; thin nanocrystal or ferroelectric layers can be

engineered to achieve information storage in SGFET devices

with relatively low operation voltages (< 510 V) [36].

C. SG Position as a Function of Gate Voltage

To obtain a relationship between the gate position and the

gate voltage, (3) and (12) need to be solved together. However,the relationship resulting from these equations involves a third-

degree polynomial and does not provide a simple solution for

x(VG) and s(VG) even when the depletion approximationis used.

To obtain a simple, yet reasonably accurate expression

for x(VG) yielding x = tgap0 for VG = VFB and x = xpi atVG = Vpi, we first impose x(s) = xpi in (12) and solve theresulting quadratic equation for s while Qsc = Qd:

s,up =

2

VG VFB +

2

4

2. (22)

Equation (22) is valid when the gate is in the up state and

VG Vpi. When the gate is pulled down and VG Vpo, sis given by the usual MOSFET relationship [37] obtained by

imposing Qsc = Qd and x = 0 in (12) or by replacing in(22) by :

s,MOS =

2

VG VFB +

2

4

2. (23)

Again, the quadratic equations providing (22) and (23) enable

also a second root as solution, which is discarded since it does

not correspond to the physical situation. Equations (22) and

(23) are compared to the iterative solution of (3) and (12) inFig. 3(a). In the iterative solution, the exact charge equation

[37] including acceptors, holes, and electrons is used. Naturally,

s,MOS is in very good agreement with the numerical solutionfor po < s < 2F above which the depletion approxima-tion loses its validity. s,up is also in good agreement withthe iterative solution, particularly for VG values close to Vpiand VFB (since, for VG VFB, Qsc 0, and the sensitivityto x is very weak). The slight discrepancy between the exactsolution and (22) for the gate-voltage range VFB < VG < Vpiis of minor importance since, in the currentvoltage character-

istic, this gate-voltage range corresponds to the bottom of the

subthreshold region with very low drain-current values.The expression for x(VG) is obtained by substituting (22)into (3) for s while Qsc = Qd:

x(VG) = tgap0 W LSiqNA

gapk

2

VG VFB +

2

4

2.

(24)

Equation (24), which is valid for xpi x(VG) tgap0, iscompared to the iterative solution in Fig. 3(b). Both models

reproduce the same trend; however, (24) underestimates the gap

height for the intermediate x values due to the approximationmade in (22). On the other hand, the difference between the

approximate and exact solutions for Vpi and Vpo in Fig. 3(a)and (b) originates from the depletion approximation and is

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Fig. 3. Exact (numerical) model versus analytical model. (a) Variation ofthe surface potential as a function of the gate voltage. (b) Variation of thenormalized gap thickness as a function of the gate voltage. W = 650 nm,L = 100 nm, h = 10 nm, E = 170 GPa (Si) (k = 2 N/m), tgap0 = 10 nm,

tox = 2 nm (SiO2), NA = 3.1017

cm3

, VFB = 0, = 25 J/m2

, andD0 = 0.2 nm. Numerical model refers to the iterative solutions of (3) and (12)and uses the exact charge equation featuring acceptors, holes, and electrons.

negligible (kT/q). Note that VFB is assumed equal to zeroin this particular example, leading to s = 0 in Fig. 3(a) andx(VG)/tgap0 = 1 in Fig. 3(b) for VG = 0.

III. OPTIMAL DESIGN WINDOW FOR

SGFET LOGIC SWITCHES

The use of SGFETs in logic circuits imposes the following

conditions for the pull-in and pull-out voltages:

Vpo > 0 (25a)

Vpi < VDD (25b)

pi < 2F. (25c)

In addition to these, the threshold voltage when the gate

is pulled in (the conventional MOSFET threshold voltage),

VT,MOS, should naturally satisfy

VT,MOS = VFB +

2F + 2F < VDD. (25d)

The scaling of the supply voltage VDD is normally imposed by

(25b), rather than (25d), despite the high body doping that tendsto increase VT,MOS.

The impact of the structural parameters on the constraints

mentioned earlier is shown in Fig. 4(a)(d) where the varia-

tion of the pull-in and pull-out voltages as a function of the

(a) device width, (b) gap height, (c) SG thickness, and

(d) gate materials Youngs modulus is shown. Note that the

dimensions used in Fig. 4 are in the nanometer scale, and

they are about three orders of magnitude smaller than thetypical dimensions of MEMS switches (several micrometers

for the vertical dimensions and hundreds of micrometers for

the beam length) in order to meet the requirements of a small

device footprint and a low-voltage actuation (the range of the

parameters in Fig. 4 is selected such that Vpi 2 V). As ageneral trend, both Vpi and Vpo increase as the beam (SG) getsstiffer, i.e., as the spring constant increases by lowering W orincreasing h or E. Vpi and Vpo increase also for a larger tgap0due to the lowered electrostatic force. For tgap0 = h = 10 nmand for a polysilicon SG (E = 170 GPa), sub-1 V operation(Vpi VFB < 1 V) requires roughly W 700 nm. Furtherlateral scaling requires a corresponding vertical scaling (the

reduction of tgap0 and/or h below 10 nm) or the use of a gatematerial with a smaller Youngs modulus (Al or Ti). However,

these solutions may not be viable due to the pronounced impact

of the van der Waals forces (as tgap0 is reduced) and also dueto the pull-out requirements. Fig. 4 reveals that an excessive

increase of W or an excessive lowering of the tgap0, h, or Emay reduce the elastic restoring force (ktgap0) to an intolerablylow value, which could result in sticking according to (19).

Therefore, the scaling of VDD depends (indirectly) on the pull-out characteristics as well. The maximum value of W andthe minimum value of tgap0, h, and E that would not lead tosticking (while the remaining parameters are fixed) correspond

to po = 0 [and hence to Vpo = VFB according to (20)], andthey are indicated with arrows in Fig. 4.

The strong sensitivity of Vpi and Vpo with respect to thehorizontal and vertical dimensions imposes a particularly tight

process control to obtain uniform SGFET characteristics. The

dependence of the pull-out (and hence the hysteresis window

width) on the surface adhesion forces is the main technological

challenge related to the fabrication and design of SGFETs.

A reliable fabrication of SGFETs with a well-controlled pull-

out requires in-depth understanding and control of the surface

adhesion forces.

Another important parameter in SGFETs is the stable travel

range (maximum ofx) of the SG before it hits the gate oxidedue to instability. Fig. 5 shows that the travel range is a strongfunction of the substrate doping concentration, and it can even

be extended to the whole gap height (x = tgap0 or xpi = 0) inlowly doped substrates (solid curve) [27]. However, the use of

the SGFET in logic circuits requires instability (in contrast to

inertial sensor applications of microstructures) to improve the

on/off capacitance or current ratio, and therefore, a large travel

range is not desired. The travel range can be minimized (i.e., xpican be maximized) by increasing the substrate doping, as shown

in Fig. 5: A highly doped substrate emulates a metallic bottom

electrode, and the xpi/tgap0 ratio converges to the maximumvalue given by (5) [27].

A second reason which makes a low substrate dopingundesirable is the possible insufficiency of the electrostatic

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Fig. 4. Variation of the pull-in and pull-out voltages as a function of the (a) device width, (b) gap height, (c) SG thickness, and (d) Youngs modulus of the gatematerial. L = 100 nm, tox = 2 nm (SiO2), NA = 10

18 cm3, VFB = 0.13 V, = 20 J/m2, D0 = 0.2 nm, and VT,MOS = 1.4 V. The variation ofVpo for

Vpo > VT,MOS is not shown since (20) is only valid in depletion.

Fig. 5. Normalized stable travel range as a function of the substrate dopingconcentration. tgap0 = 10 nm, h = 10 nm, L = 100 nm, tox = 2 nm (SiO2),

and VFB = 0.13 V.

force induced by the depletion charge to create instability.

Such structures with lowly doped substrates and relatively

high spring constants present no interest for logic appli-

cations since they do not enable weak inversion switching

(the channel would be already in inversion when the pull-

in occurs). In Fig. 5, for W = 800 nm and E = 170 GPa,the pull-in cannot be induced by the depletion charge alone

if NA < 6.1016 cm3. For W = 800 nm and E = 1 TPa

(Youngs modulus of carbon-nanotube), this limit shifts to

NA < 3.1017 cm3. In summary, as the beam gets stiffer, the

minimum substrate doping required to induce weak inversionswitching increases.

IV. CURRENTVOLTAGE CHARACTERISTICS

SGFET currentvoltage characteristics can be obtained start-

ing from any MOSFET model just by replacing the oxide

capacitance Cox in the original model equations with a seriesequivalent of Cox and Cgap = gap/x(VG), where x(VG) isgiven by (24).

For a long-channel device, as long as the pull-in occurs

in weak inversion (pi < 2F), the drain voltage VD hasnegligible influence on the surface potential [37] and therefore

does not modulate Vpi. This means that our model equationsthat are independent of VD can be safely integrated into theconventional MOSFET models. In a short-channel device, the

influence ofVD on Vpi and Vpo can be minimized by increasingthe substrate doping. As the channel length is reduced, the

fringing fields and the electrostatic force applied to the SG by

the source and drain regions (that are neglected in this paper)

become also important.

A transfer characteristic example for the SGFET, obtained by

integrating our analytical relationships into the MOSFET EKV

model [17], is shown in Fig. 6 (solid curve) along with the con-

ventional (non-SG) MOSFET characteristic (dotted curve). On

the same figure, the SGFET characteristic, obtained by using

the EKV model and the numerical solution of x(VG), Vpi, andVpo, is also shown (dashed curve). Note that the discrepancybetween the exact and the numerical model originated from

the approximation that is made while deriving (24) is trivial

since the corresponding drain-current values are well below the

junction leakage floor (assumed here as 1 pA/m).

According to Fig. 6, the SGFET operates as an idealswitch with an infinite subthreshold slope. However, the

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Fig. 6. Analytically and numerically calculated SGFET transfer characteris-tics (MOSFET characteristic is also shown for comparison). W = 500 nm,L = 100 nm, h = 10 nm, E = 170 GPa (Si), tgap0 = 10 nm (k =

4.35 N/m), tox = 2 nm (SiO2), VFB = 1.1 V, NA = 1018 cm3, VD =

1.5 V, = 250 cm2/(V s), = 45 J/m2, and D0 = 0.2 nm. Leakage flooris assumed equal to 1 pA/m.

Fig. 7. Schematic of the complementary SGFET inverter.

currentvoltage characteristic has hysteresis. This example

illustrates the interest of the SGFET for logic circuits:

By selecting Vpo just above 0 V (Vpo = 90 mV in thisexample) and the conventional MOSFET threshold just above

Vpo (VT,MOS = 280 mV in this example), SGFET provides

many orders of magnitude reduction in the off-current withoutdeteriorating the on-current, which means a tremendous im-

provement in Ion/Ioff ratio. Fig. 6 shows also the importanceof the tight Vpo control in order to take the full advantage of theSGFET low-leakage feature.

V. SGFET INVERTER

In this section, we present the operation and characteristics

of the complementary SGFET inverter in order to show the

efficiency of our simple model to design SGFET logic circuits

and to illustrate the advantages of the SGFETs mentioned in the

previous section.

The schematic of the complementary SGFET inverter isshown in Fig. 7. The architecture is the same as that of a CMOS

inverter except that the complementary MOSFETs are replaced

by complementary SGFETs.

The steady-state behavior of the proposed circuit is explained

as follows.

1) For Vin = VDD, Vout = 0. This yields VGS,n = VDD >Vpi,n, which means that the gate of the n-channel SGFET

is pulled in. On the other hand, |VGS,p| = 0 < |Vpo,p|,implying that the gate of the p-channel device is pulled

out (the subscripts n and p show the voltages or

parameters related to the n- and p-channel SGFETs,

respectively).

2) For Vin = 0, Vout = VDD. This leads VGS,n = 0 < Vpo,n,implying that the NFET is pulled out. On the other hand,

|VGS,p| = VDD > |Vpi,p|, which means that the PFET ispulled in.

In summary, in each static state, one of the transistors is

pulled in, whereas the other is pulled out. The pulled-out

transistor has a much smaller off-current than that of a regular

MOSFET, as shown in Fig. 6; therefore, the overall static power

dissipation in the SGFET inverter is reduced as compared to its

CMOS counterpart.

In SGFETs, once the gate is pulled-in in the subthreshold

region, the channel region either stays in depletion or it is

driven to inversion (even to strong inversion), depending on

the relative position of Vpi with respect to VT,MOS. We in-vestigate the SGFET inverter characteristics by distinguishing

two different situations based on the relationship between Vpiand VT,MOS. We assume a fully symmetrical case (i.e., samechannel mobility (), |Vpo|, |Vpi|, and |VT,MOS| for PFET andNFET) to focus the attention on the intrinsic behavior of the

SGFET.1) |Vpi| < |VT,MOS|: The transfer characteristics for both

types of SGFETs, satisfying |Vpi| < |VT,MOS|, are shown inFig. 8(a) in semilogarithmic and linear scales. Since, in this

case, the semiconductor surface stays in depletion after the pull-

in, the threshold voltage of the SGFET is equal to VT,MOS. Con-sequently, in linear scale, the SGFET transfer characteristics are

the same as those of the conventional MOSFETs.

The static characteristics of the SGFET inverter, designed

with the SGFETs featuring the characteristics in Fig. 8(a),

are shown in Fig. 8(b). The availability of an analytical

currentvoltage model that does not require iterations is crucial

for obtaining such characteristics in a short computing duration.Fig. 8(b) shows exactly the same voltage transfer characteristic

(and the supply current characteristic in linear scale) as that of

a CMOS inverter since the threshold voltages of the SGFETs

are not modified by the mechanical pull-in and pull-out events

that both occur in the subthreshold region. However, the SGFET

inverter consumes less static power than the CMOS inverter

because, in each static state, one of the SGs is pulled up. For this

configuration, the switching threshold of the SGFET inverter

Vth is equal to VDD/2 as in a CMOS inverter.2) |Vpi| > |VT,MOS|: The SGFET transfer curves in linear

scale corresponding to this second case are shown in Fig. 9(a)

(the n-channel SGFET characteristic in semilogarithmic scale

is similar with that in Fig. 6). The |Vpi| > |VT,MOS| conditionis satisfied just by reducing the beam length from its value in

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Fig. 8. |Vpi| < |VT,MOS| case. (a) N- and p-channel SGFET transfer charac-teristics in linear and logarithmic scales (|VD| = 1.5 V). (b) ComplementarySGFET inverter static characteristics. W = 600 nm, L = 100 nm, h = 10 nm,E = 170 GPa (k = 2.5 N/m), tgap0 = 10 nm, tox = 2 nm (SiO2), NA =

1018 cm3, |VFB| = 1.05 V, = 250 cm2/(V s), VDD = 1.5 V, =

2 J/m2, and D0 = 0.2 nm.

Fig. 8, W = 600 nm, to W = 510 nm in Fig. 9 and hencemaking the beam stiffer (the spring constant is increased). The

other parameters remained as in Fig. 8 except that a higher is assumed in Fig. 9 to locate |Vpo| between 0 and |VT,MOS|.Notice in Fig. 9(a) that the threshold voltage of the SGFETs is

no longer given by VT,MOS while sweeping VG from0 to |VDD|,but it is now equal to Vpi (i.e., to Vpi,n or Vpi,p).

The modulation of the threshold voltages by the mechanical

pull-in results in a fundamental change in the SGFET-inverter

transfer characteristics [Fig. 9(b)]: The voltage transfer curve

now exhibits hysteresis with two different switching thresholds

(Schmitt-trigger behavior). This is because, in this configura-

tion, the logic state change is not possible unless one of thebeams, which was previously pulled out, is pulled in. As a

result, the two switching threshold voltages are dispersed on

either side of VDD/2: Vth = Vpi,n while sweeping VG from 0to VDD, and Vth = VDD |Vpi,p|while sweeping VG from VDDto 0. Even though the switching event is delayed in Schmitt-

trigger-like operation with respect to that in a CMOS inverter,

the SGFET inverter features all the advantages of a Schmitt-

trigger operation, such as extremely sharp switching and the

ability to operate in noisy environments.

The variation of the supply current as a function of the input

voltage, corresponding to the voltage transfer characteristic in

Fig. 9(b), is shown in Fig. 9(c). It is noticed that, in this config-

uration, the short-circuit current drawn from the power supplyaround the switching threshold can be considerably reduced

Fig. 9. |Vpi| > |VT,MOS| case. (a) N- and p-channel SGFET transfer char-acteristics in linear scale (|VD| = 1.5 V). (b) Voltage transfer characteristic ofthe complementary SGFET inverter (comparison with the conventional CMOSinverter). (c) Variation of the short-circuit supply current as a function of theinput voltage (comparison with the conventional CMOS inverter). Same param-

eters as in Fig. 8 except W = 510 nm (k = 4.1 N/m) and = 40 J/m2

.

as compared with that of a conventional inverter. This addi-

tional feature reinforces the low-power aspect of the SGFET

inverter.

The SGFET inverter with hysteresis stands as a very promis-

ing static memory cell (SRAM) with considerably reduced

transistor count and a very simple read scheme: The data are

stored at the output node, and they are written by applying logic

0 or 1 to the input. In standby or during read operation,

Vin = VDD/2 is applied, allowing the output to retain its state.In SGFET SRAM, the hysteresis window width is given by

2Vpi VDD and can be adjusted by the circuit designer (by

modifying the beam length W on the layout). In Fig. 10, a volt-age transfer-characteristic example with an enlarged hysteresis

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Fig. 10. Voltage transfer characteristic of the complementary SGFETinverter for |Vpi| |VT,MOS|. Same parameters as in Fig. 8 except

W = 480 nm (k = 4.9 N/m) and = 60 J/m2.

window is shown. This optimized characteristic, enabling a hys-

teresis window width of VDD/2 and centered around VDD/2,is obtained simply by reducing W from 510 nm (Fig. 9) to480 nm (Fig. 10). A large hysteresis window reduces the short-

circuit supply current to a negligible level.

VI. CONCLUSION

SGFET static characteristics and design criteria were ana-

lyzed. Basic formulas for the pull-in and pull-out voltages were

provided, and the SG position is explicitly expressed in terms

of the gate voltage. By using our model, key device parameters

were highlighted, a considerable Ion/Ioff ratio improvementin SGFETs is demonstrated, and the conditions for a low-

power and low-voltage operation are determined. Challenges

related to surface adhesion forces and to strong sensitivity of the

transistor parameters to the beam geometry are also indicated.

The operation and performance assessment of the complemen-

tary SGFET inverter based on the developed analytical model

suggests a significantly reduced OFF-state power dissipation

and an improved functionality as compared to classical CMOS.

Promising applications of the SGFETs include the header and

footer switches for power management and SRAM configura-

tion switches for field-programmable-gate-arrays.

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[37] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed.New York: McGraw-Hill, 1999.

Kerem Akarvardar received the B.S. and M.S.degrees in electrical engineering from Istanbul Tech-nical University, Istanbul, Turkey, in 1996 and2000, respectively, the DEA degree in microelec-tronics from Joseph Fourier University, Grenoble,France, in 2003, and the Ph.D. degree in micro/nanoelectronics from Institut National Polytechniquede Grenoble, Grenoble, in 2006.

He was a Process Engineer with the NationalResearch Institute of Electronics and Cryptology(UEKAE-YITAL), Kocaeli, Turkey, from 1996 to

2000. During his Ph.D. studies, he was with the Institute of Microelectronics,Electromagnetism, and Photonics, Grenoble. He is currently a Postdoctoral Re-searcher with the Center for Integrated Systems, Stanford University, Stanford,CA. His research interests include emerging logic and memory devices, inparticular advanced SOI FETs and NEMS-based devices.

Christoph Eggimann received the B.S. and M.S.degrees in microengineering from the Swiss FederalInstitute of Technology, Lausanne, Switzerland, in2005 and 2007, respectively. He also studied at theUniversity of Waterloo, Waterloo, ON, Canada, andmost recently at Stanford University, Stanford, CA.

He is currently with the Swiss Federal Institute ofTechnology Lausanne, Lausanne, Switzerland. Hisscientific interests include micro- and nanosystemtechnology and analog microelectronics.

Dimitrios Tsamados was born in Athens, Greece,in 1976. He received the B.Sc. degree in physicsfrom the Aristoteles University of Thessaloniki,Thessaloniki, Greece, in 1999, the M.Sc. degree inoptics, optoelectronics, and microwaves from theInstitut National Polytechnique de Grenoble (INPG),Grenoble, France, in 2000, the M.Sc. degree inmicroelectronics from the Universit Joseph Fourier,Grenoble, in 2001, and the Ph.D. degree in micro-and nanoelectronics from the INPG for his workon RF-microelectromechanical-system reliabilityin 2005.

Since September 2005, he has been with the Swiss Federal Institute

of Technology Lausanne, Lausanne, Switzerland, working on suspended-gate field-effect-transistor (FET) numerical simulation and modeling, carbonnanotubenanoelectromechanical systems, and organic FETs.

Yogesh Singh Chauhan received the B.E. degree inelectronics and telecommunication engineering fromthe Shri Govindram Seksaria Institute of Technol-ogy and Science, Indore, India, in 2001, and theM.Tech. degree in microelectronics, very large scaleintegration (VLSI), and display technologies fromthe Indian Institute of Technology Kanpur, Kanpur,India, in 2003, and the Ph.D. degree in compact

modeling of high-voltage MOSFETs from the SwissFederal Institute of Technology Lausanne, Lausanne,Switzerland, in 2007.

During his M.Tech. studies, he was with Samtel India, Ltd., working onthe design of current-programmed active matrix displays. He was with STMi-croelectronics, Noida, India, as an Associate Design Engineer from 2003 to2004, focusing on VLSI I/O library design and validation on MAT10 quality.He was with the European Commission research project ROBUSPIC (ROBUstmixed signal design methodologies for Smart Power ICs) from March 2004 toJuly 2007. He is currently with the Semiconductor Research and DevelopmentCenter IBM, Bangalore, India, as an Advisory Research Engineer. His respon-sibilities include compact modeling of both active and passive semiconductordevices. He is the author or a coauthor of 19 papers in international refereed

journals and conferences. He is also the reviewer ofSolid State Electronics. Hiscurrent research interests include simulation, modeling, and characterization ofsemiconductor devices.

Dr. Chauhan is a member of the IEEE Electron Devices Society. He is

an active Reviewer of IEEE TRANSACTIONS ON ELECTRON DEVICES. Hewas also the Reviewer of the IEEE International Conference of VLSI Designin 2003.

Gordon C. Wan received the B.S degree (with high-est honors) in electrical engineering and mathematicsfrom the University of Texas at Austin, Austin, TX,in 2005, and the M.S.E.E degree from Stanford Uni-versity, Stanford, CA, in 2007, where he is currentlyworking toward the Ph.D. degree in electrical engi-

neering at the Center for Integrated Systems.His research interests include nanoscale physics

and device modeling, including carbon nanotubesand nanoelectromechanical systems.

Adrian Mihai Ionescu (S91M93SM00)received the Ph.D. degree in microelectronics fromthe University Politehnica of Bucharest, Bucharest,Romania, in 1994, and the Ph.D. degree in physicsof semiconductors from the Institut National Poly-

technique de Grenoble, Grenoble, France, in 1997.He was with LETI-CEA, Grenoble, and CNRS,

France, and he was a Visiting Researcher with theCenter for Integrated Systems, Stanford University,Stanford, CA. He is currently an Associate Profes-sor with the Swiss Federal Institute of Technology

Lausanne, Lausanne, Switzerland, where he is the Director of the Laboratoryof Micro/Nanoelectronic Devices and was the Director of the Institute ofMicroelectronics and Microsystems of EPFL from 2002 to 2006. He is theauthor or a coauthor of around 100 research papers. His current researchinterests include the design, modeling, and characterization of submicrometerMOS devices, single-electron devices and few-electron circuit architectures,SOI novel applications, and RF microelectromechanical system.

Dr. Ionescu was appointed as the National Representative of Switzerland forthe European Nanoelectronics Initiative Advisory Council. He received threeBest Paper Awards in international conferences and the Annual Award of the

Technical Section of the Romanian Academy of Sciences in 1994. He served inthe ISQED and IEDM conference technical committees in 2003 and 2004 andas the Technical Program Committee Chair of ESSDERC in 2006.

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Roger T. Howe (F96) received the B.S. degree inphysics from Harvey Mudd College, Claremont, CA,and the M.S. and Ph.D. degrees in electrical engi-neering from the University of CaliforniaBerkeley,Berkeley, in 1981 and 1984, respectively.

After his academic stint with Carnegie MellonUniversity, Pittsburgh, PA, and the MassachussettsInstitute of Technology, Cambridge, from 1984 to

1987, where he held faculty positions, he returnedto the University of CaliforniaBerkeley where hewas a Professor until 2005. He is a currently a

Professor with the Department of Electrical Engineering, Stanford University,Stanford, CA, where he is currently with the Center for Integrated Systems.His research interests include microelectromechanical-system (MEMS) design,micro-/nanomachining processes, and parallel-assembly processes. The focusof his research has been on processes to fabricate integrated microsystems,which incorporate both silicon integrated circuits and MEMS. He has madecontributions to the design of MEMS accelerometers, gyroscopes, electrostaticactuators, and microresonators.

Dr. Howe was a corecipient of the 1998 IEEE Cledo Brunetti Award. He waselected to the National Academy of Engineering in 2005 for his contributions toMEMS processes, devices, and systems. He is the Cofounder of Silicon Clocks,Inc., a start-up company producing timing products.

H.-S. Philip Wong (F00) received the B.Sc. degree(Hons.) in electrical engineering from the Universityof Hong Kong, Kowloon, Hong Kong, in 1982, theM.S. degree in electrical engineering from the StateUniversity of New York, Stony Brook, in 1983,and the Ph.D. degree in electrical engineering fromLehigh University, Bethlehem, PA, in 1988.

He was with the IBM T. J. Watson Research

Center, Yorktown Heights, NY, in 1988. While hewas with IBM, he worked on charge-coupled deviceand CMOS image sensors, double-gate/multigate

MOSFET, device simulations for advanced/novel MOSFET, strained silicon,wafer bonding, ultrathin-body SOI, extremely short gate FET, germaniumMOSFET, carbon-nanotube FET, and phase-change memory. He held variouspositions from Research Staff Member to Manager and Senior Manager. Whilehe was a Senior Manager, he had the responsibility of shaping and executingIBMs strategy on nanoscale science and technology as well as exploratory sili-con devices and semiconductor technology. Since September 2004, he has beenwith Stanford University as Professor of Electrical Engineering. His researchinterests are in nanoscale science and technology, semiconductor technology,solid-state devices, and electronic imaging. He is interested in exploring newmaterials, novel fabrication techniques, and novel device concepts for futurenanoelectronic systems. Novel devices often require new concepts in circuitand system designs. His research also includes explorations into circuits andsystems that are device-driven. His current research covers a broad range of

topics including carbon nanotubes, semiconductor nanowires, self-assembly,exploratory logic devices, and novel memory devices.

Dr. Wong is a member of the Emerging Research Devices Working Group,International Technology Roadmap for Semiconductors. He served on the IEEEElectron Devices Society (EDS) as an elected AdCom member from 2001to 2006. He serves on the International Electron Devices Meeting (IEDM)Committee from 1998 to 2007, was the Technical Program Chair in 2006,and is the General Chair in 2007. He served on the International Solid-StateCircuits Conference (ISSCC) Program Committee from 1998 to 2004 and wasthe Chair of the Image Sensors, Displays, and MEMS Subcommittee from2003 to 2004. He was the Editor-in-Chief of the IEEE TRANSACTIONS ONNANOTECHNOLOGY in 20052006. He is a Distinguished Lecturer of the IEEEEDS and Solid-State Circuits Society. He has taught several short courses at theIEDM, ISSCC, Symposium on VLSI Technology, IEEE International Silicon-on-Insulator Conference, European Solid-State Device Research Conference,and The International Society for Optical Engineering conferences.

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