1 sequential logic lecture #9. sequential logic 2 강의순서 flipflop active-high clock &...
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Sequential LogicSequential Logic
Lecture #9
Sequential Logic 2
강의순서 FlipFlop
Active-high Clock & asynchronous Clear Active-low Clock & asynchronous Clear Active-high Clock & asynchronous Preset Active-high Clock & asynchronous Clear & Preset
Latch Shift Register Counter
4 bits Universal Counter : 74161 Modulo 16 Up counter Modulo 16 Down counter Modulo 16 Up Down counter 0-14 hold Up counter
Sequential Logic 3
FlipFlop with active-high Clock & asynchronous Clear
library ieee;use ieee.std_logic_1164.all;entity dff_1 is port( d, clk, nclr : in std_logic; q : out std_logic );end dff_1 ;architecture a of dff_1 isbegin
process(nclr,clk)begin if( nclr='0') then
q <='0'; elsif(clk'event and clk='1') then
q <= d; end if;end process;
end a;
Sequential Logic 4
FlipFlop with active- low Clock & asynchronous Clear
library ieee;use ieee.std_logic_1164.all;entity dff_fall_1 is port( d, clk, nclr : in std_logic; q : out std_logic );end dff_fall_1 ;architecture a of dff_fall_1 isbegin
process(nclr,clk)begin if( nclr='0') then
q <='0'; elsif(clk'event and clk=‘0') then
q <= d; end if;end process;
end a;
Sequential Logic 5
FlipFlop with active-high Clock & asynchronous Preset
library ieee;use ieee.std_logic_1164.all;entity dff_ preset_1 is port( d, clk, npre : in std_logic; q : out std_logic );end dff_ preset_1 ;architecture a of dff_ preset_1 isbegin
process(npre,clk)begin if( npre='0') then
q <=‘1'; elsif(clk'event and clk=‘1') then
q <= d; end if;end process;
end a;
Sequential Logic 6
FlipFlop with active-high Clock & asynchronous Clear & Preset
library ieee; use ieee.std_logic_1164.all;entity dff_ presetclr_1 is port( d, clk, npre,nclr : in std_logic; q : out std_logic );end dff_ presetclr_1 ;architecture a of dff_ presetclr_1 isbegin
process(npre, nclr, clk)begin if( npre='0') then
q <=‘1'; elsif( nclr='0') then
q <=‘0'; elsif(clk'event and clk=‘1') then
q <= d; end if;end process;
end a;
Sequential Logic 7
Latch
library ieee;use ieee.std_logic_1164.all;
entity latch_1 is port( d, ena : in std_logic; q : out std_logic );end latch_1 ;
architecture a of latch_1 isbegin
process(ena,d)begin if(ena=‘1') then
q <= d; end if;end process;
end a;
Sequential Logic 8
Shift Registerlibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity shiftreg is port( d, clk,nclr : in std_logic; qa,qb : out std_logic );end shiftreg;
architecture a of shiftreg issignal tqa,tqb : std_logic;
beginprocess(nclr,clk)begin if( nclr='0') then
tqa <='0'; tqb <='0';
elsif(clk'event and clk='1') thentqa <= d; tqb <= tqa;
end if;end process;qa<=tqa; qb<=tqb;
end a;
Sequential Logic 9
4 bits Universal Counter: 74161
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity cnt161_4bits is port( d3,d2,d1,d0 : in std_logic; nld,ent,enp : in std_logic; clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic; rco : out std_logic);end cnt161_4bits;architecture a of cnt161_4bits is
signal q : std_logic_vector( 3 downto 0);begin
process(nclr,clk)variable d : std_logic_vector(3 downto 0);begin
d := d3&d2&d1&d0;if( nclr='0') then q <="0000";elsif(clk'event and clk='1') then
if(nld='0') then q <= d;elsif(ent='1' and enp='1') then
q <= q+'1';end if;
end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); rco <= ent and q(3) and q(2) and q(1) and q(0);
end a;
74161 은 실제로 가장 널리 사용되는 4 비트
카운터임
74161 은 실제로 가장 널리 사용되는 4 비트
카운터임
Sequential Logic 10
Modulo 16 Up Counterlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mod16cnt is
port( clk,nclr : in std_logic;
q3,q2,q1,q0 : out std_logic);
end mod16cnt;
architecture a of mod16cnt is
signal q : std_logic_vector( 3 downto 0);
begin
process(nclr,clk)
begin
if( nclr='0') then q <="0000";
elsif(clk'event and clk='1') then
q <= q+'1';
end if;
end process;
q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
Sequential Logic 11
Modulo 16 Down Counterlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mod16dncnt is
port( clk,nclr : in std_logic;
q3,q2,q1,q0 : out std_logic);
end mod16dncnt;
architecture a of mod16dncnt is
signal q : std_logic_vector( 3 downto 0);
begin
process(nclr,clk)
begin
if( nclr='0') then q <="0000";
elsif(clk'event and clk='1') then
q <= q-'1';
end if;
end process;
q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
Sequential Logic 12
Modulo 16 Up Down counter
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity UpDncnt4 is
port( clk,nclr : in std_logic;
UpDn : in std_logic;
q3,q2,q1,q0 : out std_logic);
end UpDncnt4;
architecture a of UpDncnt4 is
signal q : std_logic_vector( 3 downto 0);
begin
process(nclr,clk)
begin
if( nclr='0') then q <="0000";
elsif(clk'event and clk='1') then
if( UpDn='1') then q <= q+'1';
else q <= q-'1';
end if;
end if;
end process;
q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
1 이면 증가
1 이면 증가
0 이면 감소
0 이면 감소
Sequential Logic 13
Modulo 15 Up Counterlibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod15cnt is port( clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic);end mod15cnt;architecture a of mod15cnt is
signal q : std_logic_vector( 3 downto 0);begin
process(nclr,clk)begin
if( nclr='0') thenq <="0000";
elsif(clk'event and clk='1') thenif( q="1110") then
q<="0000";else q <= q+'1';end if;
end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
14에서 0
으로 증가
14에서 0
으로 증가
Sequential Logic 14
0-14 hold Up Counter
library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod15holdcnt is port( clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic);end mod15holdcnt;architecture a of mod15holdcnt is
signal q : std_logic_vector( 3 downto 0);
beginprocess(nclr,clk)begin
if( nclr='0') then q <="0000";elsif(clk'event and clk='1') then
if( q=14) then q<=q;else q <= q+'1';end if;
end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
14에서 정지
14에서 정지
Sequential Logic 15
1bit Async load down counter
Sequential Logic 16
4bit Async load down counter
Sequential Logic 17
1bit Async Sync load down counter
Sequential Logic 18
8bit Async sync load down counter
Sequential Logic 19
State Machine - 강의순서 Mealy Machine
Moore Machine
Sequential Logic 20
State Machine - Mealy Machine Mealy Machine
현재의 상태 (Current State) 와 현재의 입력 (Inputs) 에 의해 출력이 결정
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
Sequential Logic 21
State Machine - Moore Machine Moore Machine
현재의 상태 (Current State) 에 의해 출력 (Outputs) 이 결정
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
Sequential Logic 22
Mealy Machine – VHDL Example
S0
S1
0/00
1/00
0/01 1/10
WindowAct / RiseShot, FallShot
입력 / 출력 1, 출력 2
해석
1. WindowAct 신호가 0 에서 1 로 변하는 순간에 RiseShot 을 1 로 만들고 ,
2. WindowAct 신호가 1 에서 0 로 변하는 순간에 FallShot 을 1 로 만들어야함 ..
해석
1. WindowAct 신호가 0 에서 1 로 변하는 순간에 RiseShot 을 1 로 만들고 ,
2. WindowAct 신호가 1 에서 0 로 변하는 순간에 FallShot 을 1 로 만들어야함 ..
Sequential Logic 23
Mealy Machine–Process 2 개 사용
Library ieee; Use ieee.std_logic_1164.all;
ENTITY RiseFallShot IS
PORT( clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
WindowAct : IN STD_LOGIC;
RiseShot, FallShot : OUT STD_LOGIC);
END RiseFallShot;
ARCHITECTURE a OF RiseFallShot ISTYPE STATE_TYPE IS (s0, s1);SIGNAL state: STATE_TYPE;
BEGINPROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS
WHEN s0 => IF WindowAct='1' THEN state <= s1; ELSE state <= s0; END IF;
WHEN others => IF WindowAct='0' THEN state <= s0; ELSE state <= s1; END IF;END CASE;
END IF;END PROCESS;
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
같은 부분같은 부분
Entity 문에 입출력이 표시 .Entity 문에 입출력이 표시 .
Sequential Logic 24
Mealy Machine–Process 2 개 사용
PROCESS(state, WindowAct)
BEGIN
if( state= s0 and WindowAct='1') then
RiseShot <='1';
else
RiseShot <='0';
end if;
if( state= s1 and WindowAct='0') then
FallShot <='1';
else
FallShot <='0';
end if;
END PROCESS;
END a;
Combination
Logic F/F
Outputs
Current State
Combination
Logic
Next State
Inputs
같은 부분같은 부분
Sequential Logic 25
Mealy Machine–Process 3 개 사용
library ieee;Use ieee.std_logic_1164.all;ENTITY RiseFallShot_v2 IS
PORT(clk : IN STD_LOGIC;reset : IN STD_LOGIC;WindowAct : IN STD_LOGIC;RiseShot, FallShot : OUT STD_LOGIC);
END RiseFallShot_v2;
ARCHITECTURE a OF RiseFallShot_v2 ISTYPE STATE_TYPE IS (s0, s1);SIGNAL State, NextState: STATE_TYPE;
BEGINPROCESS (State, WindowAct)BEGIN
CASE State ISWHEN s0 =>
IF WindowAct='1' THENNextState <= s1;
ELSENextState <= s0;
END IF;WHEN others =>
IF WindowAct='0' THENNextState <= s0;
ELSENextState <= s1;
END IF;END CASE;
END PROCESS;
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
같은 부분같은 부분
Entity 문에 입출력이 표시 .Entity 문에 입출력이 표시 .
Sequential Logic 26
Mealy Machine–Process 3 개 사용
PROCESS(reset,clk)BEGIN
IF reset = '0' THENState <= s0;
ELSIF clk'EVENT AND clk = '1' THENState <= NextState;
END IF;END PROCESS;
PROCESS(State,WindowAct) BEGIN if( State= s0 and WindowAct='1') then RiseShot <='1'; else RiseShot <='0'; end if; if( State= s1 and WindowAct='0') then FallShot <='1'; else FallShot <='0'; end if; END PROCESS;
END a;
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
같은 부분같은 부분
같은 부분같은 부분
Sequential Logic 27
Moore Machine – VHDL Example
S0000
S1010
0
01
1
S2101
1
상태출력
입력 : WindowAct
출력 : y(2:0)
해석
1. WindowAct 신호가 0 에서는 상태의 변화가 없으며 , 1 인 구간에서는 상태의 변화가 S0->S1->S2->S0 로 순환한다 .
2. 출력신호 y(2:0) 은 상태가 S0 인 경우 “ 000” 을 S1 인 경우에는 “ 010” 을 S2인 경우에는 “ 101” 을 출력한다 .
해석
1. WindowAct 신호가 0 에서는 상태의 변화가 없으며 , 1 인 구간에서는 상태의 변화가 S0->S1->S2->S0 로 순환한다 .
2. 출력신호 y(2:0) 은 상태가 S0 인 경우 “ 000” 을 S1 인 경우에는 “ 010” 을 S2인 경우에는 “ 101” 을 출력한다 .
Sequential Logic 28
Moore Machine–Process 2 개 사용Library ieee; Use ieee.std_logic_1164.all;ENTITY MooreMachine ISPORT( clk : IN STD_LOGIC;
reset : IN STD_LOGIC;WindowAct : IN STD_LOGIC;y : OUT STD_LOGIC_vector(2 downto 0));
END MooreMachine;
ARCHITECTURE a OF MooreMachine ISTYPE STATE_TYPE IS (s0, s1,s2);SIGNAL state: STATE_TYPE;
BEGINPROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS
WHEN s0 => IF WindowAct='1' THEN
state <= s1;ELSEstate <= s0;
END IF;WHEN s1 =>
IF WindowAct='1' THENstate <= s2;ELSEstate <= s1;
END IF;WHEN others =>
IF WindowAct='1' THENstate <= s0;ELSEstate <= s2;
END IF;END CASE;
END IF;END PROCESS;
Entity 문에 입출력이 표시 .Entity 문에
입출력이 표시 .
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
같은부분
같은부분
Sequential Logic 29
Moore Machine–Process 2 개 사용
PROCESS(state)BEGIN
CASE state ISWHEN s0 =>
y <= "000";WHEN s1 =>
y <= "010";WHEN others =>
y <= "101"; END CASE;END PROCESS;END a;
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
같은 부분같은 부분
Sequential Logic 30
Moore Machine–Process 3 개 사용Library ieee;Use ieee.std_logic_1164.all;ENTITY MooreMachine_v3 ISPORT( clk : IN STD_LOGIC;
reset : IN STD_LOGIC;WindowAct : IN STD_LOGIC;y : OUT STD_LOGIC_vector(2 downto 0));
END MooreMachine_v3;
ARCHITECTURE a OF MooreMachine_v3 ISTYPE STATE_TYPE IS (s0, s1,s2);SIGNAL state, NextState: STATE_TYPE;
BEGINPROCESS ( State, WindowAct)BEGIN
CASE State ISWHEN s0 =>
IF WindowAct='1' THENNextState <= s1;
ELSENextState <= s0;
END IF;WHEN s1 =>
IF WindowAct='1' THENNextState <= s2;
ELSENextState <= s1;
END IF;WHEN others =>
IF WindowAct='1' THENNextState <= s0;
ELSENextState <= s2;
END IF;END CASE;
END PROCESS;
Entity 문에 입출력이 표시 .Entity 문에 입출력이 표시 .
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
같은 부분같은 부분
Sequential Logic 31
Moore Machine–Process 3 개 사용
PROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN
state <= NextState; END IF;END PROCESS;
PROCESS(state)BEGIN
CASE state IS WHEN s0 =>
y <= "000"; WHEN s1 =>
y <= "010"; WHEN others =>
y <= "101"; END CASE;
END PROCESS;END a;
Combination
Logic F/FInputs
Outputs
Current State
Combination
Logic
Next State
같은부분
같은부분
같은 부분
같은 부분
Sequential Logic 32
참고문헌1. PERRY, VHDL 4/E : PROGRAMMING BY EXAMPLE .
2. FLOYD, DIGITAL FUNDAMENTALS WITH VHDL .
3. ARMSTRONG,GRAY, VHDL DESIGN REPRESENTATION & SYNTHESIS.
4. SKHILL, VHDL FOR PROGRAMMABLE LOGIC .
5. PELLERIN, VHDL MADE EASY.
6. LEE, VHDL CODING & LOGIC SYNTHESIS WITH SYNOPSYS.