8086 lecture notes 14

1THE MOTOROLA 68XXX MICROPROCESSORS

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THE MOTOROLA 68XXX MICROPROCESSORS

14.1 Introduction14.2 Programming Model14.3 Addressing Modes14.4 Instruction Set14.5 The 68XXX Hardware

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14.1 Introduction

The Motorola MC68000 microprocessor was introduced in 1976 in integrated circuit form with an architecture similar to the 6800 family of 8-bit microprocessor and to the DEC PDP-11 family 16-bit minicomputers.

The MC68000 is found in a popular line of personal computers and is also popular for industrial and graphic-intense applications.

Internally, all versions of the 68000 have a 32-bit architecture. However, the external bus widths vary from 16 to 32 bits.

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14.1 Introduction

The MC68000 is the CPU used in Apples Macintosh series of microcomputers.

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14.1 Introduction

The 68000 use a 16-bit data bus and a 24-bit memory address bus and therefore can address only 16 Mbytes of physical memory.

Special instructions added to the 68010 give it virtual memory addressing capability.

The 68020 introduced the 32-bit data bus and a coprocessor interface which supports up to eight coprocessors and added a 256-byte on-chip instruction cache.

The internal design of 68030 is split into two independent 32-bit processors to speed up processing. It also has internal MMU to address the full 4 Gbytes of memory space.

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14.1 Introduction

The 68040 adds an internal floating point arithmetic unit to speed up complex calculations. Its internal design allow the 68040 to carry out many of its instruction execution in a pipeline mode.

The 68060 uses a new superscalar execution technique which allows it to process more than one instruction per clock cycle.

The virtual memory techniques cause information to be loaded from mass storage devices before the information is addressed by the processor.

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14.1 Introduction

Major attributes of the 68XXX processors

Attribute 68000 68010 68020 68030 68040 68060

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14.1 Introduction Performance comparisons of Apple Mac computers

MODEL CPU GRAPHICS DISK MATH PROCESSOR Mac II 0.22 0.19 0.53 0.82 16 MHz 68020 Classic II 0.25 0.15 0.90 0.78 16 MHz 68030 SE/30 0.26 0.16 0.70 0.98 16 MHz 68030 IIcx 0.26 0.25 0.77 0.96 16 MHz 68030 Color Classic+ 0.25 0.23 0.89 1.94 16 MHz 68030 IIsi 0.24 0.31 0.80 0.55 20 MHz 68030 IIsi* 0.32 0.32 0.85 0.83 20 MHz 68030 IIci 0.38 0.39 1.63 1.24 25 MHz 68030 IIci, cache 0.40 0.46 1.69 1.37 25 MHz 68030 PB 170 0.40 0.21 0.69 3.15 25 MHz 68030 LC III 0.43 0.38 0.85 1.50 25 MHz 68030 IIfx 0.71 0.45 0.74 2.97 40 MHz 68030 Co. Cl. 040++ 0.82 0.47 0.88 4.19 25 MHz 68040 C/Q 660av 0.89 1.02 1.44 14.99 25 MHz 68040 Quadra 605 0.88 1.00 1.48 4.69 25 MHz LC040 Quadra 605 0.88 1.00 1.48 14.82 25 MHz 68040 IIci, 040 1.30 1.27 1.71 10.04 40 MHz 68040 PB 540 1.17 0.64 0.84 5.60 33 MHz LC040 PB 540C 1.18 0.75 0.92 6.25 33 MHz LC040 Quadra 700 0.89 1.00 1.89 14.97 25 MHz 68040 Q 700/PPC 2.59 1.28 1.84 86.31 50 MHz 601 Quadra 630 1.18 1.11 2.03 19.86 33 MHz 68040 Quadra 650 1.19 1.34 1.89 20.01 33 MHz 68040 Quadra 950 1.19 1.29 2.85 20.02 33 MHz 68040 Q 950/PPC 3.48 1.63 2.42 115.2 66 MHz 601 6100/60 3.11 1.44 1.23 106.3 60 MHz 601 6100/66 3.40 1.68 1.54 116.5 66 MHz 601 6100/66 L2# 3.43 2.14 1.73 118.4 66 MHz 601# UMAX J700 11.87 n/a** 2.50 531.9 180 MHz 604e iMac Rev. B 15.22 n/a** 2.52 644.7 233 MHz G3 P-Mac G3/266 21.05 n/a** 3.54 745.5 266 MHz G3 S900/G3-333## 25.17 n/a** 2.95 891.1 180 MHz 604e FW iBook 28.25 n/a** 3.24 1016.5 366 MHz G3e PB G4/400 30.61 n/a** 3.35 1124.6 400 MHz G4

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14.1 Introduction Performance comparisons of Apple Mac computers

0 5 10 15 20 25 30 35

Mac IIClassic II

SE/30IIcx

Color ClassicIIsiIisiIIci

IIci, cachePB 170

LC IIIIIfx

Co. Cl. 040C/Q 660av

Quadra 605Quadra 605

IIci, 040PB 540

PB 540CQuadra 700Q 700/PPC

Quadra 630Quadra 650Quadra 950Q 950/PPC

6100/606100/66

6100/66 L2UMAX J700iMac Rev. B

P-Mac G3/266S900/G3-333

FW iBookPB G4/400

Speedometer 4.02 Mac Benchmarks

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14.2 Programming Model

The 68000 internal architecture uses 32-bit buses and registers.

The 68000 external address bus has 23 bits. It can address 8,388,608 16-bit memory location (16-Mbyte memory address space).

All new 68XXX processors, starting with the 68020, have a 32-bit external address bus and can therefore address 4 Gbytes of physical memory.

The 68XXX family programming model is broken down into the user and system sections. The user section is where ordinary tasks run, and the system section is where the full power of the microprocessor is allowed.

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The 68XXX user programming model

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The 68XXX family has seventeen 32-bit registers, a 32-bit program counter (23-bit for the 68000), and a 16-bit status register. Data registers: D0~D7, work in the bit, BCD, byte, word, or

long word modes. Address registers: A0~A7, are used to help calculate the

memory location address. Program counter: PC Condition code register: CCR Seven 80-bit data registers: when floating point unit is used 32-bit control register: when floating point unit is used.

Beside the program counter, all other 16 registers are general-purpose.

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The 68XXX status registerOriginal 6802 flags

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The user and supervisor states provide the protection from user programming error that might contaminate the content of stack or memory.

When the processor is in the supervisor state, you have access to many more instructions and a number of system register in the more advance versions of the 68XXX family of processors

The 68XXX processors are always in one of three major processing states: Normal processing state Program instructions Exception processing state Interrupts Halt processing state Wait for an interrupt

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The 68XXX supervisor programming model

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The 68000 exception states

Type of Cause Exception Type Exception Caused by

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14.3 Addressing Modes

The program counter is used for instruction fetches, and one of the address registers (A0 to A7) is used for data fetches.

The 68XXX processors can address bit, BCD, byte, word, long-word and quad-word data in memory.

There are six different kinds of addressing modes on the earlier processors and nine on the later versions (68020 and later).

All the addressing mode do the same thing: They generate an effective address.

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14.3 Addressing Modes The organization of data in 68XXX memory locations

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14.3 Addressing Modes 68XXX addressing modes by processor type

Addressing Modes Mode 68000 68020, 68030Number 68010 and 68040

Syntax Syntax

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A 68XXX instruction word showing the part used for the instruction, the mode, and register to be used.

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Register direct addressing Data register direct Address register direct

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Register indirect addressing

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Register indirect addressing Address register indirect (mode 010) Address register indirect with postincrement (mode 011) Address register indirect with preincrement (mode 100) Address register indirect with displacement (mode 101)

Address register indirect with postincrement

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Register indirect addressing with displacement

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Indirect addressing with an index

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The program counter with displacement mode

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Relative addressing using a displacement and an index

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The long and short addressing modes

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14.4 Instruction Set The 68XXX processors are upwardly compatible. The 68XXX instructions can grouped into: The data move instructions The integer arithmetic instructions The logical instructions The shift and rotate instructions The bit manipulation instructions The bit field instructions The BCD instructions The program control instructions The floating point instructions The special data movement instructions The supervisory control instructions The trap instructions The special function instructions

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14.4 Instruction Set

The data move instructions Data move instructions Move bytes, words or long words Address move instructions Move words or long words

Mnemonic Description 68000, 68020 6803068010 68040

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14.4 Instruction Set The integer arithmetic instructions


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The logical instructions The TST instruction test the operand by comparing it to zero,

and the status register bits are set. No other results are saved.


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The shift and rotate instructionsMemory shifts and rotates must work on a word. Register shifts and rotates support all operand lengths.


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The bit manipulation instructions Each bit-oriented instructions must have not only an effective

address but also a bit address.Only the status register zero flag is changed by bit operation.


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The bit field instructions The bit field instructions let the programmer work with a

variable-length bit field; that is, the operand can be from 1 to 32 bits long.


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The BCD instructions The BCD instructions let you perform arithmetic operations

(add, subtract, and negate) on byte operands. Packed BCD must be used in BCD instructions PACK and UNPK instructions allow a programmer to convert

ASCII or EBCDIC data string into BCD data or to make BCD data into ASCII or EBCDIC data string.


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The program control instructionsMnemonic Description 68000, 68020 68030

68010 68040

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The floating point instructionsMnemonic Description 68000, 68020 68030

68010 68040

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The special data movement instructions supervisory mode These special data movement instruction introduce the

ability to move blocks of data, multiple registers, and the special function registers.


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The supervisory control instructions supervisory mode The privileged instructions work only when the status

register S bit is set.


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The supervisory control instructions supervisory mode The trap instructions are like interrupts. They cause the

processor to move to the exception processing state.


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The special functions instructions The 68030 processor allows the programmer access to

virtual memory by using address translation tables which are stored in memory.

The most recently used translations are stored in an address translation cache (ATC) in the MMU.

The PFLUSH and PTEST instructions are provided to allow programmer control over the ATC contents.

The 68020 introduced the ability to support multiple processors (one to eight processors).

The CAS, CAS2, and TAS are used to manage multiple processor.

The CASH, CINV, and CPUSH are provided for on-chip cache memory support.

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The special functions instructions


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Implicit instruction addressesInstruction Implied Register

SP (System Stack Pointer)USP (User Stack Pointer)SSP (Supervisor Stack Pointer)

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14.5 The 68XXX Hardware The 68000 and 68010 use a 64-pin package. They

do not use any multiplexed address or data lines. The 68020 and newer processors support a full 32-bit

address bus and a full 32-bit data bus. They are usually packaged in pin grid array package or quad flat pack.

The 68XXX common signals Address bus Data bus Asynchronous bus control Bus arbitration control Interrupt control Bus exception control or system control Processor status or function codes Power, ground, clock

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14.5 The 68XXX Hardware The 68000 logical pinout groupings

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14.5 The 68XXX Hardware A functional pinning breakout for the 68XXX processors

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14.5 The 68XXX Hardware A 114-pin pin grid array package used for 68XXX

microprocessor

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14.5 The 68XXX Hardware A 132-pin quad flat pack

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14.5 The 68XXX Hardware 68XXX processor packages and pin count

Attribute 68000 68010 68020 68030 68040

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14.5 The 68XXX Hardware The 68040 block diagram

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14.5 The 68XXX Hardware The Macintosh II (68020) block diagram

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14.5 The 68XXX Hardware Logic Board Picture for Apple Macintosh Color

Classic

Reference: http://www.micromac.com/

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14.5 The 68XXX Hardware The 68030 and newer processors offer three different

types of bus operation: asynchronous, synchronous, and burst data transfer. The synchronous mode requires the external device to work

at the processor speed rather than telling the processor when it is finished.

The burst data transfer allows a continuous flow of data from memory into the on-chip cache memory until the cache is full.

The asynchronous bus control lines manage exchanges between external devices and the 68XXX address and data buses.

The 68XXX processors support DMA with the three bus arbitration control lines: BR (bus request), BG (bus grant), BGACK (bus grant acknowledge).

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14.5 The 68XXX Hardware There are three interrupt inputs on a 68XXX

processor indicating no interrupt (000) or seven different levels of interrupt priority (001 to 111).

Bits 8, 9, and 10 of a 68XXX status register are called the interrupt priority mask. The programmer can set these bits to indicate the priority level of interrupt of 68XXX processor will recognize.

When a 68XXX processor recognizes an interrupt, it starts an exception processing routine, and the processor is put in the privileged mode. All exception mode processing must be done in the privileged state.

The 68XXX processors use interrupt vectors given by the external interrupt device.

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14.5 The 68XXX Hardware Generating a complete address from the 8-bit

interrupt vector supplied by an external device

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14.5 The 68XXX Hardware 68XXX vector assignments

Vector Hex Address Assignment

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14.5 The 68XXX Hardware 68XXX vector assignments

Vector Hex Address Assignment

8086 lecture notes 14

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