המעבדה למערכות ספרתיות מהירות

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

טכנולוגי - מכון הטכניוןלישראל

חשמל להנדסת הפקולטה

Technion - Israel institute of technologydepartment of Electrical Engineering

Full sniffer system for PCIe

Preliminary Design Review

Performed by: Omer Blecher , Roy Fridman

Instructor: Boaz Mizrachi

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Agenda •Main Goal•Motivation •Multi level level block diagram (sub level goals and risk assessment)•Data flow•Learning stages•Dependencies•Schedule

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Main Goal• Providing a fully operational Sniffer who is able to connect on a PCIe bus ,stream a PCIe packet to a analyzer and perform a complete packet analysis of the signals in an analysis and control PC .• General purpose of project utilizing/modifying existing components of the system and creating missing components for full system integration).

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Why creating a sniffer:• cost effective :

• experiment System available today works in sterile environment and doesn't “feel” real PCIe traffic.

•Can be modified and contain features with educational values

The need for an integration project:

companycompanyPrice of analyzerPrice of analyzer

+/- 58000$+/- 58000$

+/- 30000$+/- 30000$

+/- 30000$+/- 30000$

+/- 45000$+/- 45000$

+/- 45000$+/- 45000$

•utilizes already spent/available lab resources•Verify and modify existing tools

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

System overview

PCI-e MB

PCI-e Card

Sniffing system

x16

x16

x1

x1

x1

x1Sniffing system x16

x1x16

x1

PC

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Block Diagram??

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Vertex II Pro

RS232

RS232 PCIe

Sniffer board

!!

PCIe

PC

I EX

PR

ES

S x16 lin

kPCI-e Card

PCI-e MB

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??

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Data flow

Vertex II Pro

RS232

RS232

Sniffer board PC

I EX

PR

ES

S x16 lin

k

PCIe

PCI-e Card

PCI-e MB

Analysis and control PC

PCIe

startstartstartstart

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

DependenciesSo far the two other groups working on the project are in the following stage:

• Sniffer board (Roee Mesinger): 1. Current stage - starting layout.2. Expected result - a board after assembly on 02/05.3. Date of transfer – 04/06 (after debugging).

• Analyzer core (Danny Volkind and Amir Shmuel): 1. Current stage - finishing simulation in 3 weeks and ready

to start building transmitter. 2. Expected result - basic function tested analyzer on 05/06

3. Date of transfer (if we will fully use the core) - 05/06

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

Learning stages (beginning)

• PCIe protocol (packet analysis) I.P • PCIe physical data transfer (on the connections between the system blocks. I.P

• Predecessor work: Analyzer core,TGA,sniffer board. I.P• investigating known PCI and PCIe analyzers a and sniffers and creating a feature list for feature use . I.P

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

schedule

•Schedule also depends on other groups.•Minimum time spent on project on a weekly base(toghter) – 2 full work days and 6 hour.

•08/01/06 - Presenting final stage of system characterization •04/02/06 - 1. Full report on the design/algorithm of analysis and control PC s/w. 2. Full report on the h/w design/algorithm mostly analyzer related) 3. Start of Debugging stages of the sniffer board with Roee Mesinger. • 01/04/06 – Presenting Part A of the integration project: 1. Full control of all s/w and h/w design and test tools 2. Partly ready chosen architecture of analyzer and analysis and control PC s/w.