תהליך cmos

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

CMOSתהליך

פרופ’ יוסי שחםהמחלקה לאלקטרוניקה פיזיקלית

אוניברסיטת תל-אביב)לפי ההרצאות של יאן ראבאי מברקלי(

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

הכנת הפרוסות והליתוגרפיה הבסיסית

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

CMOSתהליך

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

CMOSדוגמה - מהפך

This two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.

VDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

Layout - תרשים

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

תהליך הייצור

http://tanqueray.eecs.berkeley.edu/~ehab/inv.html.

של פרופ’ אנדי ניורייטר SIMPLהתצוגה מבוססת על התכנית מאוניברסיטת ברקלי.

אינפורמציה מלאה נמצאת באתר:

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

התחלה

Starting wafer: n-type withdoping level = 10 13/cm3

* Cross-sections will be shown along vertical line A-A’

A

A’

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

WELLהגדרת ה-

(1) Oxidize wafer(2) Deposit silicon nitride(3) Deposit photoresist

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

WELLבניית ה-

(4) Expose resist using n-wellmask

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

WELLבניית ה-

(5) Develop resist(6) Etch nitride and(7) Grow thick oxide

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

Nמסוג WELLבניית ה-

(8) Implant n-dopants (phosphorus)

(up to 1.5 m deep)

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

Pמסוג WELLבניית ה-

Repeat previous steps

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

חמצון השער

0.055 m thin

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

תחמוצת השדה

Uses Active Area mask

Is followed by threshold-adjusting implants

0.9 m thick

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

פוליסיליקון

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

השתלת יונים לצמתות

n+ source-drain implant(using n+ select mask)

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

השתלת יונים לצמתות

p+ source-drain implant(using p+ select mask)

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

פתיחת חורים

(1) Deposit inter-level dielectric (SiO2) — 0.75 m

(2) Define contact opening using contact mask

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

- אלומיניום1מתכת

Aluminum evaporated (0.8 m thick)

followed by other metal layers and glass

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

מבנה מתכת מתקדם יותר

Digital Integrated CircuitsAdapted from EECS 141 copyright UCB 1996

Manufacturing ProcessManufacturing Process

הקר בין התרשים למציאות