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Application Note 133

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and maximum currents. Additionally, FET switching speedis uncontrolled, introducing wideband harmonic into themeasurement, potentially corrupting the oscilloscopedisplay.

Closed-Loop Load Transient GeneratorPlacing Q1 within a feedback loop allows true, linear controlof the load tester. Figure 3s conceptual closed-loop loadtransient generator linearly controls Q1s gate voltage toset instantaneous transient current at any desired point,

allowing simulation of nearly any load profile. Feedbafrom Q1s source to the A1 control amplifier closes a loaround Q1, stabilizing its operating point. Q1s curreassumes a value dependent on the instantaneous inpucontrol voltage and the current sense resistor over a verwide bandwidth. Note that once A1 is biased to Q1s coduction threshold (by the DC Load Set), small variatioin A1s output result in large Q1 channel current changeAs such, large output excursions are not required fromA1; its small signal bandwidth is the fundamental speelimitation. Within this restriction, Q1s current wavefois identically shaped to A1s input control voltage, alloing linear control of load current. This versatile capabilpermits a wide variety of simulated loads.

Figure 4 further develops Figure 3, adding new elemen

A gate drive stage isolates the control amplifier from Qgate capacitance, maintaining amplifier phase margand providing low delay, linear current gain. An X10 dferential amplifier provides high resolution sensing acrothe 1m current shunt. The dissipation limiter, actinon the averaged input value and Q1 temperature, shudown gate drive to preclude excessive FET heating asubsequent destruction. Amplifier associated capacitortailor bandwidth and optimize loop response.

INPUTPULSE

(NEGATIVE)

REGULATOROUTPUTVOLTAGEMONITOR

0.001

Q1

AN133 F03

ISWITCHEDAND DC LOADMONITOR

100A REGULATOR UNDER TEST,INCLUDING OUTPUT CAPACITORS

+

+

BASELINE/DC LOAD SET

V

A1

+

Q1

0.001

AN133 F04

TEMPSENSE

FET TEMPINPUT AVG REGULATOR UNDER TEST,INCLUDING OUTPUT CAPACITORSDISSIPATION LIMITER

+

+ SHUTDOWNA1

GATEDRIVESTAGE

INPUTPULSE

(NEGATIVE)

X10

V

BASELINE/DC LOAD SET

Figure 3. Feedback Controlled Load Step Tester AllowsContinuous FET Conductivity Control. Input AccommodatesSeparate DC and Pulsed Loading Instructions

Figure 4. Developed Form of Figure 3. Differential Amplifier Provides High Resolution Sensing Across Milliohm Shunt.Dissipation Limiter, Acting on Average Input Value and FET Temperature, Shuts Down Gate Drive, Precluding ExcessiveFET Heating. Amplifier Associated Capacitors Tailor Bandwidth, Optimize Loop Response

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bandwidth while accommodating phase shift introducedby Q1s gate capacitance and, to a lesser extent, by A3.The FET response adjustment partially compensatesQ1s inherent nonlinear gain characteristic, improvingfront and rear pulse corner fidelity3.

Circuit Testing

The circuit is initially tested using a fixture equipped withmassive, low loss, wideband bypassing shown in Figure 6.Additionally, the importance of exceptionally low inductancelayout in the high current path cannot be overstated. Everyattempt must be made to minimize inductance in the 100Apath; such current density at high speed demands lowinductance if waveform purity is desirable. Figure 7 shows

results with the circuit properly trimmed and a minimizinductance high current path. The 100A amplitude, higspeed waveform is exceptionally pure with just discernibtop-front and bottom-rear corner infidelities4. AC trim ef-fects on waveform presentation are studied by deliberamis-adjustment. Figure 8s overdamped response is typicof excess A1 feedback capacitance. The current pulsewell controlled but edge rate is slow. Figure 9s inadequaA1 feedback capacitance decreases transition time b

Q1

10,000FCOMBINATION OFOS-CON, FILM ANDCERAMIC CAPACITORS

MINIMIZEINDUCTANCE

AN133 F06

MINIMIZEINDUCTANCE

FIGURE 5sCIRCUIT

DC POWER SUPPLY+

20A/DIV

AN133 F07HORIZ = 2s/DIV

Figure 6. Fixturing Tests Figure 5s Dynamic Response. Massive,Broadband Bypassing Combined with Low Inductance LayoutProvides Low Loss, High Current Power to Q1

Figure 7. Optimized Dynamic Response Trims YieldExceptionally Pure, 100A Q1 Current Pulse. Residual Top-Frontand Bottom-Rear Corner Infidelities Are Just Discernable

Note 3:The trimming procedure is not described here in order to maintaintext flow and focus. For detailed trimming information see Appendix B,Trimming Procedure.Note 4:See Appendices A, Verifying Current Measurement and C,Instrumentation Considerations for guidance on obtaining Figure 7sperformance level.

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20A/DIV


20A/DIV


20A/DIV


Figure 8. Overdamped Response Characteristicof Excessive A1 Feedback Capacitor Value

Figure 9. Inadequate A1 Feedback Capacitor DecreasesTransition Time But Promotes Instability. Further CapacitorReduction Causes Oscillation

Figure 10. Corner Peaking Due toOverstated FET Response Compensation

20A/DIV

AN133 F11HORIZ = 500ns/DIV

20A/DIV

AN133 F12HORIZ = 500ns/DIV

Figure 11. Optimized Dynamic Trims Allow 650 NanosecondRise Time, Corresponding to 540kHz Bandwidth

Figure 12. Same Conditions as Figure 11 Show500 Nanosecond Fall Time

promotes instability. Further capacitance reduction willcause loop oscillation because loop phase shift becomesa significant feedback lag5. Figure 10s corner peaking isdue to overstated FET response compensation.

If the AC trims are restored to nominal values, Figure 11sleading edge indicates 650 nanosecond rise time, equiva-lent to 540kHz bandwidth. The trailing edge (Figure 12),taken under the same conditions as the previous figure, issomewhat faster at 500 nanosecond fall time.Note 5: Sorry, no photo available. Uncontrolled 100 Ampere amplitudeloop oscillation is too thrilling for documenting.

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Layout Effects

None of the previous responses, even the mis-compen-sated examples, can be remotely approached if parasiticinductance is present in the high current path. Figure 13

deliberately places only 20nH parasitic inductance in Q1sdrain path. Figure 14a displays enormous waveshapedegradation deriving from the inductance and the loopssubsequent response. A monstrous error dominates

20A/DIV


20A/DIV

HORIZ = 2s/DIV

Figure 14. 1.5"of 0.075"(20nH) Flat Copper Braided Wire Completely Distorts (Figure 14a)Text Figure 7s (Shown Here as Figure 14b) Response. Note 5 Horizontal Scale Change

(14a) (14b)

the leading edge before recovery occurs at the pulsmiddle-top. Additional aberration is evident in the falliedge turn-off. It is especially noteworthy that the photohorizontal scale is 5 slower than Figure 7s optimizedresponse, repeated here for emphasis as Figure 14b. Thlesson is clear. High speed 100A excursions do not toleate inductance.

Q1

10,000FCOMBINATION OFOS-CON, FILM ANDCERAMIC CAPACITORS

MINIMIZEINDUCTANCE

AN133 F13

FIGURE 5sCIRCUIT

DC POWER SUPPLY+

MINIMIZEINDUCTANCE

DELIBERATLYINTRODUCED

20nH PARASITICINDUCTANCE

Figure 13. Deliberately Introduced Parasitic 20nH InductanceTests Figure 5s Layout Sensitivity

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MINIMIZEINDUCTANCE

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FIGURE 5sCIRCUIT

INPUT7V TO 14V LTC3829 BASED 6-PHASE,

1.5V, 120A POWER SUPPLY

+

+

A = 100A/DIV

B = 0.1V/DIV

AC-COUPLED


Note 6:This regulator is conveniently incarnated as LTC demonstrationboard 1675A.

Figure 15. Test Arrangement for LTC3829 Based 6-Phase,120A Buck Regulator Emphasizes Low ImpedanceConnections to Figure 5s Circuit

Figure 16. Figure 5s Circuit Subjects Figure 15s Regulatorto 100A Pulsed Load (Trace A). Response (Trace B) Is WellControlled on Both Edges

Regulator Testing

Regulator testing is possible after the above compensa-tion and layout issues have been addressed. Figure 15describes a test arrangement for an LTC3829 based,

6-phase, 120A buck regulator6. Trace A, Figure 16 showsthe 100A load pulse. Trace Bs regulator response is well

controlled on both edges.

The active loads true linear response and high bandwidthpermit wide ranging load waveform characteristics. Whithe step load pulse shown above is the commonly desired

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REFERENCES

1. Williams, Jim, Load Transient Response Testing ForVoltage Regulators, Linear Technology Corporation,Application Note 104, October 2006.

2. Hewlett-Packard Company, HP-214A Pulse GeneratorOperating and Service Manual, Overload Adjust,Figure 5-13. See also, Overload Relay Adjust, pg.5-9. Hewlett-Packard Company, 1964.

3. Hewlett-Packard Company, HP-214B Pulse GeneratorOperating and Service Manual, Overload Detection/ Overload Switch , pg. 8-29. Hewlett-Packard Com-pany, March, 1980.

APPENDIX A

Verifying Current Measurement

Theoretically, Figure 5s Q1 source and drain current a

equal. Practically, questions center on potential effecof residual inductances and the huge (28000pF!) gatcapacitance of the 1.5m FET specified. If these or othterms impact drain-source current equivalence at speeA3s indicated instantaneous current could be erroneouVerification is necessary and Figure A1 diagrams a methoAn added top-side 1m shunt and its attendant X10 dferential amplifier duplicate the circuits resident bottoside current sensing section. Figure A2s results happieliminate concern over dynamic Q1 current differenceThe two 100A pulse outputs are identical in amplitude a

shape, promoting confidence in circuit operation.

+

+

LT1193

LT1193 F

F

TO FIGURE 5sCIRCUIT

0.001

TO FIGURE 6sCAPACITOR BANKAND DC SUPPLY

0.001

* = 1% FILM RESISTOR

AN133 FA01

BOTTOM-SIDECURRENT

TOP-SIDECURRENT

Q1 4.5k*

4.5k* 432*

432*

100GAIN

100GAIN

A = 50A/DIV

B = 50A/DIV

AN133 FA02HORIZ = 2s/DIV

Figure A1. Arrangement For Observing Q1s Top and Bottom Dynamic Currents

Figure A2. Q1 Top (Trace A) and Bottom (Trace B) CurrentsShow Identical Characteristics Despite High Speed Operation

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APPENDIX B

Trimming Procedure

Trimming Figure 5s circuit is a 7-step procedure which

should be performed in the numerical order listed below.Out-of-sequence adjustments are permissible assumingthe dissipation limiter circuitry is working and adjusted.

1. Set all adjustments to mid-range except A1s feedbackcapacitor, which should be at full capacity.

2. Apply no input, bias Q1s drain from a 1V DC supply,turn on power and trim Base Line Current for 0.5Athrough Q1. Monitor this current with an ammeter inQ1s drain line.

3. Turn power off. Lift Q2s source lead and let it float.This disables the dissipation limit circuitry, leaving Q1vulnerable to damage from inappropriate inputs. Fol- low the remainder of this step in strict accordance with the instructions given.Turn power on, bias Q1s drainfrom a 1V supply and apply a 0.1000V DC input whilemonitoring Q1s drain current with an ammeter. Trim theGain adjustment for a 10.50A meter reading1. Makethis adjustment fairly quickly as Q1 is dissipating 10Watts. Turn power off and reconnect Q2s source lead2.

4. Turn power on with no input applied and Q1s drain

unbiased. Trim the IQ adjustment for +10mV at A2spositive input measured with respect to the 15V rail.Turn off power.

5. Bias and bypass Q1s drain in accordance with teFigure 6. Set the drain DC power supply for 1.5V outpand turn on power. Apply a 1kHz, 1V amplitude, 5wide pulse. Slowly increase pulse width until C1 tripshutting down circuit output and illuminating the PowLimit LED. Tripping should occur at about 12s to15pulse width. If it does not, adjust the Dissipation Limpotentiometer to bring the trip point within these limitThis sets allowable full-amplitude (100A) duty cycleabout 1.5% .

6. Under the same operating conditions as Step 5, seinput pulse width at 10s and adjust A1s capacitivtrim for the fastest positive going edge obtainable A3s output without introducing pulse distortion. Pulsclarity should approach text Figure 7 with somewh

degraded top-front and bottom-rear corner rounding7. Adjust FET Response Compensation to correct t

corner rounding noted in Step 6. Some interaction maoccur with Step 6s adjustment. Repeat Step 6 and until A3s output waveform looks like text Figure 7.

Note 1:The tight trim targets are mandated by trimming gain at only 10%of scale. This is certainly undesirable but less painful than trimming at100% of scale which would force astronomical (and brief) dissipation inQ1 and the milliohm shunt.Note 2: It is worth mention that the primary uncertainty necessitating gaintrimming is the sense lines mechanical placement at the milliohm shunt.

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

t t

1k

AN133 FC01

T1

50

INSULATEDSHELL BNC

INPUT FROMPULSE GENERATOR

TRIGGER OUTPUT

OUTPUT TOOSCILLOSCOPEEXTERNALTRIGGER INPUT

COAXIAL METALENCLOSURE

T1 = ALMOST ANY SMALL PULSE TRANSFORMER1k AND 300pF VALUES ARE TYPICAL

300pF1k

APPENDIX C

Instrumentation Considerations

The pulse edge rates discussed in the text are not particu-

larly fast, but high fidelity response requires some diligence.In particular, the input pulse must be cleanly defined anddevoid of parasitics which would unfairly make circuitoutput pulse shape look bad. The pulse generators pre-shoot, rise time and pulse-transition aberrations are wellout of band and filtered by A1s 2.1MHz (tRISE= 167ns)input RC network. These terms are not a concern; almostall general purpose pulse generators should perform well.A potential offender is excessive tailing after transitions.Meaningful dynamic testing requires a rectangular pulseshape, flat on top and bottom within 1% to 2%. The circuits

input band shaping filter removes the aforementionedhigh speed transition related errors but will not eliminatelengthy tailing in the pulse flats. The pulse generator shouldbe checked for this with a well compensated probe at thecircuit input. The oscilloscope should register the desiredflat top/bottom waveform characteristics. In making thismeasurement, if high speed transition related events arebothersome, the probe can be moved to the band limit-ing 300pF capacitor. This is defensible practice becausethe waveform at this point determines A1s input signalbandwidth.

Some pulse generator output stages produce low level DCoffset when their output is nominally at its zero volt state.The active load circuit will process such DC potentials aslegitimate signal, resulting in DC load baseline current shift.

The active loads input scale factor of 1V = 100A meathat a 10mV zero state error produces 1A of DC baselicurrent shift. A simple way to check a pulse generator fthis error is to place it in external trigger mode and read ioutput with a DVM. If offset is present it can be accountfor, nullified with the circuits baseline current trimanother pulse generator can be selected.

Parasitic effects due to probe grounding and instrumeninterconnection should be kept in mind. At pulsed 100levels parasitic current is easily induced into grounds aninterconnections, distorting displayed waveforms. Probeshould be coaxially grounded, particularly at A3s outpcurrent monitor and preferably anywhere else. Additioally, it is convenient and common practice to externaltrigger the oscilloscope from the pulse generators trigg

output. There is nothing wrong with this, in fact it is reommended to insure a stable trigger as probes are movebetween points. This practice does, however, potentialintroduce ground loops due to multiple paths between thpulse generator, the circuit and the oscilloscope. This cafalsely cause apparent distortion in displayed waveformThis effect is avoidable by using a trigger isolator at toscilloscope external trigger input. This simple coaxcomponent typically consists of isolated ground and signpaths, often coupled to a pulse transformer to provide galvanically isolated trigger event. Commercial examp

include the Deerfield Labs 185 and the Hewlett-Packa11356A. Alternately, a trigger isolator is easily constructin a small BNC equipped enclosure as shown in Figure C

Figure C1. Trigger Isolator Floats Input BNC Ground Using Insulated Shell BNCConnector. Capacitively Coupled Pulse Transformer Avoids Loading Input, MaintainsIsolation, Delivers Trigger to Output. T1 Secondary Resistor Terminates Ringing

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