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EDA-Group APB design 22.6.2012

M hnh mch dy& Cc phn t

nh c bn

Authors: Nguyen Duc Minh

[email protected]

Rev. 0.1

June 22, 2012


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EDA-Group FFT design 22.6.2012

http://edabk.org/ Rev 0.1 ii

This Page is Intentionally Blank


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http://edabk.org/ Rev 0.1 iii

Lch s thay i

Rev. Date Author Description

0.0 16/06/11 Nguyn Tun Anh Nhn yu cu cng vic0.1 17/06/11 Nguyn Tun Anh Bo co phn 1, 2.20/06/11 Nguyn Tun Anh Bo co phn 2,4.21/06/11 Nguyn Tun Anh Bo co phn 3,5.22/06/11 Nguyn Tun Anh Hon thnh 3,5.


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http://edabk.org/ Rev 0.1 iv

Contents

1.1

M T CNG VIC........................................................ ................................................................. ....... 11.2 YU CU KIN THC V CHNG TRNH CNG VIC............................................................................ 2

1.2.1 Yu cu kin thc............................................................................................................. .......... 21.2.2 Chng trnh cng vic........................................................... ................................................... 2

1.3 LM R CNG VIC............................................................................................................ .................. 31.3.1 c im............................................................ ................................................................. ....... 3

2.1 U VO V U RA......................................................................................................................... 112.2 HOT NG........................................................................................................................................ 113.1 TI U................................................................................................................................................ 233.2 CU TRC.......................................................................................................................................... 234.1 DIRECTORY STRUCTURE.......................................................... ........................................................... 294.2 M T TRIN KHAI TNG FILE...................................................... ERROR!BOOKMARK NOT DEFINED.5.1 THIT LP THC NGHIMPHN MM V PHN CNG..................................................... ................ 30

5.2

THC HIN THC NGHIM.................................................................................................................. 30

5.3 K HOCH KIM TRA............................................................... ........................................................... 355.4 KT QU THC NGHIM..................................................................................................................... 36


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http://edabk.org/ Rev 0.1 1

1

Gii thiu

1.1 M t cng vic:

Hc cc khi nim lin quan n mch dy sau:1) Cc phn t nh c bn. Nguyn tc hot ng,cu trc.

- Mch cht

- Mch Flip-Flop: D-FlipFlop, JK-FlipFlop

2) M t mch dy bng my trng thi hu hn (FSM)

- Khi nim mch Mearly, mch More.

- Khi nim th chuyn trng thi.

- Cc khi nim v m ha trng thi.

- Cch trin khai hm Booltrng thi k tip vhm Bool u ra.

3) Cc mch dy c bn. Tm hiu m t k thut (u vo, u ra, trng thi),nguyn tc hot ng v cu trc.

- Mch m

- Mch ghi dch

- B nh ROM v RAM.

- Mch pht hin sn ln (xung) ca 1 tn hiu u vo.

4) Tm hiu cc cu trc Verilog dng m t mch dy. Cc lnh intial, always,cc lnh gn non-blocking v blocking. Cu trc always @(posedge clock) hocalways (@negedge clock).

5) S dng cc cu trc Verilog 4 m t cc mch m, mch ghi dch vmch ROM, RAM tm hiu ti 3.

6) Vit bo co cc kin thc v cng vic lm c.


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1.2Yu cu kin thc v chng trnh cng vic

1.2.1 Yu cu kin thc

Cc yu cu v kin thc cn phi c hc, c trang b:

1. kin thc thit k mch t hp s,2. s dng Modelsim,3. s dng Altera Quartus.

Cc thit b cn dng cng phi c m t phn ny:

1. Cc phn mm thit k tng hp v phn tch mch s Altera Quartus2. Phn mm m phng mch s Modelsim

S ngi v tng thi gian thc hin c nhim v: 1 ngi x 1 tun.

Tham kho ti liu:1) Finite State Machines in Verilog ca UC Berkeley College of Engineering, Departmentof Electrical Engineering and Computer Science.

2) Digital Design and Computer Architecture ca David v Sarah Harris. Chng 3 vChng 4.4.-4.6.

1.2.2 Chng trnh cng vic

Phn ny trnh by nhng bo co nhng mc (milestones) cn t c

Mc Bo co M t Ngithchin

Bt u K hochkt thc Ngy ktthc

1. Yu cu cngvic

Lit k cc yu cu cng vic Minh 16/6/2011 16/6/2011 16/6/2011

3 Lm r nhimv

Cc yu cu nhim v TunAnh

17/6/2011 17/6/2011 17/6/2011

4 c tnh kthut

M t u ra, u vo, bngchn l

18/6/2011 19/6/2011 22/6/2011

5 Ti u mch Ti u mch

6 Trin khaimch

Trin khai mch TunAnh

19/6/2011 21/6/2011 22/6/2011

7 M phngkim tra mch,

phn tch tr, kch thcmch

TunAnh

19/6/2011 21/6/2011 22/6/2011

8 Conclusion Summary and future work TunAnh

22/6/2011 22/6/2011 22/06/2011


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1.3 Lm r cng vic

1) Cc phn t nh c bn. Nguyn tc hot ng, cu trc.Mch cht RS v Flip Flop l cc phn t nh c bn dng trong mch tun t v

kh nng lt li trng thi u ra cn trong mch tun t. Mch cht: l mch c th ci t li, lu gi li trng thi logic ura theo s iu

khin ca trng thi logic uvo. Cu trc:

- Mch gm 2 cng logic Nand hoc Nor mc cho nhau, c 2 u vo l S (set : ci t) v R (reset :ci t li). 2 u ra k hiu l Q ( u ra chnh )v Q( u ra ph, tc l c trng thi logic ngc li vi Q )

- C 2 loi cht RS:+ Nu mch cht c to ra bi 2 cng Nor Cht RS tc ng mc

cao.+ Nu mch cht c to ra bi 2 cng Nand Cht RS tc ng mcthp.

Nguyn tc hot ng: Cht RS tc ng mc cao:

Bng trn l cng NOR:

- Khi thit lp mch cht t R = 0, S = 1:

X Y F

0 0 10 1 0

1 0 01 1 0

R S Q( t+1) Q(t+1)0 0 Q(t) Q(t)0 1 1 01 0 0 11 1 Cm Cm


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Do S = 1 nn Q = 0 bt chp ng cn li Vy ng ra n nh s l Q = 1v Q= 0

- Khi xo mch cht R = 1 v S = 0:Do R = 1 nn Q = 0 bt chp ng cn li Vy ng ra n nh s l Q = 0 v Q=1

- Khi ng vo S= 0 v R=0:V vy khi S=0, R=0 Q = (Q) Trng thi ra khng thay i, tc l trc nh th no th sau vn vy.

- Khi thit lp v xo cng lc S=1, R=1R rng khi ny c 2 cng NOR u c mc vo l 1 nn mc ra l 0, y l iukin khng mong mun v quy c Q v c trng thi logic ngc nhau. Hnna khi S, R tr li mc thp(0) th s khng th d on Q vQ thay i; v vytrng thi ny khng c s dng cn gi l trng thi cm.

Cht RS tc ng mcthp:

- Khi thit lp mch cht t R = 0, S = 1:Do R = 0 nn Q = 1 bt chp ng cn li Vy ng ra n nh s l Q = 0v Q= 1

- Khi xo mch cht R = 1 v S = 0:Do S = 0 nn Q = 1 bt chp ng cn li Vy ng ra n nh s l Q = 1 v Q=

0 - Khi ng vo S= 1 v R=1:V vy khi S=1, R=1 Q = (Q) Trng thi ra khng thay i, tc l trc nh th no th sauvn vy.

- Khi thit lp v xo cng lc S=0, R=0:R rng khi ny c 2 cng NAND u c mc vo l 0 nn mc ra l 1, y l iukin khng mong mun v quy c Q v c trng thi logic ngc nhau. Hnna khi S, R tr li mc cao (1) th s khng thd on Q vQ thay i; v vytrng thi ny khng c s dng cn gi l trng thi cm.

Flip Flop:

- Flip Flop c to ra t cch ghp cc mch cht ng m c (GatedLatch).

X Y F

0 0 10 1 11 0 11 1 0

R S Q( t+1) Q(t+1)

0 0 cm cm0 1 0 11 0 1 01 1 Q(t) Q(t)


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Gated latch: l mch cht RS c them tn hiu xung Clock iu khin qutrnh thay i trng thi.- M hnh:

- Nguyn l hot ng:+ Khi xung Clock = 1, mch cht RS thay i trng thi bnh thng.+ Khi xung Clock = 0, mch cht RS khng thay i trng thi.

Gated Latch hot ng theo mc xung Clock. Gated D Latch: l

- c im: Cht Gated latch c mt u vo d liu D lu gi tr vo dis iu khin ca tn hiu Clk Gated D Latch.

- M hnh:

Flip Flop c to ra bng cch ghp 2 Gated Latch theo kiu Master -Slave.

Cht Master thay i trng thi khi Clk = 1, cht Slave thay i trng thi khiClk = 0. iu ny c c bng cch cp xung Clock tri ngc nhau.

T cch ghp , ta thu c Flip Flop active theo sn ca xung Clock.(C nhiu cch tip cn cc loi Flip Flop t Gated latch, theo em c l c

2 cch ca tc gi Nguyn Trung Lp - TP H Ch Minh tip cn t m hnh


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Gated Latch tng qut v thy Hong Mch Thng t D Gated Latch. Em xintrnh by cch to Flip Flop t D Gated Latch). D Flip Flop:

- M hnh:

-Nguynl

hotng:

T cch ghp trn, ta to ra c Flip Flop D thay i trng thi theosn m xung Clock.

u ra ly gi tr bng u vo D ti mi sn xung nhp. JK Flip Flop:

- M hnh:


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- Nguyn l hot ng:+ Mch JK Flip Flop tc ng theo sn.+ Khi J = K = 0, u ra khng i.+ Khi J= 0, K = 1, u ra Reset v 0.+ Khi J = 1, K = 0, u ra c t l 1. + Khi J = K = 1, u ra lt trng thi.

T Flip Flop:

- Nguyn l hot ng:

+ Mch T Flip Flop tc ng theo sn.+ Khi T = 0, u ra khng i.+ Khi T = 1, u ra lt trng thi.

Ngoi ra, mi Flip Flop c thm cc chn Preset v Clear:


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- Nguyn l:+ Khi Preset = 0, Clear = 1, u ra bng 1 bt chp u cc u vo khc. + Khi Preset = 1, Clear = 0, u ra bng 0 bt chp u cc u vo khc.

Phn bit Latch v Flip Flop: Ging nhau:

- u l cc phn t nh c bn trong mch tun t, c kh nng thit lp,

lu tr, lt li trng thi thi im trc . Khc nhau:

- Latch: tc ng theo mc, c th xy ra cc t hp u vo trng thi cm,c tc nhanh do mch n gin.

- Flip Flop: tc ng theo sn, khng xy ra cc t hp u vo trng thicm, tc chm hn.

Trong mch tun t, thng dng Flip Flop v tnh an ton hn Latch.2) M t mch dy bng my trng thi hu hn (FSM) Mch dy (Mch tun t): l mch m trng thi u ra khng ch ph thuc vo t

hp trng thi u vo m cn ph thuc vo trng thi trc ca mch.- Mch tun t gm 2 loi:

+ Mch tun t ng b: l mch c xung Clock iu khin hot ng camch.+ Mch tun t khng ng b: l mch hot ng khng c s iu khinca xung Clock.

- Mch tun t ng b c thc hin vi mch logic t hp v Flip Flop.- C 2 m hnh biu din mch dy l:

+ M hnh Moore: u ra ch ph thuc vo trng thi hin ti.+ M hnh Mealy: u ra ph thuc vo trng thi hin ti v u vo.


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th chuyn trng thi: L mt th c hng chuyn i t trng thi ny ntrng thi khc ca mch.

- th chuyn trng thi bao gm: Cc trng thi ca mch v cc mi tnchuyn trng thi.+ Cc trng thi gm c: Tn trng thi / Gi tr u ra (Moore), Tn trng

thi (Mealy).+ Cc mi tn chuyn trng thi: Gi tr u vo (Moore), Gi tr u vo /Gi tr u ra (Mealy).

- iu kin:+ Mi trng thi ch biu din duy nht 1 trng thi.+ Mi mi tn chuyn trng thi ch biu din duy nht mt s bin i ttrng thi ny sang trng thi khc.+ Ti mi nh phi m t c tt c cc trng hp c th i ra khitrng thi v ti mt thi im xc nh ch c duy nht 1 cch i ra khinh .

M ha trng thi: th chuyn trng thi ch m t chc nng ca mch, khng m t cch thc

hin, tng hp mch Cn chuyn sang dng bng. Khi c dng bng, tng hp mch, ta thc hin m ha trng thi, theo

nguyn tc m ha:- S bit m ha:

- Mi trng thi c m habng mt t hp trong 2nt hp cc bt m ha.

- C th gn trc tip ty cc t hp vo cc trng thi, tuy nhin cch gnlin quan nhiu n trc ca mch t hp c sau ny nn c mt s quytc c c php gn ti u:+ Cc trng thi c cng trng thi tip theo i vi mt u vo nn gnln cn nhau+ Cc trng thi l trng thi tip theo ca cng mt trng thi nn c gnln cn.

Cch trin khai hm Bool trng thi k tip vhm Bool u ra: Sau khi thc hin php gn, bng trng thi ta c:

+ Trng thi hin ti (KH: y).+ Trng thi k tip (KH: Y).

+ u vo (KH: w).+ u ra (KH: z).

X 2n ( n min )X : S trng thi cn m ha.n : S bit cn thit m ha.


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Cn thc hin tng hp mi quan h hm Boolean gia trng thi k tip vitrng thi hin ti v u vo, u ra vi trng thi hin ti (trong m hnhMoore) hoc trng thi hin ti v u vo (trong m hnh Mealy). V ta csn m hnh dng bng nn vic tng hp hm Bool nn c thc hin ti uha bng phng php ba Karnaugh.

1.3.1 c im

Cc mch dy c bn.Tm hiu m t k thut (u vo, u ra, trngthi), nguyn tc hot ng v cu trc: Mch m: l mch c kh nng m tng hoc m gim theo sn dng chu k

xung nhp.- Ty vo s bit cn dng trong mch, ta c cc mch m tng (gim) theo

cc modulo 2n (n - S bit) Mch thc hin m t0 2n- 1.- C 2 loi mch m l: Mch m ng b v mch m khng ng b.

Mch ghi dch: gm n flip flop dng lu n bit, cho php dch cc bit thng tinsang tri hoc sang phi- Xung Clk c dng cho tt c cc flip flop.

B nh RAM v ROM:- B nh l ni ct gi chng trnh v s liu khi vic tnh ton c thc

hin.- B nh tng ng vi nhiu thanh ghi, mi thanh ghi cha mt t m nh

phn.- B nh c chia lm 2 loi:

+ B nh ch cho php c d liu ROM (Read Only Memory).+ B nh cho php va c va ghi ghi d liu (Random Access

Memory). Mch pht hin sn ln (xung) ca tn hiu vo: L mch mi khi gp sn

dng (01) hoc sn m (10) th mch s m tng ln 1.- VD: My m s ngi i vo trong phng.


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2

M t k thut

Phn ny l c t k thut ca khi c trin khai thit k. Phn ny phi lm r phnjob clarification. Chi tit ha cc yu cu v chun job description thnh cc m t kthut c th. Bao gm:

Mch m: M t k thut

o u vo v u ra:Cng Kch

thcHng Description

Interface: data in outClk, Vo To xung nhp hot ng cho Flip Flop.Preset, Reset. 1 bit Vo Thit lp gi tr ban u cho Flip Flop.z n bit Ra D liu ra: n bit (Din t cc s t 0 2n-1)

o Nguyn tc hot ng:- Mch thc hin vic m trong vng t 0 n 2n-1 (Modulo 2n).- Mch thay i trng thi mi khi gp sn dng xung Clock.- Tn hiu u vo ch nh vic m tng hoc m gim.- M t dng sng:


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o Cu trc mch:


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Mch ghi dch:

M t kthuto u vo v u ra:

Cng Kchthc

Hng Description

Interface: data in outw 1 bit Vo D liu vo: 1 bit ch nh m tng (1),

gim(0).y, Y 2n n

bitTrng thi hin ti v trng thi k tip camch, mch c 2n trng thi, mi trng thic m ha bng n bit.

z n bit Ra D liu ra: n bit (Din t cc s t 0 2n-1)o Nguyn tc hot ng:- Mch c chc nng dch vng n bit t phi sang tri.- Vic dch c thc hin di s iu khin ca xung Clock mi khi gp sn dng.

- Dng song:

o Cu trc:


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B nh RAM v ROM:RAM: B nh cho php va c va ghi ghi d liu.

M t k thuto u vo v u ra: B nh 2n m bit.

Cng Kchthc

Hng Description

Interface: data in out

A n bit Vo D liu vo: u vo n bit nhn d liu v a chca nh.


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CS,OE,WE

1 bit Vo D liu vo: Nhn tn hiu iu khin t Vi x l.- CS: Cho php RAM hot ng.- WE: iu khin vic ghi d liu.- OE: iu khin vic c d liu.

Clk Vo Tn hiu iu khin ng b.

O m bit Vo/Ra D liu vo ra: m bit. Hng vo ng vi vic ghi dliu, hng ra ng vi vic c d liu.

Nguyn tc hot ng:- Mch cho php c d liu trong cc nh t u ra v ghi d liu t bn ngoivo cc nh.- Vic c hay ghi d liu c iu khin theo cp tn hiu:+ c d liu khi CS=OE=1 v WE=0.+ Ghi d liu khi CS=WE=1 v OE=1.+ Khi CS=0, b nh khng hot ng bt chp WE v OE c bng 1 hay khng.- Hot ng ghi hay c d liu c thc hin di s iu khin ca xung C lockmi khi gp sn dng.

Cu trc:


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ROM: B nh ch cho php c d liu.

M t k thuto u vo v u ra: B nh 2n m.Cng Kch

thc

Hng Description

Interface: data in outA n bit Vo D liu vo: u vo n bit nhn d liu a ch

ca nh.CS,OE

1 bit Vo D liu vo: Nhn tn hiu iu khin t Vi xl.

- CS: Cho php ROM hot ng.- OE: iu khin vic c d liu.

Clk Vo Tn hiu iu khin ng b.O m bit Ra D liu vo ra m bit ng vi d liu trong

nh c chn. Nguyn tc hot ng:- Mch cho php c d liu trong cc nh t u.- Vic c d liu c iu khin theo cp tn hiu:

+ c d liu khi CS=OE=1 v WE=0.+ Khi CS=0, b nh khng hot ng bt chp OE c bng 1 hay khng.

- Hot ng c d liu c thc hin di s iu khin ca xung Clock mi khi gpsn dng.

Cu trc:


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Mch pht hin sn ln (xung) ca tn hiu vo: M t k thut

o u vo v u ra:Cng Kch thc Hng DescriptionInterface: data in out

D Vo D liu vo bt k vicc trng thi mc cao thp ngunhin.

U, L 8 bit Ra D liu ra cho bit s ln pht hin thy sn ln vsn xung.

Nguyn tc hot ng:- Mch cho bit s ln d liu vo thay i trng thi ln mc cao v

thay i trng thi xung mc thp.- Khipht hin thy sn dng ca tn hiu, u ra U tng ln 1.- Khi pht hin thy sn m ca tn hiu, u ra L tng ln 1.

Dng sng:


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Cu trc:


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3

Ti u v cu trc mch

Phn ny m t thut ton dng trin khai (di dng lu thut ton) v s khica h thng. Phn s khi phi ch r c cc tn hiu (tham s) truyn gia cc khi(gia cc hm) v nh dng cc tham s .

3.1 Ti u

Trong bi ny, em vit code m phng hot ng trn Quartus v Quartus t tng hpmch. Sau y l cu trc mch Quartus tng hp c.

3.2 Cu trc

Mch m:


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Mch ghi dch:


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Mch RAM:


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Mch ROM:

Mch pht hin sn m, dng ca tn hiu:


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4

Trin khai

Phn ny m t cc trin khai bi ton. Bao gm cc vic sau:

Cu trc v phn chia cc file, cc th mc lin quan n projects: cc file m ngun, ccfile cu hnh, cc file documents

M t c th tng file trin khai, nhn mnh vo nhng im cn ch .

4.1 Directory structure

Mch m:

- B cng.

Mch ghi dch:

- B dch bit sang tri, sang phi. RAM, ROM:

- B Mux, chn c iu kin tha mn.

Mch pht hin sn dng, sn m:

- Mch m.


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5

Thc nghim v kim tra

Phn ny m t cc tools v software, hardware c s dng cc bc c th thitlp mi trng v thchin li bi ton (di dng tutorial)

5.1 Thit lp thc nghim Phn mm v phn cng

Trong bi ny, em s dng 2 ngn ng mo t phn cng Verilog HDL v VHDL mphng cc mch dy trn.

5.2 Thc hin thc nghim

Mch m:Code Verilog:

module Count ( Clk,Q,Rst,Prst );input Clk,Rst,Prst;output[3:0] Q;reg[3:0] Q;always @(posedge Clk or posedge Rst or posedge Prst) begin

if( Rst == 1'b1 ) beginQ = 4'b0;

end else if( Prst == 1'b1 ) beginQ = 4'b1;end else begin

Q = Q + 1;//Neu dem giam thi Q=Q-1;end

endendmodule

Code VHDL:

library ieee;

use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;


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entity Count isport( Clk :in std_logic;

Q :buffer std_logic_vector( 3 downto 0);

Rst, Prst :in std_logic);

end Count;architecture Behavior of Count is begin

process( Clk, Rst, Prst )begin

if( Prst = '1' ) thenQ


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Q(1)


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end if;end if;

end process;process( Clk, CS, OE, WE ) begin

if( Clk'event and Clk = '1' ) then

if( CS='1' and OE='0' and WE='1' ) thenmem(conv_integer(Add))


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if( CS='1' and OE='1' ) thenData


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5.3 K hoch kim tra

Mch m:Testbench:

module tb_Count ();reg Clk,Rst,Prst;wire[3:0] Q;

parameter time_out = 300;Count C1 ( .Clk(Clk), .Q(Q), .Rst(Rst), .Prst(Prst) );initial #time_out $finish;initial begin

Clk = 0;forever #5 Clk = ~Clk;

end

initial beginRst = 0;Prst = 0;#200 Rst = 1;#10 Rst = 0;#50 Prst = 1;#10 Prst = 0;

endendmodule

Mch ghi dich:

Testbench:module tb_ShiftReg ();

reg Clk, Rst;wire[3:0] Q;

parameter time_out = 300;ShiftReg C1 ( .Clk(Clk), .Rst(Rst), .Q(Q) );initial #time_out $finish;initial begin

Clk = 0;forever #5 Clk=~Clk;

end

initial beginRst = 0;#200 Rst = 1;

endendmodule

Mch ROM, RAM: Phn mch ny em cha m phng trn Modelsim c do khim phng kt qu ra khng nh mong mun, vic ghi cn ph thuc vo cc nhmem bn trong

Mch pht hin sn dng, m ca tn hiu vo:

Testbench:


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module tb_phlx ();reg D;wire[7:0] U , L;

parameter time_out = 200;phlx P1 ( .D(D), .U(U), .L(L) );

initial #time_out $finish;initial begin

D = 0;forever #5 D = ~D;

endendmodule

5.4 Kt qu thc nghim

Cc kt qu thc nghim.

Mch m:

Mch ghi dch:


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Mch pht hin sn xung:


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Ch mcThis section contains an alphabetical list of helpful document entries with theircorresponding page numbers.

- Slide MinhNDk39_MoHinhHoaMachLogicTohop.

- Slide in t s - TS Hong Mnh Thng.

- in t s -ng Vn Chuyt.

- www.google.com.vn

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