bai tap vhd

7/31/2019 bai tap VHD

1/15

THI MN THIT K H THNG STrnh : Cao ngThi gian: 45 phtChng trnh c vit v m phng trn phn mm Active- HDL

1. Thit k v m phng Flip-Flop DFF ng b tn hiu reset.1b. DFF c enable.2. Thit k v m phng Flip-Flop DFF khng ng b tn hiu reset3. Thit k v m phng Flip-Flop JKFF ng b tn hiu reset.4. Thit k v m phng Flip-Flop JKFF khng ng b tn hiu reset.5. Thit k v m phng Flip-Flop RSFF ng b tn hiu reset.6. Thit k v m phng Flip-Flop RSFF khng ng b tn hiu reset.7. Thit k v m phng mch c 3 u vo A, B, C khi hai trong 3 u vo c gi tr

bng mt th u ra mang gi tr bng 1.8. Thit k v m phng mch 3 trng thi.9. Vit chng trnh v m phng chc nng ca IC 74139 ( vit bng cc lnh song

song).10. Vit chng trnh v m phng chc nng ca IC 74139 ( vit bng cc lnh ni

tip).11. Vit chng trnh v m phng chc nng ca IC 74138 ( vit bng cc lnh song

song).12. Vit chng trnh v m phng chc nng ca IC 74138 ( vit bng cc lnh ni

tip).13. Thit k v m phng mch m tin vi Kd bt k.14. Thit k v m phng mch m li vi Kd bt k.15. Thit k v m phng b ghp knh 4-116. Thit k v m phng b ghp knh 8-117. Thit k v m phng b phn knh 1-418. Thit k v m phng b phn knh 1-819. Vit chng trnh thit k v m phng b so snh 4 bit20. Thit k v m phng thanh ghi dch c di 4 bit21. Vit chng trnh thit k v m phng b cng n bit22. Vit chng trnh thit k v m phng chuyn m BCD sang LED 7 thanh.23. Vit chng trnh thit k v m phng chuyn m BCD sang thp phn.24. Vit chng trnh thit k v m phng chuyn m HEX sang LED 7 thanh.25. Vit chng trnh thit k v m phng kim tra tnh chn l ca chui n bit26. Vit chng trnh thit k v m phng thc hin b ALU 8 bit vi 2 u vo 8 bit

v tn hiu iu khin c chc nng nh sau:a. Thc hin php cng khi u vo iu khin nhn gi tr 00.b. Thc hin php tr khi u vo iu khin nhn gi tr 01.c. Thc hin php ton AND khi u vo iu khin nhn gi tr 10d. Thc hin php ton OR khi u vo iu khin nhn gi tr 11.

27. Vit chng trnh thit k v m phng m s s 1 trong chui u vo 8 bit.28. Vit chng trnh thit k v m phng m s s 0 trong chui u vo 8 bit.29. Thit k v m phng b chia tn s vi h s chia bt k..30. Thit k b m ha 3-8.


2/15


3/15

END IF;END PROCESS;

END behavior;

Bai tap 4:JK KHNG NG B

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity jk isport(clk : in STD_LOGIC;

rst : in STD_LOGIC;x : in STD_LOGIC_VECTOR(0 to 1);y : buffer STD_LOGIC );

end jk;architecture jk of jk isbegin

process(clk,rst)variable temp: std_logic;begin

if(rst='1') then temp:='0';elsif(clk'event and clk='1')then

if(x="00") then temp:=temp;elsif (x="01")then

temp:='1';elsif(x="10")then

temp:='0';elsif(x="11")then

temp:=not temp;end if;end if;y


4/15

variable temp:std_logic;wait until (clk'event and clk='1');

beginif (rst='1')then

temp:='0';

elsif (clk'event and clk='1')thenif(r='0'and s='0')thentemp:=temp;

elsif(r='0'and s='1')thentemp:='0';

elsif(r='1' and s='0')thentemp:='1';

elsif(r='1' and s='1')thentemp:='Z';

end if;end if;

qyyyy


5/15

end mach;architecture mach of mach isbeginy'Z');

end mach; BI TP 9:LS 139 (THEO KIU SONG SONG)library IEEE;use IEEE.STD_LOGIC_1164.all;entity ls is

port(x : in STD_LOGIC_VECTOR(2 downto 0);y : out STD_LOGIC_VECTOR(3 downto 0) );

end ls;architecture ls of ls isbegin

process(x)begincase x is

when "000"=>yyyyyYYYYYYY


6/15

when"001111"=>YY


7/15

end if;end if;q


8/15

b when sel="01" elsec when sel="10" else

d;end mux;

BI TP16: MUX 8-1ibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux8_1 is

port( a : in STD_LOGIC;b : in STD_LOGIC;c : in STD_LOGIC;d : in STD_LOGIC;e : in STD_LOGIC;f : in STD_LOGIC;

h : in STD_LOGIC;g : in STD_LOGIC;sel:in std_logic_vector(2 downto 0);y : out STD_LOGIC );

end mux8_1;architecture mux8_1 of mux8_1 isbeginy


9/15


10/15

use IEEE.STD_LOGIC_1164.all;

entity thanhghi isgeneric (n:integer :=4);port( d : in STD_LOGIC;

clk : in STD_LOGIC;rst : in STD_LOGIC;q : out STD_LOGIC);

end thanhghi;architecture thanhghi of thanhghi issignal temp :std_logic_vector (n-1 downto 0):="0000";begin

process(clk,rst)begin

if(rst='1')thentemp'0');

elsif (clk'event and clk='1')thentemp


11/15

BI TP 22:BCD LED

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity chyendoi isport(

x : in STD_LOGIC_VECTOR(3 downto 0);y : out STD_LOGIC_VECTOR(6 downto 0)

);end chyendoi;architecture chyendoi of chyendoi isbeginy


12/15


13/15


14/15

variable temp:integer range 0 to 8;begin

temp:=0;for i in 0 to 7 loop

if (a(i)='1')then

temp:=temp+1;end if;end loop;q


15/15

y '1');temp2:= 0;if (ena='1')then

for i in sel'range loopif (sel(i)='1')thentemp2:=2*temp2+1;

elsetemp2:=2*temp2;

end if;end loop;temp1(temp2):='0';

end if;x

bai tap vhd

Documents