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1 Chapter 2 Chapter 2 Interconnection Technology Interconnection Technology (Zero (Zero - - level package) level package)

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Page 1: Chapter 2m09408034/cae/semiconductor/Chapter 2... · chip Technology. 23 Why Need FC Technology ? 24 ... using the diamond blade turning at high speed Inner Lead Bonding Process of

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Chapter 2Chapter 2Interconnection TechnologyInterconnection Technology

(Zero(Zero--level package)level package)

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Introduction of Wire Bond TechnologyIntroduction of Wire Bond Technology

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Category of Wire BondCategory of Wire Bond1957, Bell Lab.

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Category of Wire BondCategory of Wire Bond

銲接種類 超音波銲接Ultrasonic Bonding

熱壓銲接Thermocompression

Bonding

熱音波銲接Thermosonic

Bonding能量種類 超音波 熱、壓力 熱、壓力、超音波

線材 Al-1%Si銲線 Au銲線 Au銲線

打線條件

溫度 室溫 330 ~ 350℃ 150 ~ 200℃

荷重 小 大 中

時間 0.4 ~ 0.6 s/wire 0.15 ~ 0.4 s/wire 0.1 ~ 0.3 s/wire

超音波 有 無 有

方向性 有 無 無

備考 使用純鋁線 過去使用 目前使用

1. Wire diameter: 25 ~ 75 um (1~3 mil)2. Sonic frequency: 20~120 kHz

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Thermosonic Thermosonic BondingBonding

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Thermosonic Thermosonic BondingBonding

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Ultrasonic BondingUltrasonic Bonding

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Ultrasonic BondingUltrasonic Bonding

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Qualification CheckQualification Check

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Qualification CheckQualification Check

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WB QFP Process FlowWB QFP Process Flow

Wafer Saw Die Bonding

Molding

Wire BondingTrimming & Forming

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WB QFP/BGA Process FlowWB QFP/BGA Process Flow

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WB Package FamilyWB Package Family

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Introduction of FlipIntroduction of Flip--chip Technologychip Technology

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Why Need FC Technology ?Why Need FC Technology ?

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Advantages of Flip ChipAdvantages of Flip Chip

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Advantages of Flip ChipAdvantages of Flip Chip

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What is Flip Chip ?What is Flip Chip ?

With underfill FC: organic substrateWithout underfill FC: ceramic substrate

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Bumping Process (Evaporation)Bumping Process (Evaporation)

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Bumping Process (Electroplating)Bumping Process (Electroplating)

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Bumping Process (Printing)Bumping Process (Printing)

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FC BGA/CSP Process FlowFC BGA/CSP Process Flow

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FC Assembly FlowFC Assembly Flow

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Wafer thickness: 6~8 mils (152.4~203.2 um)12’ wafer: may not have backside grinding due to avoid wafer crack

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FC Assembly FlowFC Assembly Flow

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FC Assembly FlowFC Assembly Flow

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FC Assembly FlowFC Assembly Flow

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FC Assembly FlowFC Assembly Flow

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Reflow ProfileReflow ProfileEutectic solder 240 CLead free solder 260 C

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FC Family PackagesFC Family Packages

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Introduction of Tape Automatic Introduction of Tape Automatic Bonding TechnologyBonding Technology

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Application of TCP Packaging TechnologyApplication of TCP Packaging Technology

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Definition of TCPDefinition of TCP

‘TCP’ is a connection technique for attaching Au bumped semiconductor die to the tape (polyimide film which is patterned with conductor).

• TCP : Tape Carrier Package• COG : Chip On Glass• TAB : Tape Automated Bonding

TCP ( Tape Carrier Package )

Flex Hole Flex CoatAdhesive ICBump

Solder Resist

Base Film

Cu

3 layer Flm

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LCM Module LCM Module

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TCP Cross Section TCP Cross Section

BASE Film - Upilex-S- Thickness : 75um

Adhesive- Toray#7100,#8200, TomegawaE,X- Thickness : 12um

Au Bump- Thickness : 15~25um- Ave : 18 um

Drive IC

Solder Resist- AE-70-M11- AR7100- CCR232GF- SPI1000- Thickness : 20+/-15um

Tin Plating ( Sn )- Thickness : 0.2+/-0.1um

ILB Bond

POTTING- Epoxy Resign

Copper ( Cu )- FQ-VLP- FX-VLP- 3EC-VLP- SLP- Thickness : 15, 18, 25um

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TCP Tape Structure TCP Tape Structure

Input outer leadAlignment Hole

Sprocket Hole

Test pads for output signal

Inner lead

OLB AlignmentMark

Cut-linefor User Application

Slit hole(Bending Position)

ILB AlignmentMark

Solder resist Area

Product Name

TP

Output outer lead

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Tape Design Tape Design

Tape width: 35W, 35SW, 48W, 48SW, 70W

Perforation: 2pf, 3pf, 4pf, 5pf,………

Min. pitch: 45um, 50um, 55um,…….

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Tape Manufacture Tape Manufacture

Puncher Mask for tape O/S checker

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Gold Bump Process Gold Bump Process

LSI WAFER

RESIST Coating

UBM Sputtrting

RESIST Patterning

UBM ETCHING

RESIST Stripping

Au PLATING

- Provide the proper metallurgy for the ILB- Provide a standoff preventing the TAB lead

from shorting to the edge of the die- Protect the underlying aluminium from

corrosion or contamination

Passivation UBM(Ti/w)

BUMP

Bump SizeBump Clearance

Pad Metal (Al)

Bump Height

The Purpose of BUMP

Control Factors- Bump Height & Hardness- Bump Shear Strength- Bump Size & Shape [Flatness]

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Wafer Testing Wafer Testing

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Process Flow of TCPProcess Flow of TCP

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Process Flow of TCPProcess Flow of TCP

DicingProcess of cutting the water into pieces by using the diamond blade turning at high speed

Inner LeadBonding

Process of combining gold bump and inner lead of film on the basis of appropriate time, pressure, and temperature by using the ILB tool.

Potting Process of spreading the liquid resin on the surface of the chip to protect it.

Test Process of probing the electrical condition of products.

VisualInspection

Process of packing products and finally checking the outer condition of the product

MarkProcess of printing a character on the surface of the device which is potted. The character is composed of the device name and production work week.

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ILB ( Inner Lead Bonding ) ILB ( Inner Lead Bonding )

Inner Lead Bonding is to form a strong metallugical bond between the die (bump) and the carrier tape (plated copper with Sn or Au)

Bond ForceBond TimeBond TempStage Temp

Bump Height & Bump HardnessBump Shape & Contamination

Thermode FlatnessThermode Temperature StabilityRecognition & Alignment Accuracy

Inner lead Width & ThicknessPlating Thickness[Pure Sn]

Parameter Control Factors

Eutectic Bond / Gang Bond (Constant Heat)

Bonding Method

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Potting ProcessPotting Process

Pre Cure : 120℃ / 25min Post Cure - 5020 : 120℃ / 4hr- 8151 : 150℃ / 1hr

Chip coat viscosity & Inner lead PitchTape Warpage Cure ConditionNeedle SizeNeedle Height & SpeedPressure

Epoxy Type Chip coatType : 5020(HITACHI) / 8151 (NAMICS)

Coating Pattering(Teaching points)Dispensing SpeedPressure

Parameter Control Factors

Cure Condition

Material

Potting is a process to encapsulate IC in order to protect inner lead bonded ICfrom external contamination or mechanical stress.

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Marking Process Marking Process

Marking is to print a character on the surface of the device which is potted.The character is composed of the device name and production work week.

UV Cure Time

Tape WarpageUV Cure ConditionPosition Sensor / Clamp Alignment Location

Ink : 9065 (Markem)

Laser SpeedLaser FrequencyPower ( Intensity of Laser )

Parameter Control Factors

Material

Ink Marking

Laser Marking

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Final Testing Final Testing

• F/T probe card

• F/T push plate

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FMEA SystemFMEA System

Failure Analysis System

Decap Equipment X-RaySEMEDXCross Section

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TCP Family PackagesTCP Family Packages