ee2169_lab5_spring2012v3

8/2/2019 EE2169_Lab5_spring2012v3

1/4

UTEP Electrical and Computer Engineering Department

EE2169 Laboratory for Digital Design I

LAB #5

NAND & EPROM BCD to 7-Segment Decoder

INTRODUCTION

Design a BCD to seven-segment display combinatorial converter using the 4 least significantswitches as inputs and the right hand digit on the 7 segment display as the output on the BASYS2 board.

Use an EPROM in the schematic capture first for all 7 outputs. Then implement two out of the sevenoutput functions b and d in the system using NAND gates. The pin out of the FPGA is shownbelow.

8/2/2019 EE2169_Lab5_spring2012v3

2/4

PRE-LABA seven-segment display is made out of seven LEDs, which are identified by the letters

a, b, c, d, e, f and g. Figure 1 shows what this display looks like and where each LED is located.

Hexadecimal digits are represented with symbols from 0 to F. The problem presented requires

binary inputs using 4 bits (W, X, Y and Z). The 4 inputs will be fed into a logic function andused to obtain the corresponding combination of the seven output values (a, b, c, d, e, f , g).

Figure 1: Seven-Segment Decoder

Table 1 below, presents an example of how the truth table for this system should look

like. It uses the example taken from figure 1 in which the decimal number 8 is depicted on theBCD display by turning ON all the segments.

Do the following for your pre-lab:

1. Fill in the truth table (Table 1) for your pre-lab in this manner (assuming ones turn onthe segments). Make sure you display the numbers as shown on the seven-segment

display below.2. Fill another truth table assuming a zero turns the segment on and a one turns it off

(for number 8 that means the whole row will have zeros instead of ones). Again

display the numbers as shown on the seven-segment display below.3. Simplify the circuit using k-maps. Remember to use the dont care terms.4. Draw the circuit diagram using AND-OR gates (for both tables).5. From AND-OR circuit create a NAND-NAND circuit (for both tables).6. Complete the ROM table below by entering the output values for the remaining input

patterns.

Keep in mind that ALL the input combinations for W, X, Y and Z must be includedin the table but use dont cares to optimize the logic. The converter does not need

to convert A-F only the digits 0-9.
http://www.engr.colostate.edu/~dga/mechatronics/figures/6-34.gif

8/2/2019 EE2169_Lab5_spring2012v3

3/4

Table 1: Seven-Segment Decoder Truth Table

W X Y Z Hex a b c d e f g

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9

1 0 1 0 NoneX X X X X X X

1 0 1 1 None X X X X X X X





W X Y Z a b c d e f g

Table 2.Mapping table for I/Orelation in EPROM

8/2/2019 EE2169_Lab5_spring2012v3

4/4

Seven-segment number display

LABORATORY

Description

Use the schematic entry tool to create a BCD to 7 Segment Display convertor. Use theEPROM for 5 of 7 lines and NAND-NAND logic to perform the remaining two lines. Synthesis

the design and download to the BASYS2 board to demonstrate to the TA.

Procedure

Using NAND circuits:

a. Construct function b and dusing schematic capture map the pre-lab circuit diagram (theone the TA chooses, either the one that turns the segments with ones or the one withzeros) in the Xilinx design environment.

b. Perform waveform verification using Isimc. Program FPGA on Basys2 board and verify functionality in hardware.

ee2169_lab5_spring2012v3

Documents