ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

FPGA Lab

Speaker : 鍾明翰 (CMH)

Advisor: Prof. An-Yeu Wu

Date: 2010/12/14

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P2

Objective

In this Lab, you will learn the basic set-up and design

methods of implementing your design by ISE 10.1.

Create a New Project

Add HDL Source & Check Syntax

Create Timing / IO Constraint

Implement Design and Verify Constraints

Download Design to the FPGA Board

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P3

Reference Design

A 26-bit counter

Can be used as frequency divider

Counter

(Frequency divider)

clk (33MHz)

rst

out1 (count[25])

～1Hz

out2 (count[24])

～0.5Hz

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P4

Reference Design

Verilog Code (counter.v)

module counter (clk, rst, out, out2);

input clk;

input rst;

output out;

output out2;

reg [25:0] count;

wire out, out2;

assign out = count[25];

assign out2 = count[24];

always@(posedge clk or posedge rst) begin

if(rst)

count <= 26'd0;

else

count <= count + 26'd1;

end

endmodule

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P5

Starting the ISE Software

Start->All Programs->Xilinx ISE 10.1->Project

Navigator

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P6

Create a New Project

Select File->New Project

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P7

Create a New Project

2.Verify that HDL is selected from the

Top-level Source Type list

1.Enter Project Name

3.

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P8

Create a New Project

Fill in the properties in the table

Product Category: ALL

Family : Virtex 5

Device: XC5VLX110T

Package:FF1136

Speed:-3

Source Type: HDL

Synthesis Tool: XST

Simulator:

Modelsim –SE Verilog

Prefered Language :

Verilog

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P9

Add HDL Source

Project->Add Source

Add counter.v to project

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P10

Add HDL Source

1.Double click on source file

2.You can edit your source file here

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P11

Syntax Check

You’ll get a green check if your code has no errors

Double Click on

“Check Syntax”

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P12

Create Timing / IO Constraint

Create Timing Constraint

Double Click on “Create Timing

Constraint”

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P13

Create Timing / IO Constraint

Click on “Yes” to create UCF file

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P14

Create Timing / IO Constraint

1. Set Clock period: 30ns

2. Save UCF file

3. Close Timing Constraint

setting (right click -> close)

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P15

Create Timing / IO Constraint

You can also edit UCF file manually

Content of counter.ucf

use “Add source” to add ucf file to your project

NET "clk" TNM_NET = clk;

TIMESPEC TS_clk = PERIOD "clk" 30 ns HIGH

50%;

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P16

Create Timing / IO Constraint

I/O Constraint (Pin Assignment)

Double Click on “Floorplan IO”

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P17

Create Timing / IO Constraint

Pin assignment

For different IO setting, see reference[2]

1.Enter pin location

2..Save

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P18

Implement Design and Verify Constraints

Implement the design and verify that it meets the timing

constraints specified in the previous section

Right Click -> RUN

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P19

Implement Design and Verify Constraints

Design Summary

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P20

Download Design to the FPGA Board

1.Connect the 5V DC power cable to the power input on the FPGA

board

2.Connect the download cable between the PC and FPGA board

3.PC will configurate FPGA driver automatically

FPGA download cable connector

5V DC power cable connector

Switch

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P21

Download Design to the FPGA Board

Generate Programming File

Right Click -> RUN

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P22

Download Design to the FPGA Board

Right click on ”Configure Target Device”->RUN

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P23

Download Design to the FPGA Board

Make sure your FPGA board is

connected to the PC, then click “finish”

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P24

Download Design to the FPGA Board

Click on “Bypass” for the first four targets, and select

“counter.bit” for the last one (xc5vfx110t)

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P25

Download Design to the FPGA Board

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P26

Download Design to the FPGA Board

Right click on target device “xc5vfx110t”->Program

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P27

Download Design to the FPGA Board

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P28

Download Design to the FPGA Board

If it shows “Program Succeeded”, your design has

been download to the FPGA board correctly.

Check FPGA to see whether your design works or not.

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P29

Check point

Rst

GPIO Switch1

Counter(Frquency Divider) on FPGA

out0 /out1

GPIO LED0/GPIO LED1

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P30

Reference

[1] ISE quick start

[2] XUPV5-LX110T User Manual

http://www.xilinx.com/products/boards/ml505/docs.htm