Design of a 4th Order LP ∑Δ Modulator−What About Non-Idealities?

F. Sandoval-Ibarra #1, D. Calderón-Preciado#2, J. G. García-Sánchez #3, E. Ch. Becerra-Álvarez *4 # Cinvestav, Unidad Guadalajara

Av. del Bosque 1145, 45019 Col. El Bajío, Zapopan, Mexico 1 sandoval@gdl.cinvestav.mx

2 dcalderon@gdl.cinvestav.mx 3 ggarcia@gdl.cinvestav.mx

* Centro Universitario de Ciencias Exactas e Ingeniería-Universidad de Guadalajara Blvd. Gral. Marcelino García Barragán 1421, Col. Olímpica, 44450 Jalisco, Mexico

4 edwin.becerra@cucei.udeg.mx

Abstract—This modulator, a cascade hybrid proposal, takes

advantage of both Continuous Time (CT) and Discrete Time (DT) approaches. In order to define a set of specifications Processing Basic-Blocks (PBBs) are firstly analyzed with the help of SIMSIDES. After that transistor-based simulations are carried out not only to verify fulfil specifications, but also to analyse the effect of non-idealities on the modulator performance. The expected response of the modulator is obtained by defining a set of experiments based on analytical models, which allow us to translate all design considerations into a set of values such that the design at transistor level be established according to the desired performance of the proposed architecture. This design strategy perhaps is not the most accurate but it allows us to get a general understanding of the system under design, and also a comprehension at the highest level of abstraction. The system under study is a cascade 4th order hybrid Sigma-Delta (ΣΔ) modulator, from which the second stage is a 2nd order Low-Pass (LP) DT ΣΔ modulator. The ideal performance of the DT modulator is used to show how non-idealities must be taken into account, and also how to translate design considerations into a set of physical values not only to design PBBs at transistor level, but also to minimize the non-idealities effects up to acceptable values.

Resumen—El diseño del modulador híbrido toma ventaja de

las aproximaciones en tiempo discreto y tiempo continuo, y es un diseño en cascada. En esta contribución, primeramente las características de desempeño de los bloques básicos de procesamiento se obtienen con ayuda de SIMSIDES. Luego, la simulación a nivel transistor se realiza no solo para verificar el cumplimiento de especificaciones, sino para analizar el efecto de las no-idealidades en el desempeño del modulador. Para ello, se define un diseño de experimentos en el que el desempeño esperado del modulador permita traducir las características específicas en un conjunto de valores que permitan su síntesis a nivel transistor, y en consecuencia que el modulador responda a las especificaciones impuestas. Esta estrategia de diseño quizá no sea la más exacta, pero sí permite una comprensión general a nivel sistema desde el nivel más alto de abstracción. El sistema bajo estudio es un modulador híbrido Pasa-Bajas en cascada, Sigma-Delta (ΣΔ) de 4o orden, siendo el back-end una implementación en tiempo discreto. En este artículo, el desempeño ideal del modulador, en tiempo discreto, es usado como vehículo para mostrar cómo, el análisis de no idealidades, no solo se traduce en consideraciones de diseño en todos aquellos bloques básicos de procesamiento −desarrollados a nivel transistor− sino también cómo ese análisis permite llevar el efecto de las no idealidades a valores aceptables.

I. INTRODUCTION It is well known that an analog system design consists of

an architecture selection, a set of Analog Building-Blocks (ABBs) as well as theirs particular specification in order to implement the chosen architecture, and an accurate small-signal analysis focused to minimize the circuit non-idealities effects on the whole system performance (see Fig. 1a). In this work the System Under Design (SUD) is a universal multi-service wireless terminal, which is a common device for communication purposes. According to commercial regulations such a device must operate at a bit rate ranging from 279kHz/s to 3.84MHz/s, and a frequency band from 890MHz to 2.48GHz if GSM, UMTS, Bluetooth and WLAN are the standards of interest. Thus, in this work, we will explain why neither a fully DT design nor a CT design are suitable design strategies to satisfy the operative conditions mentioned above. Based on that explanation, we are proposing a hybrid design where PBBs are synthetized according technological design rules of a standard 130nm CMOS fabrication process.

Fig. 1. A strategy for designing an analog system design is based on three basic concepts: Architectures, Analog blocks and Analysis, (AAA).

This paper is organized as follows: The architecture selection based on Analog Building Blocks (ABBs) is presented in section II, where simulation conditions are given in order to define a set of specifications for each ABB. In the same section a top-down simulation strategy is also presented. Preliminary results based on SIMSIDES simulations are presented in section III, where the design

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was focused to the most important component of the modulator: the integrator circuit. From simulation results a set of parameters (to be synthetized at transistor level) were deduced in order to design a fully-differential amplifier. The topology and Spice simulation are given also in this section. Finally, the conclusions of this work and a resume of the future work are discussed in section IV.

II. ARCHITECTURE SELECTION, NON-IDEALITIES AND SIMULATION TOOLS

The design of a universal multi-service wireless terminal invites us to consider architectures based on ΣΔ modulation, where the modulator is neither CT nor DT proposals, but a hybrid one. The reason of our choice is simple. Silicon-based design of DT ΣΔ modulators (ΣΔM) have enhanced their performance because of the improvement in microelectronics manufacturing methods along with architectures that work accurately in the discrete domain. However, the increasing demands for high data rates restrict the modulator performance due to the prohibitive unity-gain frequency requirements of the differential amplifier in Switched-Capacitor (SC) integrators [1]. On the other hand, CT ΣΔM present fastest operation and lower power consumption than DT modulators but suffer of high sensitivity to several non-ideal effects, particularly jitter, mismatch and time constant variations. In practice, although these problems have been partially solved in several silicon-based mono-standard Integrated Circuits (ICs), all of them are a critical factor in multi-standard applications with several Analog-to-Digital Converters (ADC) specifications, which explains why the number of multi-standard CT ΣΔM reported so far are really poor [2], [3]. Thus, in a Hybrid CT/DT ΣΔ modulator (H-ΣΔM), it is assumed that the whole design takes advantage of both design approaches [1], [4]-[10]. So, the architecture is as simple as a cascade design is.

Once the architecture has been defined, we propose just two ABBs: a 2nd order CT block for implementing the front-end stage, and a 2nd order DT block to develop the back-end stage. In other words, the system under design is actually a LP 4th order H-ΣΔM, where it is expected that the modulator operates according to the design specifications given in Table I. Note that, as Fig. 2 shown, PBBs have been identified in a block diagram in order to visualize how each ABB must be builded.

To establish the design specifications for each PBB, it is needed to define a list including the most important non-idealities that affect the performance of the whole design, as well as their corresponding Figures-of-Merit (FOM) in order to achieve the required data rate, satisfy the needed bandwidth, establish the sampling frequency, minimize power consumption, reduce integration area, and so on.

TABLE I SIMULATION CONDITIONS BASED ON DESIGN SPECIFICATIONS

Quantizer Bias ±1.2V

Number of levels 3

Input signal Amplitude -10dB

Frequency, fi 991.234kHz Bandwidth, BW 10MHz Sampling frequency, fs 200MHz

Fig. 2. H-ΣΔM based on two analog basic blocks, where each one is divided formed with specific Processing Basic Blocks (PBBs).

In addition to establish design specifications, it is also well-known that the process to translate design specifications at transistor level is deeply correlated with the non-idealities effect affecting to each PBB. The behind idea shown in Fig. 1b is do not put in practice individual analysis, but a unique fully-integrated analysis including architecture selection, definition of ABB, and a suitable design strategy that adds a general small-signal analysis. Consequently, the simulation process must be done at the highest level of abstraction, i.e. a process commonly called Behavioral Simulation (BS). This kind of simulation allows us to get a general comprehension of the SUD, and all the design considerations can be converted into a set of values such that the parameters of the transistor-based circuits can be established according to the desired performance of the selected architecture. Just for illustrative purposes, Fig. 3 shows a single-ended Differential Pair (DP) that was optimized for obtaining an equivalent input-referred voltage noise lower than 5.0nV/√Hz. In this example neither the operation point nor the open-loop low-frequency gain was negatively affected. Table II shows no-optimized and optimized values of the DP obtained from Spice simulations. In practice, advantages of BS is that simulation time is much lower than the simulation time at transistor level, and all design considerations are converted into a set of values that allows us to establish the parameters of all the transistor-based circuits. In other words, the idea of the high level design is not only to develop a behavioral model for reducing simulation time, but also to select a suitable architecture such that each PBB can be described with the help of both a behavioral description language and a set of explicit expressions. For instance, a mathematical expression modeling the equivalent input noise of the Single-Ended DP (SEDP), at room temperature, is given by

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

2mp

3mn2p,eqTOT,eq g

g12VV , (1)

where Veq,p2 is the rms voltage noise due to the transistor Mp2:

⎟⎟⎠

⎞⎜⎜⎝

⎛=

2mp2p,eq g3

2kT4V , (2)

with k and T the Boltzmann’s constant and the absolute temperature, respectively [11]. From this result it is easy to conclude that the SEDP thermal noise is reduced by

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increasing just the value of gmp2. Further, that fact increases the open-loop gain and the bias current remains without change; the same is true for the power consumption. However, even when gmp2 should be made as large as possible to minimize thermal noise contribution, parasitics will also increase affecting the needed bandwidth. This design problem is just one of several trade-offs that the analog designer must take into account in order to minimize the effect of these non-idealities. That is the reason why it is not recommended to apply a set of individual analysis but a unique fully-integrated analysis, from which BS is just a design option.

A. What do non-idealities really mean?

Since several decades ago the idea of Design Methods (DMs) was introduced to develop circuits and devices, and also to understand the physical origin of the so-called Sources of Non-Idealities (SNIs). A SNI is an unwanted phenomena coexisting in any electronic device and negatively modifies its expected performance. Since then how must be represented each SNI at circuit level for modeling purposes has defined a research field. In that sense, several Physical Theories (PTs) have been proposed in order to explain the nature of many SNIs. Such an explanation is commonly described with the help of an Analytical Model (AM). Examples of these models include intrinsic/extrinsic noise, temperature effects, mismatch, parasitic components, offset, downsizing effects, harmonic distortion, etc. However, the comprehension of any SNI via AMs is not enough. The challenge of a new technology necessarily implies redesign these AMs because MOS analog circuits do not have any benefit when technologies scale down. Unfortunately the analog circuits designer knows that bias, width, and length of the MOS transistors are his/her only design variables and, in conjunction with technology models (BSIM, BSIMv3, BSIMv4.7.0, EKV, etc.) and simulation tools (SPICE, HSPICE, TSPICE, etc.), the designer also knows that developing a design flow any analog architecture can be designed at transistor level. However, it is assumed that the designer knows advantages/disadvantages of the models provided by manufacturers, such that he/she is not only free to put in practice his/her design flow, but also how adds open literature information in it. At the end, it is expected that the effect of specific Non-Idealities (NIs) on the performance of a specific system be as low as dictated by regulations [12]. It is the authors’ opinion that SNIs form a rational invention of the Man in order to develop and also to enhance well-identified properties of any engineering design.

B. Simulation tools

The behind idea of developing Computer-Aided-Design (CAD) is take into account an alternative design step, before fabrication, in order to assess the performance of electronic circuits. A CAD tool currently must include accurate SNIs modeling, appropriate initial conditions and voltage dependences to accurately simulate the behavior of the CUD. Today the term CUD has necessarily change to SUD because of the complexity of modern systems. In practice to simulate the performance of systems at transistor level SPICE is commonly used, however simulation time grows with the system size, the analysis type and also with the

number of events required to compute a given Figure of Merit (FOM). In other words, systems simulations based on SPICE is prohibited at least on the first steps of the adopted design flow. This fact explains why it is highly recommended to divide the SUD into basic blocks, where each one must be described with a behavioral description language. This design strategy, the behavioral simulation, is illustrative shown in Fig 1c, where architecture selection, ABBs definition, and the suitable small-signal analysis form the rational support of the analog circuits designer. An example of this design strategy focused to the design of the H-ΣΔM is SIMSIDES (SIMulink-based SIgma-DElta Modulator), which is a copyright software developed by the Instituto de Microelectrónica de SEvilla (IMSE) [9]; a free copy can be downloaded once filling in on-line the request/registration form (see www.imse-cnm.csic.es). So, with the help of that tool mathematical expressions allow us to relate output variables with the input and internal state variables of each defined block.

Fig. 3. Circuit used to illustrate how non-idealities analysis helps to reduce its effect (at system level) and also to enhance the circuit performance.

TABLE II SPICE RESULTS

Parameter Non-optimized Optimized Open-loop gain 36.71dB 43.19 dB

Total input noise 5.7671 nV/√Hz 3.2390 nV/√Hz IBIAS 372μA 372μA gmp2 0.816mS 2.13mS gmn3 0.187mS 0.187mS

(W/L)Mp1 68.66 68.66 (W/L)Mp2 68.66 343.33 (W/L)Mn3 2.0 2.0

III. BEHAVIOURAL SIMULATION The simulation strategy of the 4th order hybrid ΣΔM is as

follows. 1) The front-end/back-end is a 2nd order CT/DT proposal, 2) for simulation purposes the front-end is assumed for all cases an ideal design, i.e. non-idealities are not taken into account, and 3) for comparison purposes the back-end is firstly assumed an ideal design in order to capture the ideal response, secondly several non-idealities are taken into account to measure their effect on the system performance. According to this procedure a set of parameters shall be varied in order to evaluate both the performance of the fully-differential Switched-Capacitor (SC) integrator and the hybrid ΣΔM performance. With the help of SIMSIDES the strategy described above is carried out to obtain a set of specific parameters. The general block diagram of the modulator shown in Fig. 2 is a cascade 2-stage (2-2) architecture.

The main electrical parameters affecting the overall behaviour of a DT SC integrator are the open-loop low-frequency Gain (Av), the 0dB gain frequency (f0), the input

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transconductance (gm) of the differential amplifier [12], and the maximum output current (Io) of the amplifier. Fig. 4 shows the modulator performance under variations of the gain Av, where values higher than 60dB produces a Signal-to-Noise Ratio (SNR) variations of the order of ±1dB, which relaxes the low-frequency gain of the operational amplifier. However, since the output swing of the integrators establishes several caracteristics of the transistor-based circuits (see Fig. 5), simulation results shown that the needed Output Swing (OS) is not the same for each integrator. Even more, it is important to underline that all SC integrators suffer from several amplifier non-idealities. However, these effects on the integrator performance are directly related to the amplifier topology. Thus, from SIMSIDES simulation we have found specific characteristics for the amplifier (see Table III) to satisfy the requirements in Table I. These values produce the spectrum response and the SNR shown in Fig. 6 and 7, respectively. Note that the noise shaping presents a high-pass characteristic.

TABLE III SELECTED PARAMETERS

Integrator

Io 1mAGm 1mSAv >60dBRon 250Ω

Output Swing ±0.6V

Fig. 4. Behavioural response of the SNR as a function of Av.

Fig. 5 SNR vs maximum OS.

Fig. 6 ΣΔM Output spectrum. Ideal response vs response based on non-

idealities effect.

Fig. 7 Ideal vs SNR selected parameters.

A. The OTA transistor-based design The key point in the design of circuits by using SC

techniques is the Operational Transconductance Amplifier (OTA) [13]. As Table I shows, the sampling frequency is fs=200MHz, which leads an OTA with a unity gain frequency five times higher than the sampling frequency, i.e. f0=1GHz, whereas the phase margin must be in the range 45o-60o in order to provide good settling behaviour [14], [15]. The chosen architecture is a Complementary Folded Cascode Feed-forward Compensated (CFCFC) shown in Fig. 7a [16]. The OTA has been designed according technological design rules of a 130nm CMOS process. Table IV shows the transistor dimensions of the OTA.

The CMFB used (see Fig. 7b) when compared to other available circuits surpasses them because of its good linearity, small parasitic capacitance and higher sensibility to common mode signals [17], [18]. Once the operation point is defined and the size of transistor is finally established, transistor based simulations allow us evaluate the open-loop response. Table V shows the average simulation performance of the fully-differential CFCFC OTA. For comparison purposes, the AM deduced from the small-signal analysis is given by

effoCmnmpBmpmnA rGggGggGA ,111950 ))()(( +−+−= , (3)

where

119, )1()1(

1

dsBdsAeffo gGgG

r−+−

= , (4)

9ds7ds5ds9mp

9mpA gggg

gG

+++= , (5)

13ds11ds1ds11mn

11mnB gggg

gG+++

= , (6)

11mn9mpC ggG += , (7)

With the help of (3)-(7) the low-frequency gain is easily computed. Equation (3) is actually a better AM respect the one given in [16]. On the other hand, as shown in Fig. 5 the SNR presents an acceptable performance (>68dB @ Cf=2.5pF) for OS values ranging from 0.6- to 0.8-V. However, even when the maximum OS is different for each integrator, it is expected that the same OTA fulfill the requirement of both (CT and DT) integrators. In addition to that, other studies must be carried out by adding the degradation of several circuit-level errors, were capacitor mismatch, time-constant error, In-Band Noise (IBN) power, and the correct operation of the analog-to-digital interface (see Fig. 2) are some examples.

858

(a)

(b)

Fig. 7 Fully differential OTA (a), and continuous time CMFB (b).

TABLE IV TRANSISTOR ASPECT RATIOS.

OTA

M1-M2 1029:1M3 491:1M4 64:1

M5-M6 420:1M7-M8 504:1

M9-M10 630:1M11-M12 165:1M13-M14 56:1

Cf 2.5pF

CMFB M15-M16 712:1M17-M20 44:1M21-M22 56:1

TABLE V SIMULATION RESULTS

OTA

Io 0.311mAf0 1.047GHzAv 60dBCL 2.5pFΦM 48.5o

Ps 11.82mWSR -

IV. CONCLUSIONS Top-down design based on behavioral simulation allows

to the designer converts all design considerations into a set of values suitable for designing silicon-based circuits. Perhaps this design methodology is not the most accurate but it allows us to get a general comprehension of the system under design. In addition to that, once the architecture is well-defined, it is mandatory to list a set of non-idealities affecting the performance of the design, and also to define a set of mathematical expressions that model

the behavioral performance of each ABB and all PBB as well. To face such a design in this work we used SIMSIDES to simulate the behavioral performance of a 4th order LP hybrid ΣΔ modulator. The analysis and design of a 2nd order LP DT ΣΔ modulator was used to illustrate how adding non-idealities to the design flow allows us to define specific characteristics at transistor level of some PBB, from which a fully-differential OTA was sized and simulated in order to shown the usefulness of the proposed design methodology. Some results of this design include an Equivalent Number Of Bits (ENOB) of 10.46 when the switch on-resistance of 250Ω was assumed. However, leakage current of switches, slew-rate, settling time, and other parameters of the OTA must be optimized in order to increase both the SNR and the ENOB. Fortunately, behavioral simulation allows us to reduce simulation time and also to add mathematical expressions modeling these non-idealities.

Finally, three sentences must be underlined: 1) the analog circuits design is not black art, 2) the analog circuit designer is not a magician doing mystical art, and 3) analog circuits design is an engineering discipline supported in physical laws. So, in the design of analog circuits specific SNIs are minimized with both bias and transistors size. These parameters and a well-defined design methodology form a unique tool to obtain accurate analog circuits. At the end of any design flow AMs, simulation tools, and PT must predict in a correct way the whole performance of the SUD. In terms of the system described in this contribution, it is expected that the proposed design methodology gives us the desired performance of the 4th order LP hybrid ΣΔ modulator. As an example of the design methodology, a fully-differential OTA has been designed and simulated at transistor level, currently its design at layout level is a work in progress.

ACKNOWLEDGMENTS This work is supported by the Mexican Council of

Science and Technology (CONACyT) under grant 169660, and also by the PNPC-CONACyT.

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