SAURABH MISHRA 914 E, Lemon Street, #206, Tempe, AZ - 85281 Ph. No. +14802079515 smishr19@asu.edu SUMMARY Graduate student at ASU (School of ECE), specialized in VLSI Design, actively looking for a full time opportunity in Mixed Signal Circuit Designing and verification, RTL Design, STA, APR, Memory Design, Custom Design, PDK Development and other related areas, with prior 3 years of work experience and internship at Intel Folsom in PCH full chip front end validation. EDUCATION Master of Science in Engineering, Electrical Engineering May’16 Arizona State University, Tempe, AZ Bachelor of Technology, Electrical Engineering May’11 KIIT University, Bhubaneswar, India TECHNICAL SKILLS

Hardware Description Languages and OS: System Verilog, Verilog Programming and Unix, Linux Programming Languages: C, C++, Shell programming, Perl, Assembly, OpenCL Other Tools: OVM/Saola, VCS, DVE, DVT, GIT, Perforce, ModelSim, AutoCad, MATLAB, COMSOL, L-Edit EDA Tools: Cadence Encounter RTL Compiler, Cadence Encounter APR, Virtuoso, Spectre, Hspice, Hercules, Calibre 8051 Microcontroller Programming, addressing and interfacing using C and Assembly Utilized ARM7 Processor, skilled on PCB designing and PIC Microcontroller. Programmed Hardwired Logic Control, PLC by Simatic Manager; Operated Drives (AC /DC), Profibus WORK EXPERIENCE Pre-Silicon Chipset Validation Engineer - Intern, Platform Controller Hub Full Chip team, Intel Folsom, CA May’15-Dec’15 Enabling Front End Full Chip validation of Security and Manageability related IP into chipset products in simulation

based pre-silicon environment. Reviewed spec documents and test plans to understand the architecture, functionality and interaction of IP’s in Peripheral Connectivity Hub, reviewed codes, debugged and edited them using the aid of trackers and waveforms. Did close collaboration with IP architects, engineers and integrators to find out inherent issues and debugged them. Volunteered for developing a Perl script for Full-chip regression for helping regression owner to bucketize errors in

different categories like Hang, Moat Errors, OVM Errors, Assertion Errors, Fatal Error etc. Senior Electrical Engineer, PMC Projects (I) Pvt. Ltd., Adani Group, Visakhapatnam & Surat, India Jul’11–Mar’14 Executed, liaison (with FLSmidth) and documentation for construction, installation, testing and commissioning of

drives, cables, relays, HT Motors, power transformers, Liebherr Cranes, overhead & underground transmission line. Documented, edited (using AUTOCAD) and verified designs and SLD for equipments and overall layout. PROJECTS Schematic, Layout, Simulation, PEX and delay calculation for Standard cells designed with 7nm PDK Feb’16 Auditing VLSI Design class under Professor Lawrence T. Clarke

Worked on schematic, layout, simulation and layout of SRAM 6T cells memory. Design and verification of SRAM array with decoders, write drivers and sense amplifiers. Development and characterization of multi Vth standard cell Library (using 7nm FINFET PDK)

Design, Layout, Simulation and PEX for 32x32 Register file and its decoder stage using 7nm PDK Mar’16 Designed a 32x32 Register file with a single read and write port from schematic through layout for minimum area and EDP. Simulated the column, made changes to cell and column design provided to make it work and then arranged the column to produce an array. Designed pre-decoder, decoder and control logic to the design with full layout. Design of a 2-bit Error Detection and 1-bit Error Correction logic using Hamming Code (RTL TO GDSII) Apr’16 Data input was 128 bits wide and power was saved by inserting Clock gating. RTL was generated for Parity tree, decoder & correction logic, synthesized, verified. Entire Back End design, that is Floor planning, Placement and Routing, STA, Clock tree synthesis was done using Cadence Encounter APR Tool. Programming in C language to determine size of the caches, measuring latency, while considering the effect of virtual addressing and TLB on cache access timing. Sep’14 Extra Credits: Implementing Stream Functions in OpenCL, benchmark performance comparing CPU vs GPU Oct’14 Implementation of Thread Level Parallelism using C language Nov’14

Turning off compiler optimizations and increasing the number of threads to measure and compare performance and time elapsed by plotting them out to get an analytical understanding of architecture.

Design, Layout of 8 Bit modulo Adder (by D flip flop and adder) minimizing EDP & Layout area in 32nm PDK Nov’14 Design, Layout and Simulation minimizing area and power consumption (70pW at standby) for: SAR ADC (Successive Approximation Register ADC). This energy consumption was one of the lowest ever reported. Apr’15 RELEVANT COURSES (1) Analog IC Design; (2) Digital IC Design; (3) VLSI Design ; (4) Computer Arch.; (5) Adv. Analog IC Design; (6) Adv. Bio-Sensors Concepts; (7) Intro to MEMS; (8) Low Power Bio-Electronics; (9) Reading & Conference; (10) NanoFab; SOCIAL VOLUNTEERING Cadet (under B & C certificate courses), NCC (National Cadet Corps) Jul’08–May’13 Taught young kids and provide them with after school support in Maths, Science and English.