sr_wgfog

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ABSTRACT

This scope is to give the details of software requirement specification for FPGA firmware design

implementation for WG-FOGACC-2! "oard The firmware design involves generation of cloc#

signal$ generation of control signal$ digiti%ation of acceleration data$ digiti%ation of temperature

data$ collecting final data and sending all these data to PC in pac#et format

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Contents

List of Tables......................................................................................................6

1. INTRODUCTION................................................................................................71.1. Purpose...........................................................................................................................7

2. GENERAL DESCRIPTION....................................................................................72.1. Product Perspective........................................................................................................7

3. Desig a!!"oa#$.............................................................................................%

&. TOP LE'EL DESIGN........................................................................................1(4.1.1. System interface:...................................................................................................11

4.2. Major Components Identication:.................................................................................124.3. unctions of Major Components....................................................................................13

4.3.1. C!oc" #eneration $o%ic...........................................................................................134.3.2. &'C interface modu!es:..........................................................................................134.3.3. Pico(!a)e processor................................................................................................13

4.3.4. 'P*C Interface........................................................................................................134.3.+. 'P,&M Modu!e.......................................................................................................134.3.-. Compensator modu!e.............................................................................................144.3.7. ost data /and!er...................................................................................................144.3.0. ser Interface.........................................................................................................1+4.3.. ardare Interface.................................................................................................1+

&escription of each hardware "loc# in "rief ......................................................................................1-'(! Power suppl) *(+( , !'+.........................................................................................1-'(2 . /TC2001 A&Cs *Acceleration data.............................................................................1-'(( 0-channel A&C /TC!'0 *Thermistor data......................................................................1-'(0 Temperature sensor A&30!' *On-"oard temperature data....................................................1-'(' 45022 level converter ................................................................................................1-'(. ( &P6C "oards *7A4T interface..................................................................................1-

'(3 Cr)stal Oscillator ......................................................................................................1-'(8 92'P!. 5P: Flash;<TAG interface.................................................................................17'( 4eset circuit.............................................................................................................174.3.1. Communication Interface.....................................................................................174.3.11. Memory Constraint...............................................................................................17

'evice ti!i)ation of P#& 56C3S'10a 4CS4048............................................................174.3.12. 9peration.............................................................................................................174.3.13. Pac"et structure for pro%ramma!e parameters...................................................14.3.14. Pac"et structure for Pro%rammin% parameters on P#&.......................................2

). Use" C$a"a#te"isti#s*.....................................................................................21

6. Cost"aits+ ass,-!tios a e!ee#ies...................................................21

-.1. 'esi%n constraints........................................................................................................21-.1.1. Softare constraints...............................................................................................21-.1.2. ardare constraints..............................................................................................21

-.2. &ssumptions and dependencies...................................................................................21

7. Soft/a"e S0ste- att"ib,tes...........................................................................217.1. ,e!iai!ity...................................................................................................................... 217.2. &vai!ai!ity.................................................................................................................... 227.3. Security........................................................................................................................ 227.4. Maintainai!ity..............................................................................................................227.+. Portai!ity..................................................................................................................... 22

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List of FiguresFigure 1: System Block Diagram...................................................................................................................7Figure 2: Functional Block Diagram of Wg-Fogacc-2.1...............................................................................14

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List of Tables

Table 1: acket Structure.............................................................................................................................. !Table 2: "yro #arameters.............................................................................................................................. $Table %: &ccelerometer #arameters.............................................................................................................1'Table 4: acket structure for #arametersDesign a##roac(..........................................................................11Table ): *ut#ut +ata format......................................................................................................................... 1%

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,T*D/0T,*

1.1.1. Purpose

T(e #ur#ose of t(is +ocument is to +escribe reuirement an+ functions for a Softare system. ,t is a+escri#tion of t(e be(a3ior of a system to be +e3elo#e+ an+ may inclu+e a set of use cases t(at +escribeinteractions t(e users ill (a3e it( t(e softare. Softare reuirements s#ecification establis(es t(ebasis for agreement beteen customers an+ contractors on (at t(e softare #ro+uct is to +o as ell as(at it is not e#ecte+ to +o. Softare reuirements s#ecification #ermits a rigorous assessment of reuirements before +esign can begin an+ re+uces later re+esign. ,t s(oul+ also #ro3i+e a realistic basisfor estimating #ro+uct costs5 risks5 an+ sc(e+ules.

1.2. GENERAL DESCRPT!N

1.2.1. Pro"u#t Perspe#ti$e

W"-F*"&00-2.1 boar+ is +e3elo#e+ to measure t(e angular acceleration of an ob6ect. T(isboar+ acce#ts t(e ra current in#ut an+ tem#erature t(ermistor8 +ata from accelerometer sensor an+ itcom#ensate t(e tem#erature in+uce+ errors before sen+ing t(e +ata to (ost o3er a S-422 #rotocol. ,n t(issystem t(ere are % accelerometer c(annels carrying acceleration 3alues of % aes an+ % tem#eraturec(annels.

F"& firmare +i3i+e+ into folloing t(ree sections:18 0ontrol an+ clock signal generation28 &lgorit(m im#lementation 0om#ensation of tem#erature in+uce+ acceleration errors8%8 0ommunication it( eternal orl+ T(roug( /&T8

Figure 1: System Block Diagram

1.%. Design approa#&

T(e inten+e+ firmare is for F"& of W"-F*"&00-2.1 boar+.

F"& (as folloing ma6or functionalities:

1. T(e system consists of t(ree icoBla9e5 one icrobla9e an+ one finite state mac(ine FS8 to

control +ifferent (ar+are an+ softare +e3ices.

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2. To icoBla9e mo+ules are use+ to rea+ +ata from t(e to grou# of %-&D0s eac( ;T0244'5 24-

bit &D08. S, #rotocol an+ t(e necessary &D0 control signals are generate+ by t(is icoBla9e.

T(ese 24-bit &D0 sam#les are sign eten+e+ to %2-bits for furt(er #rocessing. T(ese icoBla9e<s

rea+s t(e % &D0s &D0115 &D012 = &D01%8 an+ ot(er % &D0<s&D0215 &D022 = &D02%8 one

by one by #olling t(eir busy #ins an+ t(e sam#les are store+ into a 1>%2 D& D& of 24-

bit &D08 in a seuential or+er 1 to %.%. FS is use+ to rea+ ,20 base+ 1'-bit +igital on-boar+ tem#erature sensor &D741)8. ,20 #rotocol

is im#lemente+ in FS to rea+ +ata from &D741). T(is 1'-bit tem#erature 3alue sign eten+e+ to

1>?%2 bits for furt(er #rocessing.

4. icroBla9e #rocessor rea+s t(e +ata from D& of 24-bit &D0 an+ also rea+s t(e +ata from t(e

FS of on-boar+ tem#erature sensor t(roug( its !-bit #orts using #arallel interface.

). otational rate 3alue an+ boar+ tem#erature of % D@0 boar+s are recei3e+ by t(e icobla9e

t(roug( % /&T recei3ers.

>. &ll t(e abo3e sai+ +ata is rea+ by t(e icrobla9e an+ t(e &00 +ata is store+ in (e 3ariables

+efine+ in t(e co+e for t(e #rocessor.

7. *n recei3ing t(e Sync #ulse5 icrobla9e sen+s +ata #acket to t(e (ost. T(e #acket structure sent

to t(e (ost is as s(on in t(e table belo.

Se'uen#e Data

1 acket Aea+er '2B7)8 2-Byte8

2 acket 0ount alue 2-Byte8

% Status Wor+ 2-Byte8

4 D@0C1 rotation rate 3alue 4-Byte8

) D@01 rotation rate 3alue 4-Byte8

> D@0E1 rotation rate 3alue 4-Byte8

7 D@0C2 rotation rate 3alue 4-Byte8

! D@02 rotation rate 3alue 4-Byte8$ D@0E2 rotation rate 3alue 4-Byte8

1' D@0C% rotation rate 3alue 4-Byte8

11 D@0% rotation rate 3alue 4-Byte8

12 D@0E% rotation rate 3alue 4-Byte8

1% D@0C4 rotation rate 3alue 4-Byte8

14 D@04 rotation rate 3alue 4-Byte8

1) D@0E4 rotation rate 3alue 4-Byte8

1> &ccelerometerC-1 +ata 4-Byte8

17 &ccelerometer-1 +ata 4-Byte8

1! &ccelerometerE-1 +ata 4-Byte8

1$ &ccelerometerC-2 +ata 4-Byte8

2' &ccelerometer-2 +ata 4-Byte821 &ccelerometerE-2 +ata 4-Byte8

22 &ccelerometerC-% +ata 4-Byte8

2% &ccelerometer-% +ata 4-Byte8

24 &ccelerometerE-% +ata 4-Byte8

2) &ccelerometerC-4 +ata 4-Byte8

2> &ccelerometer-4 +ata 4-Byte8

27 &ccelerometerE-4 +ata 4-Byte8

2! &ccelerometer-2 sensor tem#erature 2-Byte8

2$ 0(ecksum 2-Byte8

Table ): *ut#ut +ata format

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!. Data transfers beteen W"-F*"&00-2.1 boar+ an+ Aost is initiate+ by a sync #ulse from (ost. ,t

also (as an o#tion of using t(e internally generate+ sync #ulse if reuire+

$. ;DS lines are use+ by W"-F*"&00-2.1 to interface D@0.

1'. T(e #rogrammable #arameters are sent to t(e W"-F*"&002.1 boar+ 3ia an eternal

*#tocou#ler?S-422 transcei3er. T(ese #arameters are ritten in t(e flas( memory #resent on t(e

boar+.11. T(is +ata is rea+ back from t(e flas( an+ ec(oe+ to t(e (ost to confirm t(e rite of t(e +ata.

12. &t startu#5 t(e #arameters in t(e flas( are rea+ by t(e icroBla9e an+ ma+e a3ailable for

com#ensation. T(ese rea+ #arameters are sent back to t(e (ost initially. T(e #arameters can be

c(ange+ on t(e fly

1.(. T!P LE)EL DESGN

Figure 2: Functional Block Diagram of Wg-Fogacc-2.1

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1.(.1.1 S*ste+ interfa#e,

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Figure 0! 5)stem "loc# diagram

Descri#tion of system block +iagram.

1.T(ere are % accelerometers eac( (a3ing current out#ut #ro#ortional to acceleration. T(e accelerometer current out#ut ranges from H)' m& to G)' m& it( resolution of >2 n&. T(e current out#ut of accelerometer is con3erte+ into 3oltage by ,- con3erter.

2.&n &D0 +igiti9es t(e out#ut of ,- con3erter. Since5 t(e reuire+ +ynamic range of current in#ut to

system is (ig(I t(e &D0 use+ is 24-bit sigma-+elta &D0 ;T0244'8.

%.,n a++ition to current in#ut5 out#uts of t(ree tem#erature sensors one t(ermister on eac( accelerometer8are also a##lie+ to &00D0 boar+.12 bit &D0 ;T01)$4; +igiti9es t(e +ata from t(ese t(ree tem#eraturesensors. T(e &D0 ;T01)$4 is interface+ to S&&T& % &DS F"& o3er S, interface.

4.&00D0 boar+ acce#ts rate an+ tem#erature +ata from D@0 boar+ o3er a +ifferential line. T(eseboar+s are also connecte+ to eac( ot(er on S, interface o#tional8. ,n t(is configuration &00D0 boar+ illact as master (ile D@0 boar+ ill act as sla3e. &00D0 boar+ generates reuire+ timing signal. ,nres#onse to signal from &00D0 boar+5 D@0 boar+ ill sen+ rate an+ tem#erature +ata.

).&00D0 boar+ ill +o tem#erature com#ensation on acceleration +ataI t(e #acket is ma+e of tem#erature com#ensate+ acceleration +ata an+ rate5 tem#erature +ata recei3e+ from D@0 boar+s. T(e

#acket is sen+ to na3igation boar+ o3er a +ifferential line using S*T interface.

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1.(.2. 4a5or Co+ponents "entifi#ation,

T(e ma6or com#onents in t(e F"& +esign are:1. 0lock "eneration ;ogic2. /&T bau+ clock o+ule%. Data transmission #ulse "enerator 4. &D0 interface mo+ules

• &D0 ;T0244' interface mo+ule.

• &D0 741) tem#erature sensor interface mo+ule.

). D& mo+ule>. 0om#ensator 1 an+ 0om#ensator 2 block7. /&T recei3e controller !. "yro +ata (an+ler rocessor.$. D& mo+ule1'. Aost Data (an+ler rocessor.11. Flas( +ata (an+ler 12. /&T T =

1.(.%. Fun#tions of 4a5or Co+ponents

1.(.%.1 Clo#6 Generation Logi#

T(is +esign mo+ule su##lies t(e necessary clock signals to all ot(er +esign mo+ules. ,n#ut to t(ismo+ule is t(e clock signal from t(e 0rystal *scillator. /sing F"& resource like D0 an+ some mo+-counter logic necessary clock signals are +eri3e+. Similar resources are use+ for generation of t(ereference clocks reuire+ for t(e /&T mo+ules (ic( uses t(e 1.!%2A9 crystal.

1.(.%.2 ADC interfa#e +o"ules,

T(is +esign mo+ule is use+ to get rea+ +ata from +ifferent &D0s.

1.(.%.2.1 ADC LTC2((3 interfa#e +o"ule,

T(is o+ule contains to icoBla9e mo+ules (ic( rea+ &D0 +ata using to se#arate S,interfaces for t(e to grou#s of &D0<s. T(e +ata rea+ from t(e &D0<s is t(en store+ in t(e res#ecti3eD&S for eac( icoBla9e. T(is +ata is t(en rea+ by t(e (ost +ata (an+ler for transmission to t(e (ost.

1.(.%.2.2 ADC (17 te+perature sensor interfa#e +o"ule.

T(is mo+ule rea+s t(e +ata from onboar+ tem#erature sensor. T(e FS rea+s t(e +ata from t(ismo+ule an+ #ro3i+es it to t(e (ost +ata (an+ler.

1.(.%.% Pi#oBla8e pro#essor

,t is a sim#le !-bit soft #rocessor from ilin. ,t is a 3ery sim#le !-bit ,S0 microcontroller #rimarilyfor t(e S#artan-% +e3ices. &lt(oug( it coul+ be use+ for #rocessing of +ata5 it is most likely to be em#loye+in a##lications reuiring a com#le5 but non-time critical state mac(ine. Aence it (as t(e name of JK8

constant 0o+e+ rogrammable State ac(ineL. T(is K0S% reuires 6ust $> slices of F"&. Toget(er it( t(is small amount of logic5 a single block & is use+ to form a * store for a #rogram of u# to1'24 instructions. @3en it( suc( si9e constraints5 t(e #erformance is res#ectable at a##roimately 4% to>> ,S +e#en+ing on +e3ice ty#e an+ s#ee+ gra+e.

T(e icoBla9e microcontroller core is totally embe++e+ it(in t(e target F"& an+ reuires noeternal resources. T(e icoBla9e microcontroller is etremely fleible. T(e basic functionality is easilyeten+e+ an+ en(ance+ by connecting a++itional F"& logic to t(e microcontroller<s in#ut an+ out#ut#orts.

T(e icoBla9e microcontroller is +eli3ere+ as synt(esi9able AD; source co+e5 t(e core is future-#roof an+ can be migrate+ to future F"& arc(itectures5 effecti3ely eliminating #ro+uct obsolescencefears. Being integrate+ it(in t(e F"&5 t(e icoBla9e microcontroller re+uces boar+ s#ace5 +esign cost5an+ in3entory.

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1.(.%.( DPEC nterfa#e

T(e +ata from t(e D@0 is recei3e+ on t(e /&T at a bau+ rate of 11).2kb#s. T(e D@0 sent+ata after getting sync #ulses generate+ by t(e icoBla9e. Total % D@0s are t(ere eac( connecte+ tose#arate /&T mo+ule.

1.(.%.7 DPRA4 4o"ule

T(e D& mo+ule is use+ in beteen t(e ;T0244' interface mo+ule an+ t(e (ost +ata (an+ler

= beteen +ata (an+ler an+ (ost +ata (an+ler. T(e &D0 rea+ #icobla9e rites t(e &00 +ata into t(eD&. T(e (ost +ata (an+ler5 on recei3ing t(e transmit interru#t5 rea+s t(e 3alues from t(e D& an+stores it into a local D& before transmission. T(e gyro +ata (an+ler rea+s t(e +ata from S2%2 an+rites it in t(e D& (ic( is to be transmitte+.

1.(.%.9 Co+pensator +o"ule

T(e com#ensator mo+ule contains ;/Ts to com#ensate t(e ra &00 sam#les againsttem#erature. @ac( com#ensator mo+ule of W"-F*"&00-2.1 boar+ com#ensates % accelerometer c(annels. ,n case of W"-F*"&00-2.' boar+ t(e com#ensator com#ensates t(e > accelerometer c(annels. ;e3el 2 com#ensator inclu+es t(e remo3al of cross cou#ling effect +ue to mis-alignment of t(eacc<s an+ gyro<.

1.(.%. 0ost "ata &an"ler T(is mo+ule is use+ to collect t(e % accelerometer c(annels +ata for eac( sub sync #ulse. ,t also

interfaces it( t(e (ost to transfer t(e gyro an+ accelerometer +ata it( accelerometer boar+ tem#erature+ata u#on t(e reuest of transmit +ata #ulse. ,t recei3es t(e #arameters from 0?Aost (ic( are use+ for misalignment com#ensation an+ rites t(em into flas(. T(ese #arameters are retaine+ in t(e flas( e3enafter #oer off. T(e mo+ule #ro3i+es t(ese #arameter 3alues to t(e com#ensator mo+ules.

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1.(.%.: ser nterfa#e

1.(.%. 0ar";are nterfa#e

5.3.1 Po;er suppl* <%)% = 1.7)>

%.% an+ 1.) su##lies are use+ to #oer t(e F"&. *n-boar+ 1.) 3oltage regulator is use+ togenerate F"& core #oer su##ly an+ %.% su##ly is use+ to #oer ,?* blocks of F"&. %.%

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7.%.2 9 LTC2((3 ADCs <A##eleration "ata>

&cceleration +ata of % accelerometer sensors is +igiti9e+ by using si 24 -bit &D0s ;T0244'8.@ac( accelerometer sensor out#ut current is fe+ to to 24 -bit &D0s. T(ese si 24 -bit &D0s ;T0244'8are interface+ to F"& t(roug( to se#arate S, interfaces5 forming to grou#s of % &D0<s eac(..

7.%.% (?#&annel ADC LTC17( <T&er+istor "ata>

@ac( accelerometer sensor is (a3ing inbuilt t(ermistor to #ro3i+e its tem#erature. Suc( %

t(ermistors of % accelerometer sensors are connecte+ to first % c(annels of a 4-c(annel 12-bit &D0&D1)$48 to +igiti9e t(e res#ecti3e tem#erature rea+ings of accelerometer sensors. 4 t( c(annel of &D1)$4is left unuse+. 4-c(annel &D0 &D1)$48 is interface+ to F"& t(roug( S, lines.

7.%.( Te+perature sensor AD(17 <!n?boar" te+perature "ata>

To measure boar+ tem#erature an ,20 base+ tem#erature sensor &D741)8 is use+. T(is sensorconnecte+ to F"& 3ia ,20 interface.

7.%.7 RS(22 le$el #on$erter

/&T signals generate+ by F"& are connecte+ to S422 le3el con3erter c(i# to communicate &00D0 boar+ to an eternal (ost.

7.%.9 % DPEC boar"s <ART interfa#e>

&00D0 boar+ communicates it( % D@0 boar+s using /&T +ata transferre+ on ;DS lines. Toenable t(e rotational rate +ata transfer from D@0 to boar+ a sync(roni9ation #ulse is #ro3i+e+ by (ost 3ia;DS lines.

7.%. Cr*stal !s#illator

& )'A9 oscillator su##lies master clock to F"&. T(is master clock is use+ furt(er to +eri3einternal system clocks for signal #rocessing. &not(er crystal of 1.!4%2A9 is use+ for generating bau+enable signals for a bau+ rate of 11)2''b#s an+ $21>''b#s for /&T communication

7.%.: 427P19 SP Flas&@TAG interfa#e

*n-boar+ S, flas( memory is use+ to configure t(e F"& after e3ery #oer-on. T(is can be use+to store t(e reuire+ system information.

7.%. Reset #ir#uit

oer on acti3e lo reset to t(e F"& is #ro3i+e+ by t(is reset circuit.

1.(.%.13 Co++uni#ation nterfa#e

RS2%2@RS(22 interfa#e,0ommunication it( 0 a##lication softare is im#lemente+ on /&T. F"& acting as aster of communication transfers t(e +esire+ +ata to 0. &00 boar+ acce#t % gyros +ata using % +ifferent /&Tr.

1.(.%.11 4e+or* Constraint

De$i#e tili8ation of FPGA <C%SD1:33a (CS(:(>

De3ice /tili9ation S&T&-%& DS8 for &00D0

Logi# tili8ation se" A$ailable tili8ation

Slice Fli# Flo# >544$ %%52!' 1$M

4-,n#ut ;/Ts >5174 %%52!' 1!M

Logi# Distribution

*ccu#ie+ Slices )5$7$ 1>5>4' %)M

Total no of (?nput LTs >5%12 %%52!' 1!M

/se+ as ;ogic 45>%2

/se+ as route-t(ru 1%!

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/se+ as S(ift registers !$'

/se+ as Dual ort &<s 4$>

/se+ as %21 &s 1)>

umber of bon+e+ ,*s )4 %'$ 17M

umber of &B1>BW@s 17 !4 2'M

umber of DS4!&s %% !4 %$M

umber of B/F"/s ! 24 %%M

umber of D0s % ! %7M

1.(.%.12 !peration

,S@ 1'.1 is use+ for .bit an+ .mcs file generation5 t(ese files are +um#e+ in (ar+are using im#act tool.

acket structure beteen W"-F*"&00-2.1 boar+ an+ Aost

Fiel" No. Pa#6et Des#ription Total B*tes

1 acket Aea+er '2B7)8 22 acket 0ount alue 2

% Status Wor+ 2

4 D@0C1 rotation rate 3alue 4

) D@01 rotation rate 3alue 4

> D@0E1 rotation rate 3alue 4

7 D@0C2 rotation rate 3alue 4

! D@02 rotation rate 3alue 4

$ D@0E2 rotation rate 3alue 4

1' D@0C% rotation rate 3alue 4

11 D@0% rotation rate 3alue 4

12 D@0E% rotation rate 3alue 4

1% D@0C4 rotation rate 3alue 4

14 D@04 rotation rate 3alue 4

1) D@0E4 rotation rate 3alue 4

1> &ccelerometerC-1 +ata 4

17 &ccelerometer-1 +ata 4

1! &ccelerometerE-1 +ata 4

1$ &ccelerometerC-2 +ata 4

2' &ccelerometer-2 +ata 4

21 &ccelerometerE-2 +ata 4

22 &ccelerometerC-% +ata 4

2% &ccelerometer-% +ata 4

24 &ccelerometerE-% +ata 4

2) &ccelerometerC-4 +ata 4

2> &ccelerometer-4 +ata 427 &ccelerometerE-4 +ata 4

2! &ccelerometer-2 sensor tem#erature 2

2$ 0(ecksum 2

Table 1: acket Structure

8/10/2019 sr_wgfog


1.(.%.1% Pa#6et stru#ture for progra++able para+eters

a. "yro arameters


1 Aea+er H 2B7 2

2 0ounter 2

% Status - '''2 2

4 " 4

) "y 4

> "9 4

7 "y 4

! "yy 4

$ "y9 4

1' "9 4

11 "9y 4

12 "99 4

1% " *ffset 4

14 "y *ffset 4

1) "9 *ffset 41> Dummy 4

17 Dummy 4

1! Dummy 4

1$ Dummy 4

2' Dummy 4

21 Dummy 4

22 Dummy 4

2% Dummy 4

24 Dummy 4

2) Dummy 4

2> Dummy 4

27 Dummy 42! Dummy 2

2$ 0(ecksum 2

Table 2: "yro #arameters

b. &cc arameters


1 Aea+er H 2B7 2

2 0ounter 2

% Status - '''4 2

4 &N#lus 4

) &Nminus 4> &y 4

7 &9 4

! &y 4

$ &yyN#lus 4

1' &yyNminus 4

11 &y9 4

12 &9 4

1% &9y 4

14 &99N#lus 4

1) &99Nminus 4

1> & *ffset 4

17 &y *ffset 4

8/10/2019 sr_wgfog


1! &9 *ffset 4

1$ Dummy 4

2' Dummy 4

21 Dummy 4

22 Dummy 4

2% Dummy 4

24 Dummy 4

2) Dummy 4

2> Dummy 4

27 Dummy 4

2! Dummy 2

2$ 0(ecksum 2

Table %: &ccelerometer #arameters

1.(.%.1( Pa#6et stru#ture for Progra++ing para+eters on FPGA


1 Aea+er H AAAA 2

2 " 4

% "y 44 "9 4

) "y 4

> "yy 4

7 "y9 4

! "9 4

$ "9y 4

1' "99 4

11 " *ffset 4

12 "y *ffset 4

1% "9 *ffset 4

14 &N#lus 4

1) &Nminus 41> &y 4

17 &9 4

1! &y 4

1$ &yyN#lus 4

2' &yyNminus 4

21 &y9 4

22 &9 4

2% &9y 4

24 &99N#lus 4

2) &99Nminus 4

2> & *ffset 4

27 &y *ffset 4

2! &9 *ffset 4

2$ 0(ecksum 2

Table 4: acket structure for #arameters

1.7. ser C&ara#teristi#s,

• /ser s(oul+ (a3e basic knole+ge in ,S@ 1'.1 tool.

• /ser s(oul+ (a3e basic knole+ge in gyros an+ accelerometers.

• /ser must kno t(e (ar+are connection +etails.

• /ser s(oul+ (a3e basic knole+ge in ,m#act 1'.1 tool.

• /ser s(oul+ kno t(e /&T interface +etails.

• /ser s(oul+ be an @ngineer or scientist.

8/10/2019 sr_wgfog


1.9. Constraints assu+ptions an" "epen"en#ies

1.9.1. Design #onstraints

1.9.1.1 Soft;are #onstraints

• The pin assignment should "e according to the schematic and proper :O standard should

"e set

• Wherever possi"le the logic will ma#e use of in "uilt features of FPGA such as "loc#

4A9$ &C9$ multiplier macros constructed with FPGA primitives etc

1.9.1.2 0ar";are #onstraints

• Cloc# should not contain glitches

• +oltage levels at :;O should match with the interface

• Power suppl) should "e ripple free

1.9.2. Assu+ptions an" "epen"en#ies• The "ias frequenc) generated ") this unit depends on the multiplier and divider constants

accepta"le ") the &C9 of the FPGA used

• /oo# up ta"le "ased compensation algorithm used for "ias compensation

• The s)stem cloc# should have minimum =itter for proper operation of &C9

• 7A4T "aud rate accurac) depends on the accurac) of the !80(2 9>% cr)stal used and

the &C9

1.. Soft;are S*ste+ attributes

1..1. Reliabilit*

System is teste+ at +ifferent tem#eratures in burning test.

1..2. A$ailabilit*

ot a##licable.

1..%. Se#urit*

We are generating t(e .bit an+ .mcs files to +um# t(e (ar+are. nobo+y +on<t kno (at is t(ere in .bitan+ .mcs files.

1..(. 4aintainabilit*

ot a##licable.

1..7. Portabilit*

We can migrate t(e ,S@1'.1 co+e to latest 3ersion of ,S@ by c(anging t(e F"& +e3ice3erte-2 is notsu##orte+ for latest 3ersions of ,S@8

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