test cost challengestest cost challenges¹€창식.pdf · 2009-11-10 · concurrent testing-...
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Test Cost ChallengesTest Cost Challenges
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November 11, 2009Chang Kim (김창식)
Where we are !!!
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Number of Die per wafer exponentially increasing!!
150mm 200mm 300mm 450mm
Bigger Wafer Diameter
1985 1990 1995 2000 2005 2010 2015150mm 200mm 300mm 450mm
Moore’s Law
32nm process Technology Ready
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32nm process Technology Ready
History of DRAM Price per Megabit (Source: DQ)
• DRAM has maintained a 32% average reduction per year in• DRAM has maintained a 32% average reduction per year in Price per Megabit, over 34 years!
• Over four years this is approximately a 5x reduction in price
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Over four years, this is approximately a 5x reduction in price per Megabit
New Trend has been increasing complexity
M d lTSV
Module
MCPPOP
SOC + Memory + Analog
POP
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SIP
Higher Speed, Higher Density, More Core
Higher Density
Core #1
Core #2
CRF GDDR5
Core #3
Multi CoreHigher Speed
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Multi Core
Known Good Die
TSV Module
KGD required
MCP POPSpeed, Functionality, Reliability
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SIPIt’s a dream!?
Known Good Die
TSV Module
but still MGD..
MCP POPMaybe Good Die?
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SIPIDEA!!!
Overall ATE Market
ATE TAM History - Worldwide
6,5746,000
7,000
3 831
5,232
4,233
5,136
4,3204 000
5,000
($M
)
Memory ATE TAMSOC ATE TAMATE TAM
3,831
2,6032,348
3,4303,0743,000
4,000
Reve
nue
(
E i C i i
1,000
2,000 Economic Crisis
-1999 2000 2001 2002 2003 2004 2005 2006 2007 2008
IT Bubble
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Solution for Test COST
Higher Parallelism• Higher Parallelism
C t• Concurrent
P t l A• Protocol Aware
P Pi PMU• Per-Pin PMU
• Single Platform
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History of Multi Parallel Testing History of Multi Parallel Testing
64-site 256-site 512-site128-siteDRAM
2000 2002 2004 2006 2008 2010
2 or 4-site 16-site 32-site 64-site8-siteSOC
DRAM
• Multi-site capability is the key strategy to achieve low cost of test
• Test technology has been aligned to high site count parallel test strategy
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How to achieve Higher Parallelism How to achieve Higher Parallelism
SPCSmall Pin Count
IBCI l Bi CInternal Bit Compress
BOSTBOSTBuild off self-test
BISTBuilt-in self-test
DFTDesign for Testability
Today
Memory >512 site
Channel SharingATESOC >32 site
Channel SharingTIU
Test Interface Unit
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ATE Requirement for Higher Parallelism
Track Serial Data Rates - PCIe, SATAI P t D it
Track Serial Data Rates - PCIe, SATAI P t D it
New Higher Density Options for higher-site parallel Higher Performance for new technology
DigitalChannels
DigitalChannels
Increase Port DensityIncrease Port Density
Track HS DRAM Data RatesDDR2 DDR3/4 GDDR5Track HS DRAM Data RatesDDR2 DDR3/4 GDDR5
Increase Digital Pin Density. Track Mobile DDR Rates. ‘Protocol Aware’ features
Increase Digital Pin Density. Track Mobile DDR Rates. ‘Protocol Aware’ features
ChannelsChannels DDR2 DDR3/4 GDDR5DDR2 DDR3/4 GDDR5
AnalogChannelsAnalog
Channels
Track converter resolution and SNRCombine Audio, Baseband, Video capabilities
Increase so rce and digiti er densit
Track converter resolution and SNRCombine Audio, Baseband, Video capabilities
Increase so rce and digiti er densitIncrease source and digitizer densityIncrease source and digitizer density
Higher Density Power Suppliesfor Parallel Memory and SOC Test
Higher Density Power Suppliesfor Parallel Memory and SOC Test
DPSChannels
DPSChannels Higher Density DC (Per Pin PMU)
for Integrated Power Management FunctionsHigher Density DC (Per Pin PMU)
for Integrated Power Management Functions
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Solution for Test COST
Higher Parallelism• Higher Parallelism
C t• Concurrent
P t l A• Protocol Aware
P Pi PMU• Per-Pin PMU
• Single Platform
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Concurrent Testing- Device-Centric Test Time Reduction
Parallel test execution of independent functional cores in the device
SerializedFlow
2 LevelsConcurrency
3 LevelsConcurrency
Etc…
Core #1 Core
DUT
2 2 re
3 sts
ow
#1#2
Core #3
Cor
e #1
Te
sts
Cor
e #2
Test
s
Cor
e #1
Te
sts
re
3 sts
Cor
e #2
Test
s
Cor
e #1
Te
sts C
or #3Te
s
Test
Fl#3
*Device must be designed with independent cores
Cor
e #2
Te
sts
s
Co # 3
Tes
Tp
f CO f SOC Sf CO f SOC SC
ore
#3
Test
sBenefits: Reduce COT via parallel test of cores within a SOC or dies within a SIP
Characterize the operation of cores running simultaneouslyReduce Time to Market via re-use of modular test programs
Benefits: Reduce COT via parallel test of cores within a SOC or dies within a SIPCharacterize the operation of cores running simultaneouslyReduce Time to Market via re-use of modular test programs
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educe e o a e a e use o odu a es p og a seduce e o a e a e use o odu a es p og a s
Concurrent Testing - Independent Resources Per-Core
1 536MHz1900MHz
“Tester Slice” per“Tester Slice” per--CoreCore EnvironmentEnvironmentDC
InstrumentsDC
Instruments1.536MHzMicrowaveTransceiver Audio
ConvertersPLL
Instruments
ACInstruments
DigitalInstruments
ACInstruments
DigitalInstruments
9.5MHz 266MHzPMIC DDRInterface
DSP MCU Memory I/F
DigitalInstruments
DSP
DCInstruments
DigitalInstruments
DSP
Synchronous phase start of clocks and patternsComputer
AdvantagesI d d t t t d l t f
Advantages• Independent test development of each core
• Independent timing, signals, resources processing
• Able to synchronize across tests• Able to support concurrency with shared device resources
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resources, processing
Solution for Test COST
Higher Parallelism• Higher Parallelism
C t• Concurrent
P t l A• Protocol Aware
P Pi PMU• Per-Pin PMU
• Single Platform
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Chip Design Evolution
Tim
eD
esig
n T
CPU
Complex SOC
Mobile and B b d
Increasing Chip complexity
Baseaband
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g p p y
Async Chip Creates Non-Deterministic Test
DD
R6G
bps
DDR Interface
G 1.6
rfac
e
erfa
ce
PCI Express TMDS/HMDIPC
IE In
te
TDM
S In
teGraphics Processorp
16 Lanes2.5Gbps
3 Pairs1.6Gbps
Graphics Data Idle Graphics Data Idle Graphics DataPCI Express
RD Idle WR
Disp Data
DDR Interface
TDMS Interface
RD WR Idle WR Idle
Disp Data Disp Data Disp Data Idle Disp Data
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Async Chip Creates Non-Deterministic Test
DR bp
s
Protocol Synchronization & Communication
Protocol Aware ATEP
rotoco
Protoco
DDR Interface
GD
D1.
6GbProtocol Aware ATE l S
ynchroniza
ol Synchroniz
face
rfac
e
PCI Express TMDS/HMDI
ation & C
omm
zation & Com
PCIE
Inte
rf
TDM
S In
ter
Graphics ProcessorPCI Express
16 Lanes2.5Gbps
TMDS/HMDI3 Pairs
1.6Gbps
munication
mm
unication
T
Stored Response ATE Protocol Level ATEExecute fixed pass/fail vectors Interact with DUT using standard protocols
(PCI-E, I2C, USB, etc)Slave DUT to tester Adapt tester to DUT
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Convert Design Information to Tester Language
Use RTL level commands directly on tester
Protocol Aware attributes of a new solution
• Accommodate Functional Test: less 200DPM• Low test cost• Low test cost
• Fits the normal 5-10sec test model• No massive infrastructure changes
A d t N D t i i• Accommodate Non-Determinism• Minimum: Idle deletion• Preferred: Non-Deterministic Sequence
All h d i i i i d
Just Do It• Allow the device to operate in mission mode
• Reduce Time to Market• User operates at transaction levelp• Operates more like bench fixture• Test time reduced: Several Months Weeks
• Memory solutiony• Design verification through variable frequency for Mobile solution• Reusable application testing instead of SLT
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Solution for Test COST
Higher Parallelism• Higher Parallelism
C t• Concurrent
P t l A• Protocol Aware
P Pi PMU• Per-Pin PMU
• Single Platform
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DC Test Time is Becoming More Critical
Problem: As DRAM makers drive test costs down by reducing test time, DC test becomes a larger percentage of test time
60.0%
t e, C test beco es a a ge pe ce tage o test t e
40.0%
50.0%
me
Big Cost of Test Issue!
Major trends are
30.0%
DC
Tes
t Tim
Historically not a big problemTT Down
parallel-up and test time-down.
10.0%
20.0%% D problem
0.0%50 100 150 200 250 300
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Test Time (sec)
DC Test Cost Solution
DC Test Time is reduced drastically with Today’s solution – fast with no loss of test coverage or reduced quality.
50 0%
60.0%
40.0%
50.0%
Tim
e
Cost of Test Advantage:
20 0%
30.0%
% D
C T
est T
Cost of Test+ DC Test time is very
short+ No loss in DC test
coverage
10.0%
20.0%%
Per-Pin PMU
Shared PMUcoverage
+ Short test time at higher parallelism
0.0%50 100 150 200 250 300
Test Time (sec)
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Test Time (sec)
Solution for Test COST
Higher Parallelism• Higher Parallelism
C t• Concurrent
P t l A• Protocol Aware
P Pi PMU• Per-Pin PMU
• Single Platform
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Single platform Trend
GDDR DRAMGDDRDDR3
FLASHLPDDR Power
DRAM
FLASH PowerLPDDR Power
SOC RFSOC
IMAGE
RFSOC
IMAGE
RF
IMAGE
Multi Platform Single PlatformMulti Platform Single Platform• Optimizing current market requirement
• Easy concept
• Think next generation
• Less Investment
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• Short life cycle time • Long life cycle time (Reuse)
Conclusion - What is the cost saving way!Conclusion - What is the cost saving way!
BOST SLT (실장) ATE
Time to Market
Test Coverage
P iPrice
Upgrade Cost
Engineering toolsEngineering tools
Accuracy
Test Time
Utilization
# of Parallel
Life cycle
• ATE still provides cost effective way and huge benefit !!!
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p y g
Conclusion
• What is test? Cost!
• Cost down 요구는계속증가
• ATE has created new technology and solution. o Higher Parallelismo Concurrento Protocol Awareo Protocol Awareo Per-Pin PMUo Single Platform
• ATE keeps trying to find out a breakthrough!
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Thank you!
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