Test CostTest Cost절감을절감을위한위한Test Cost Test Cost 절감을절감을위한위한Test Item Test Item 선정선정정정

LG전자전준우책임연구원

LG Electronics 2008

Purpose

• Test Cost는회사이익에중요한역할을하는것으로서품질과신뢰성을보장하는범위에서 test cost reduction 작업은이루어져야한다.

• 이를위해서는 test setup 안정화와함께 test time reduction (TTR)이이루어져야한다.자 에서 대상 에서진행한 안정화• 본자료에서는대상 device에서진행한 test setup 안정화

와 TTR을위해적용된내용기술및양산 data를통해서분석및적용한결과를기술하였다분석및적용한결과를기술하였다.

Outline

• ASIC device test setup flow• ASIC device test setup flow

• Test cost reduction

• TEST에서의 Test Cost Reduction Methods

• 설계에서의 Test Cost Reduction Methods

ASIC device test setup flow

• General device test setup flowp

Probe Card Simulation (*1) Wafer TestProbe Card 제작

Design Fab

Simulation ( 1)

FT board Simulation (*1) FT setup

양산

FT board 제작Simulation (*1) p제작

*1: for high speed device*2: SLT (system level test) 추가진행

Test cost reduction

• Quality and Reliability를유지한상태에서 test cost를Quality and Reliability를유지한상태에서 test cost를줄이는모든방법으로서 design에서부터양산

까지모두고려되어야한다monitoring까지모두고려되어야한다

Figure. Cost of silicon manufacturing and test Figure. Cost of test challenge (verigy.com)

Test cost reduction

• Test setup안정화Test setup 안정화– 설계에서의 test setup 안정화

– Test에서의 test setup 안정화

• Test time reduction (TTR)– 설계에서의 TTR설계에서의 TTR

– Test에서의 TTR

적용 device

• ASIC1– 0.13um Digital to Analog converter SoC– ARM9 embedded– 16b DDR1 I/F @ 175Mhz– PLL 4종, 10bit ADC, 10bit 1ch-DAC– 256PBGA

• ASIC2– 65nm Digital to Analog converter SoC of 5M gates– ARM9 embedded9 e bedded– 16b DDR1 I/F @ 175Mhz– PLL 4종, 10bit ADC, 10bit 3ch-DAC– 256PBGA256PBGA

Figure. ASIC2 block diaram

Test에서의 test cost reduction

• Quality & reliability를만족하는 test setup• Test setup의안정화

– IDD등 test item 안정화를위한 H/W, S/W 대응

• Test에서의 TCR– Test house 선정시 ATE 단가

– Test time reduction (TTR)

– ATE별최대가능 multi-site test

– ATE별 test item별로 parallel test시 TTR영향고려– ATE별 test item별로 parallel test시 TTR 영향고려

– Concurrent test

– 양산 & 불량율 monitoring을통한 test item 최적화및재배치

– Wafer test item versus package test item 최적화

– Vector truncation

– Vector elimination

– Architectural methods

– Test program optimization

– 높은 first yield 유지

– Adaptive test flow

– Low cost ATE활용Low cost ATE 활용

Vector truncation (Maxwell 2006)

• 10% of the vector => 96% of failures• 10% of the AC scan vector => 62% of failures• Wafer test vector truncation• Package yield drop

Figure. Cumulative fallout of AC scan vectorsFigure. Cumulative fallout of stuck-at scan vectors

Vector elimination (Maxwell, 2007)

• ATPG tool generates patterns using an abstract model with no knowledge of the defect detection capability of the resultant tests

• In reality there are large differences in the effectiveness ofIn reality, there are large differences in the effectiveness of each pattern

• The three most effective tests detects 35 of the 41 failures, the i i t ib ti l 60 DPMremaining contributing only 60 DPM

Figure. Number of fails for each test

Multi-site test

• ATE별로 device에적용가능한최대multi-site수가다름• 고가의 ATE 적용시최대multi-site수와저가의 ATE에적용시최대multi-site 수를고려하여 COT를비교용시최대 수를 려하여 를비

• Multi-site수를늘리기위해 design에서 pin count를줄임• ATE specifation을넘어선경우에는 application을통해• ATE specifation을넘어선경우에는 application을통해대응

– Channel부족 : Photo-MOS relay사용Channel 부족 : Photo MOS relay사용– Analog channel 부족:

Concurrent test

• Tests are run in parallel within the same devicep• Major savings can be expected (rivoir, 2004)• Design have to be added for this modeg

SRAMFUNCPLL

SRAMFUNCPLL

ADCDAC

Figure Conventional test

ADCDAC

Figure Concurrent testFigure. Conventional test Figure. Concurrent test

Test order (Butler & Saxena,2000)

• Reordering tests to put the most time-effective first g pin the flow

• On one study, it showed an 8% decrease in test time• This method does not apply to fabless company

Low cost ATE

• Digital part에대해서는우수한비용절감g p• Analog part 및 debugging 관련해서는성능저하• ATE별여러제한사항에따라 TTR의효과가다름별여러제한사항에따라 의 과가다름

• High speed interface에서 loop back test

Figure. DVI loop back test load board Figure. DUT vs ATE trend

Wafer test vs package test

• Package test는최종단으로 full test적용Package test는최종단으로 full test 적용

• Vector truncation at wafer test

• Wafer test에서 yield 분석으로일부의 test item만적용

• wafer test에서 low speed test를적용p

• Wafer test에서저가의 ATE를사용

W f t t i ld가높은경우 f t t ki 을고려• Wafer test yield가높은경우 wafer test skip을고려

• FT yield drop에따른 package 손실비용고려

Special package tests (maxwell, 2007)

• Package test had to be repeated even though the die g p ghad been prescreened on wafer test (maxwell, 2002)

• Peripheral vector vs normal vector– Faults in the pad and pad logic– Faults in “logical proximity” to pad

F lt i h i l i it t d– Faults in physical proximity to pad

• The periphery set are not a satisfactory replacement

Stuck-at 641msTransition 710msStuck at physical 20ms

Fail regular scan physical logical

36 2 0 10Stuck-at physical 20msTransition physical 58msStuck-at logical 12msTransition logical 25msStuck-at pad 10ms

2311

0 0

0F il i h padTransition pad 18ms

Table. Execution times of tests Figure. Distribution of failed parts

Fail periphery pad

Voltage stress test

• Reliability Screeningy g• Test time & Test pattern & Test voltage• Foundry dependenty p• Stuck-at SCAN, MBIST• Outlier screenigOutlier screenig• 0.01% yield reduction (Maxwell, 2007)• Pre & Post screeningPre & Post screening

Analog test time reduction

• ADC & DAC TTR– AC, DC test item의선정– Sample 수의감소– Bit수의감소– Stabilization time의단축

• PLL TTR– 중복되는 test item의제거– Data 산포에영향을주지않는 Sampling 수의선정– Loop-back test를통한여러 pll의동시 test

T tTi S l C tTestTime vs Sample Count

0.8

1

1.2

1.4

Tim

e

0

0.2

0.4

0.6

1000

2000

3000

4000

5000

6000

7000

8000

9000

0000

1000

2000

3000

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7000

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9000

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Test

T

10 20 30 40 50 60 70 80 90 100

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Sample count

SPLL(175Mhz) FS(27Mhz) AuPLL(24Mhz) DPLL(27.1Mhz)

Figure. Test time vs sample count in PLL test

Adaptive test flow (Madge et al., 2005)

• In a variation of some techniques described , a q ,sample of die can be tested with a complete test, and depending on the yield, remaining die can be tested

ith d d twith a reduced set• From a TTR perspective, a die surrounded by good

die can be adequately tested with a reduced test setdie can be adequately tested with a reduced test set compared to one which is in a bad neighborhood

기타

• Eliminating redundant voltage conersg g• ATE 단가 (for fabless company)• Test program optimizationp g p• 높은 first yield 유지• Test frequency speed upTest frequency speed up• Test setup 안정화 (재현성확보)• Removing redundant test itemsRemoving redundant test items

설계에서의 test cost reduction

• 충분한설계마진을갖는 device를설계• 설계에서의안정화

– SI/ PI board simulation (high speed device)

– 설계안정화 (floating node 제거등)

– IDD 산포안정화를위한설계변경및벡터대응

• 설계에서의 TCR– DFT의강화 (Scan compression, At-speed MBIST with PLL)

F lt d l ( t k t ll d l t iti th d l b id i )– Fault model ( stuck-at, small delay transition, path delay, bridging )

– Concurrent Test Design

Loop-back test– Loop-back test

– MCP test mode 고려

SI/PI Simulation setup condition

• DDR Interface sim.Signal/Power Integrity with SSN

– I/O interface• Operating Frequency : 175 MHz

CLK/CLKB/DQ#/DM#/DQS#/Add /Ct l• CLK/CLKB/DQ#/DM#/DQS#/Addr./Ctrl.• Signal driving IBIS model / Signal receiving load C

– Write mode» 16bit data/Clk/Clk B/DQS signals simultaneous» 16bit data/Clk/Clk_B/DQS signals simultaneous

switching– Control mode

» Address /Control signals» Address /Control signals

– Power ripple check• +2.5v main2.5v main• +1.25v reference

• Rs damping resistor value tuning• Rs = 22 ohm• Rs = 15 ohm

SI/PI Simulation setup condition

Input Pogo probing• Package + FT Boardg– Pkg. 4 layer– FT Board 24 layer

Rs Damping Resistor

Die pad Signal output

SI/PI Simulation analysis target

• Power Integrity 검증– Pogo 단에서 2.5v power 인가후, DUT에서 signal transient 에의한

power ripple 관찰• Power plane 의 impedance resonance 확인

– Ground Bounce 에의한 1.25v Vref. ripple 관찰

• Signal Integrity검증• Signal Integrity 검증– Trace/via/pad/Rs 의 discontinued impedance 에의한 reflection 관찰

• DDR 의 Electrical spec. 만족여부확인Undershoot/overshoot• Undershoot/overshoot

– Trace length 차이에의한 skew 검증• CLK/DQS/DQ/DM 간의 timing margin확인• Test장비에서 delay/skew보정을위한정보제공• Test 장비에서 delay/skew 보정을위한정보제공

– Cross-talk 에의한 distortion 확인– Signal driving 시 power 공급이원활한지 check

<Micron의 DDR SDRAM datasheet 참고>

SI/PI Simulation DDR write mode

2.5V power

DQ#/DMDQS#

• ASIC2 에서 출력된 신호가 slot 의 pogo 에서 입력받는 파형을 추출한 결과

• Site1/2 가 동시에 data write mode 로 동

작시, 악조건으로 시뮬레이션한 결과임

• Site1/2 사이 DQ# 및 DM 간 delay 는

Rs=22ohmCLK Diff. probing

Vref. 1.25v

• Site1/2 사이 DQ# 및 DM 간 delay 는148ps 로 양호

1.25v

DQ#/DM 간 delay 차 = 약 148ps

• Clk/ClkB 의 single ended probing 결과는

2.5v power ripple 의 영향으로 좋지 않으

나 differential probing 의 결과가 양호하Rs=15ohm margin 이 높음

나, differential probing 의 결과가 양호하

기 때문에 동작상 문제없음.

SI/PI Simulation DDR addr/ctrl mode

Addr./Ctrl.•ASIC2 에서 출력된 신호가 slot 의 pogo 에서 입력받는 파형을 추출한 결과

• Site1/2 가 동시에 Addr./Ctrl. Signal 들이

switching 함.

Site1/2 사이 Addr # 및 Ctrl 간 delay 는

Rs=22ohmCLK Diff. probing

• Site1/2 사이 Addr.# 및 Ctrl. 간 delay 는169ps 로 양호

1.25v

Addr.#/Ctrl. 간 delay 차 = 약 169psRs=15ohm margin 이 높음Rs 15ohm margin 이 높음

Design for test

• Test quality, test time reduction q y,

Fault models

• Stuck-at fault– A line has a stuck-at fault if it has a fixed logic value regardless

of the change in input values of a circuit

• Bridging faultT li h ll i d d b– Two or more lines that are normally independent become connected when faulty

• Delay fault– Transition faultTransition fault– Path delay fault

Scan stitching

• Scan TestS t t di id hi ti i t t d hi h hift d t– Scan test divides chip operations into two mode, which are shift and capture.

– Shift mode : test patterns are applied or observed through scan chains which connect flip-flops serially.

– Capture mode : data evaluated by combinational logics at normal operation mode are latched to scan flip-flop.

Scan stitching

• Scan Compression– Architecture

data_in

test_si

data_out data_in data_out

d2a1T

test_so192 192

16 16

– Architecture

SCCOMP_DECOMPRESSOR

SCCOMP_COMPRESSORscan chain

sel

STPI VALID t t

**

STPI_VALIDSTPI_SOP

STPI_DATASTPI_CLKGPIO[0]TMOD_N

test_se

when TMOD_N = 0, {GPIO[0], STPI_CLK, STPI_DATA} = 3’b111test_se = STPI_VALIDad_scan_mode = STPI_SOP ( 1 : ScanCompression_mode,

0 : Internal_scan)

test modedecoding logic

Ad t– Advantage• Decrease test time and test data volume• Increase test quality when addressed ATE memory limitation problem

Di d t– Disadvantage• Area overhead : 10 gates per 1 sub scan chain

– Compression ratio : 10X

Scan flow (stuck-at test)

• Test Sequence– Test setup– Shift– Hold– Hold– Force PI– Measure PO– Capture– Reshift & Measure scan out

At-speed test

• Capture timing diagramp g g

launch capture shiftshift

At-speed test

• ATPG will target both Small Delay Defect (SDD) target faults and t t f ltnon-target faults

– Uses slack-based test generation for defined SDD target faults– Uses regular transition fault test generation for all others in fault listg g

• Slack-aware tests detect small-delay defects– ATPG selects observation path with lowest slack

Sl k d t f P i Ti– Slack data from Prime Time

ASIC2 floor plan

2.6V SSTL2 I/O * Physical mapMemory : 26%AIP : 12%

3.3V digital

AIP : 12%Logic : 62%

3.3V digital

AIP6

2.5V

AIP1AIP2

AIP3AIP4 AIP5

1.2V

ESD dummy

2.5V 1.2V 2.5V 1.2V 1.2V 1.2V digital, 1.2V analog, 3.3V digital

ESD dummy

Power Cut Cell

(PRCUTA or PRCUT)2.5V analog

(PRCUTA or PRCUT)

ASIC2 fault summary (Probe test)

O/S P/S IIL IPU IIL SIDD AIDD MBIST SCAN SC_TR SC_PATH SC_BR

1.602% 9.766% 0.689% 0.000% 0.576% 9.496% 0.811% 30.427% 38.571% 8.031% 0.020% 0.012%Per fail

* path delay pattern is covered 10ppm in wafer test and 132ppm in package test* Bridging pattern is covered 5~6ppm in wafer test and 5ppm in package test*sample is more than 6M

Total faults 90%(excluded AIP, DDR interface) Undetected fault : 10%

(AIP, DDR interface)

IIL, IPU, SIDD, AIDD, O/S, P/S 20.7%

Transition7.2%

Stuck-at35%

Bridging

Path delay0.02%

MBIST27.1%

Included PLL

0.012%

BIST clock, controller & collar

MBIST controller

• MBIST controllers automatically configured and y gassigned to memories based on several criteria / constraints including – Clock domains, Physical clustering, test time, power draw

적용결과

• ASIC1은 low cost ATE에서 ASIC2는 high cost ATE에서 setup• 각각현 device에서최대적용가능한multi site수를적용• FT TTR 적용결과

16 19% TTR– 16.19% TTR

Figure. TTR 적용결과 (Low cost ATE)

적용결과

• FT Multi-site & TTR & ATE별적용결과– 19.3% TTR, +4.8% 증가

Figure Low cost ATE vs high cost ATEFigure. Low cost ATE vs high cost ATE Figure. Multi site 적용결과

적용결과

• FT TCR 적용결과

Figure TTR적용결과Figure Low cost ATE vs high cost ATE (single비교시) Figure. TTR 적용결과Figure. Low cost ATE vs high cost ATE (single 비교시)

적용결과

• EDS TTR 적용결과

Figure. TTR 적용결과비교 (Low cost ATE)Figure. TTR 적용결과 (Low cost ATE)

적용결과

• EDS ATE별 TTR 적용결과– 18.35% 증가, 7% 증가

Figure. Low cost ATE single vs High cost ATE quad Figure. High cost ATE single vs quad

적용결과

• EDS ATE별 TTR 적용결과

Figure. TTR 적용결과비교Figure. Low cost ATE single vs High cost ATE quad to single

Conclusion

• 65nm 공정에서 path-delay fault, bridging fault의결과p y , g g• 여러종류의 TTR 기법을확인• Analog part와 digital part의 setup 조건에따라다르나g p 와 g p 의 p 건에따라다 나일반적으로 low cost ATE 보다 high cost ATE의multi site 활용이 TCR 효과큼

• 양산 yield monitoring을통한 wafer test item의선택적용이 TCR 효과큼

Acknowledgement

• 이용 (DFT)( )• 송태림 (SI/PI simulation)• 이동준 (Q/A)이동준 (Q )• 옥재철 (Design)• 강용석강용석

• 홍승일

Thank you all !

참고문헌

• Peter Maxwell, “Principles and Results of Some Test , pCost Reduction Methods for ASICs”, Proc. IEEE International Test Conference, pp1-5, 2007.

• Jochen Rivoir, “Parallel Test Reduces Cost of Test More Effectively Than Just a Cheap Tester”, Proc. IEEE International Test Conference pp1 12 2004IEEE International Test Conference, pp1-12, 2004.

• Robert Madge et al., “The Value of Statistical Testing for Quality Yield and Test Cost Improvement” Procfor Quality, Yield and Test Cost Improvement , Proc. IEEE International Test Conference, pp1-10, 2005.