tsramakrishnan_resume.pdf

8/14/2019 TSRamakrishnan_Resume.pdf

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T.S.Ramakrishnan

[email protected]

+91-9500039681

Objective: To work with a technically motivated team and strive for professional excellence in EDI.

Summary:

3.5 years of experience in EDI (Electronic Data Interchange) cross-platformcommunications and infrastructure management.

Well acquainted with debugging and troubleshooting of AS2, SMT/POP and FTP basedapplications.

Good knowledge of business transaction flow in supply chain management.

Experience with working on Mainframe, Linux, Unix and Windows platforms.

A 2012 Microelectronics MS graduate from Newcastle University, UK.

Certified in VLSI design and verification by Maven Silicon.

Professional / Work experience

Organization: Infosys Bangalore

Duration: 20072011

Was inducted into Infosys through a campus placement drive and post training in Mainframetechnologies was allocated to the Ingram Microproject in the EDIdomain.

The project focussed on the production support and maintenance of the clients EDI based businesstransaction processing servers and the associated transaction processing software components.

Established and maintained communications between the clients EDI servers (both internaland external) and clients external trading partners communication servers on the FTP,AS2/AS1, VAN (Value added network) and Connect Direct platforms. Won Fresher of the

Quarter award for reduced the turnaround time of communication requests by 75%.

Analysed and fixed issues in production runs of EDI jobs on Mainframe and on Unixplatforms. Actively reduced the issue ticket count by 50%and communication requests inthe active pipeline by 62%.

Implemented high impact changes in productionEDI transaction processing systems on the

Gentran platform. Developed and tested changes in transaction processing maps on TIBCO tools.

Provided technical training to project stake holders at client and offshore locations andmanaged the knowledge transferral through documentation of the projects technologies andprocess.

Managed the work allocation of the offshore EDI Infrastructure team.

Programming languages

C/C++

System Verilog

Verilog VHDL
mailto:[email protected]:[email protected]:[email protected]:[email protected]


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Communication protocols

FTP

HTTP/HTTPS

C:DConnect Direct

RS-232

SPI

Projects

Pipeline mechanism for a vector architecture:Designed an Instruction set architecture (ISA) and the associated pipelinedvector data-pathbased on the standard MIPSarchitecture. The design was implemented on VHDLwithsynthesis targeted for an Altera Flex10KFPGA based on the .42 umprocess technology.

Physical design of a MS DFF:A Master-Slave D flip-flop was designed using invertersand tri-stateinverters.Schematic capture was performed on Cadence Virtuoso. The devices were manually laid

out usingCadenceslayout editor. DRCagainst a 90 nm process and LVSchecks wereperformed using Cadence tools. Parameterization of rise and fall times, drive strength wasperformed using a SPICElevel simulation carried out on Cadence Spectre.

Design and verification of an alarm clock module:An industrial standard alarm clock design was implemented on Verilog with synthesis aimedat a Xilinx SpartanFPGA. Atest environment based on the UVMframework, implementedon System Verilog was used for functional verificationof the design.

Digital design of a FIR low-pass filter accelerator:A FIR LPFaccelerator which exchanged data using the RS-232 protocol was designed.Design implementation was on VHDL with synthesis targeted for an Altera Flex10K FPGA.

Devising 90nm CMOS transistors:ORCADwas used to parameterize and analyse shrinkage of N-FET and P-FETs leading upto 90nmdevices. Short-channel effects due to further scaling were studied and solutionswere analysed and implemented for further scaling leading to 50nmgate length devices.

Educational qualification

Stage Grade

MSc Microelectronics, - 2:1 (67.8%)Newcastle University (2012)

B.E. ECE, - 65.06%Visveswaraiah Technological University (2007)

2nd

P.U.C, Karnataka Board - 85%

X, ICSE - 77%

Accomplishments

Represented my college in a paper presentation meeting of the IEEE student body. Thepresentation was on Field programmable nanowire interconnects.

Conducted blood camps at the academic level.

An active member of 2 NGOsiPledge and Swarg.

An active member of the quizzing and gaming teams at the academic and professional levels

and have conducted inter-collegiate tournaments in the same events. Won Fresher of the Quarter award at Infosys.


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Personal Details

Date of birth: 08thFebruary, 1986

Fathers Name: Mr T.V.Swaminathan

ContactE-mail: [email protected]

Mobile: +91-9500039681

Postal address: 10, Third floor, Prashanthi Apartments,Parangusapuram Street, Rangarajapuram,Kodambakkam, Chennai - 600024

tsramakrishnan_resume.pdf

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